decoder.isa revision 2469
1// -*- mode:c++ -*- 2 3//////////////////////////////////////////////////////////////////// 4// 5// The actual MIPS32 ISA decoder 6// ----------------------------- 7// The following instructions are specified in the MIPS32 ISA 8// Specification. Decoding closely follows the style specified 9// in the MIPS32 ISAthe specification document starting with Table 10// A-2 (document available @ www.mips.com) 11// 12//@todo: Distinguish "unknown/future" use insts from "reserved" 13// ones 14decode OPCODE_HI default Unknown::unknown() { 15 16 // Derived From ... Table A-2 MIPS32 ISA Manual 17 0x0: decode OPCODE_LO { 18 19 0x0: decode FUNCTION_HI { 20 0x0: decode FUNCTION_LO { 21 0x1: decode MOVCI { 22 format BasicOp { 23 0: movf({{ if (xc->readMiscReg(FPCR) != CC) Rd = Rs}}); 24 1: movt({{ if (xc->readMiscReg(FPCR) == CC) Rd = Rs}}); 25 } 26 } 27 28 format BasicOp { 29 30 //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 31 //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." 32 33 0x0: decode RS { 34 0x0: sll({{ Rd = Rt.uw << SA; }}); 35 //0x0:nop({{ ; }}); //really sll r0,r0,0 36 // 0x1:ssnop({{ ; }});//really sll r0,r0,1 37 // 0x3:ehb({{ ; }}); //really sll r0,r0,3 38 } 39 40 0x2: decode SRL { 41 0: srl({{ Rd = Rt.uw >> SA; }}); 42 43 //Hardcoded assuming 32-bit ISA, probably need parameter here 44 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 45 } 46 47 0x3: sra({{ Rd = Rt.sw >> SA; }}); 48 49 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 50 51 0x6: decode SRLV { 52 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 53 54 //Hardcoded assuming 32-bit ISA, probably need parameter here 55 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 56 } 57 58 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); 59 } 60 } 61 62 0x1: decode FUNCTION_LO { 63 64 //Table A-3 Note: "Specific encodings of the hint field are used 65 //to distinguish JR from JR.HB and JALR from JALR.HB" 66 format Jump { 67 0x0: decode HINT { 68 0:jr({{ NNPC = Rs & ~1; }},IsReturn); 69 70 1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn); 71 } 72 73 0x1: decode HINT { 74 0: jalr({{ NNPC = Rs; }},IsCall,IsReturn); 75 76 1: jalr_hb({{ NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn); 77 } 78 } 79 80 format BasicOp { 81 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 82 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 83 } 84 85 format WarnUnimpl { 86 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative 87 0x5: break(); 88 0x7: sync(); 89 } 90 } 91 92 0x2: decode FUNCTION_LO { 93 format BasicOp { 94 0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }}); 95 0x1: mthi({{ xc->setMiscReg(Hi,Rs); }}); 96 0x2: mflo({{ Rd = xc->readMiscReg(Lo); }}); 97 0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }}); 98 } 99 } 100 101 0x3: decode FUNCTION_LO { 102 format IntOp { 103 0x0: mult({{ 104 int64_t temp1 = Rs.sw * Rt.sw; 105 xc->setMiscReg(Hi,temp1<63:32>); 106 xc->setMiscReg(Lo,temp1<31:0>); 107 }}); 108 109 0x1: multu({{ 110 int64_t temp1 = Rs.uw * Rt.uw; 111 xc->setMiscReg(Hi,temp1<63:32>); 112 xc->setMiscReg(Lo,temp1<31:0>); 113 }}); 114 115 0x2: div({{ 116 xc->setMiscReg(Hi,Rs.sw % Rt.sw); 117 xc->setMiscReg(Lo,Rs.sw / Rt.sw); 118 }}); 119 120 0x3: divu({{ 121 xc->setMiscReg(Hi,Rs.uw % Rt.uw); 122 xc->setMiscReg(Lo,Rs.uw / Rt.uw); 123 }}); 124 } 125 } 126 127 0x4: decode FUNCTION_LO { 128 format IntOp { 129 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}}); 130 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 131 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}}); 132 0x3: subu({{ Rd.sw = Rs.sw - Rt.uw;}}); 133 0x4: and({{ Rd = Rs & Rt;}}); 134 0x5: or({{ Rd = Rs | Rt;}}); 135 0x6: xor({{ Rd = Rs ^ Rt;}}); 136 0x7: nor({{ Rd = ~(Rs | Rt);}}); 137 } 138 } 139 140 0x5: decode FUNCTION_LO { 141 format IntOp{ 142 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 143 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 144 } 145 } 146 147 0x6: decode FUNCTION_LO { 148 format Trap { 149 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 150 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 151 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 152 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 153 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 154 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 155 } 156 } 157 } 158 159 0x1: decode REGIMM_HI { 160 0x0: decode REGIMM_LO { 161 format Branch { 162 0x0: bltz({{ cond = (Rs.sw < 0); }}); 163 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 164 } 165 166 format BranchLikely { 167 //MIPS obsolete instructions 168 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 169 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 170 } 171 } 172 173 0x1: decode REGIMM_LO { 174 format Trap { 175 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 176 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 177 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 178 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 179 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 180 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 181 } 182 } 183 184 0x2: decode REGIMM_LO { 185 format Branch { 186 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn); 187 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn); 188 } 189 190 format BranchLikely { 191 //Will be removed in future MIPS releases 192 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn); 193 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn); 194 } 195 } 196 197 0x3: decode REGIMM_LO { 198 format WarnUnimpl { 199 0x7: synci(); 200 } 201 } 202 } 203 204 format Jump { 205 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 206 207 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn); 208 } 209 210 format Branch { 211 0x4: beq({{ cond = (Rs.sw == Rt.sw); }}); 212 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 213 0x6: blez({{ cond = (Rs.sw <= 0); }}); 214 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 215 } 216 } 217 218 0x1: decode OPCODE_LO { 219 format IntOp { 220 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}}); 221 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 222 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 223 0x3: sltiu({{ Rt.sw = ( Rs.sw < imm ) ? 1 : 0 }}); 224 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); 225 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); 226 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); 227 0x7: lui({{ Rt = INTIMM << 16}}); 228 } 229 } 230 231 0x2: decode OPCODE_LO { 232 233 //Table A-11 MIPS32 COP0 Encoding of rs Field 234 0x0: decode RS_MSB { 235 0x0: decode RS { 236 format System { 237 0x0: mfc0({{ 238 //uint64_t reg_num = Rd.uw; 239 240 Rt = xc->readMiscReg(RD << 5 | SEL); 241 }}); 242 243 0x4: mtc0({{ 244 //uint64_t reg_num = Rd.uw; 245 246 xc->setMiscReg(RD << 5 | SEL,Rt); 247 }}); 248 249 0x8: mftr({{ 250 //The contents of the coprocessor 0 register specified by the 251 //combination of rd and sel are loaded into general register 252 //rt. Note that not all coprocessor 0 registers support the 253 //sel field. In those instances, the sel field must be zero. 254 255 //MT Code Needed Here 256 }}); 257 258 0xC: mttr({{ 259 //The contents of the coprocessor 0 register specified by the 260 //combination of rd and sel are loaded into general register 261 //rt. Note that not all coprocessor 0 registers support the 262 //sel field. In those instances, the sel field must be zero. 263 264 //MT Code Needed Here 265 }}); 266 267 268 0xA: rdpgpr({{ 269 //Accessing Previous Shadow Set Register Number 270 //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/; 271 //uint64_t reg_num = Rt.uw; 272 273 //Rd = xc->regs.IntRegFile[prev]; 274 //Rd = xc->shadowIntRegFile[prev][reg_num]; 275 }}); 276 277 0xB: decode RD { 278 279 0x0: decode SC { 280 0x0: dvpe({{ 281 Rt.sw = xc->readMiscReg(MVPControl); 282 xc->setMiscReg(MVPControl,0); 283 }}); 284 285 0x1: evpe({{ 286 Rt.sw = xc->readMiscReg(MVPControl); 287 xc->setMiscReg(MVPControl,1); 288 }}); 289 } 290 291 0x1: decode SC { 292 0x0: dmt({{ 293 Rt.sw = xc->readMiscReg(VPEControl); 294 xc->setMiscReg(VPEControl,0); 295 }}); 296 297 0x1: emt({{ 298 Rt.sw = xc->readMiscReg(VPEControl); 299 xc->setMiscReg(VPEControl,1); 300 }}); 301 } 302 303 0xC: decode SC { 304 0x0: di({{ 305 Rt.sw = xc->readMiscReg(Status); 306 xc->setMiscReg(Status,0); 307 }}); 308 309 0x1: ei({{ 310 Rt.sw = xc->readMiscReg(Status); 311 xc->setMiscReg(Status,1); 312 }}); 313 } 314 } 315 316 0xE: wrpgpr({{ 317 //Accessing Previous Shadow Set Register Number 318 //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/); 319 //uint64_t reg_num = Rd.uw; 320 321 //xc->regs.IntRegFile[prev]; 322 //xc->shadowIntRegFile[prev][reg_num] = Rt; 323 }}); 324 } 325 } 326 327 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 328 0x1: decode FUNCTION { 329 format System { 330 0x01: tlbr({{ }}); 331 0x02: tlbwi({{ }}); 332 0x06: tlbwr({{ }}); 333 0x08: tlbp({{ }}); 334 } 335 336 format WarnUnimpl { 337 0x18: eret(); 338 0x1F: deret(); 339 0x20: wait(); 340 } 341 } 342 } 343 344 //Table A-13 MIPS32 COP1 Encoding of rs Field 345 0x1: decode RS_MSB { 346 347 0x0: decode RS_HI { 348 0x0: decode RS_LO { 349 format FloatOp { 350 0x0: mfc1({{ /*Rt.uw = Fs.ud<31:0>;*/ }}); 351 0x2: cfc1({{ /*Rt.uw = xc->readMiscReg(FPCR[Fs]);*/}}); 352 0x3: mfhc1({{ /*Rt.uw = Fs.ud<63:32>*/;}}); 353 0x4: mtc1({{ /*Fs = Rt.uw*/}}); 354 0x6: ctc1({{ /*xc->setMiscReg(FPCR[Fs],Rt);*/}}); 355 0x7: mthc1({{ /*Fs<63:32> = Rt.uw*/}}); 356 } 357 } 358 359 0x1: decode ND { 360 0x0: decode TF { 361 format Branch { 362 0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 363 0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 364 } 365 } 366 367 0x1: decode TF { 368 format BranchLikely { 369 0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 370 0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 371 } 372 } 373 } 374 } 375 376 0x1: decode RS_HI { 377 0x2: decode RS_LO { 378 379 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 380 //(( single-word )) 381 0x0: decode RS_HI { 382 0x0: decode RS_LO { 383 format FloatOp { 384 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); 385 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); 386 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); 387 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); 388 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); 389 0x5: abss({{ Fd.sf = fabs(Fs.sf);}}); 390 0x6: movs({{ Fd.sf = Fs.sf;}}); 391 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); 392 } 393 } 394 395 0x1: decode RS_LO { 396 //only legal for 64 bit-FP 397 format Float64Op { 398 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}}); 399 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}}); 400 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}}); 401 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}}); 402 } 403 404 format FloatOp { 405 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}}); 406 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}}); 407 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}}); 408 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}}); 409 } 410 } 411 412 0x2: decode RS_LO { 413 0x1: decode MOVCF { 414 format FloatOp { 415 0x0: movfs({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); 416 0x1: movts({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); 417 } 418 } 419 420 format BasicOp { 421 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 422 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); 423 } 424 425 format Float64Op { 426 0x5: recips({{ Fd = 1 / Fs; }}); 427 0x6: rsqrts({{ Fd = 1 / sqrt((double)Fs.ud);}}); 428 } 429 } 430 431 0x4: decode RS_LO { 432 433 format FloatOp { 434 0x1: cvt_d_s({{ int rnd_mode = xc->readMiscReg(FCSR); 435 Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE); 436 }}); 437 438 0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR); 439 Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE); 440 }}); 441 } 442 443 //only legal for 64 bit 444 format Float64Op { 445 0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR); 446 Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE); 447 }}); 448 449 0x6: cvt_ps_s({{ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/ }}); 450 } 451 } 452 } 453 454 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 455 0x1: decode RS_HI { 456 0x0: decode RS_LO { 457 format FloatOp { 458 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 459 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 460 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 461 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 462 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 463 0x5: absd({{ Fd.df = fabs(Fs.df);}}); 464 0x6: movd({{ Fd.df = Fs.df;}}); 465 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 466 } 467 } 468 469 0x1: decode RS_LO { 470 //only legal for 64 bit 471 format Float64Op { 472 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 473 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}}); 474 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}}); 475 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}}); 476 } 477 478 format FloatOp { 479 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 480 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }}); 481 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }}); 482 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }}); 483 } 484 } 485 486 0x2: decode RS_LO { 487 0x1: decode MOVCF { 488 format FloatOp { 489 0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }}); 490 0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }}); 491 } 492 } 493 494 format BasicOp { 495 0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }}); 496 0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }}); 497 } 498 499 format Float64Op { 500 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 501 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 502 } 503 } 504 505 0x4: decode RS_LO { 506 format FloatOp { 507 0x0: cvt_s_d({{ 508 int rnd_mode = xc->readMiscReg(FCSR); 509 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE); 510 }}); 511 512 0x4: cvt_w_d({{ 513 int rnd_mode = xc->readMiscReg(FCSR); 514 Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE); 515 }}); 516 } 517 518 //only legal for 64 bit 519 format Float64Op { 520 0x5: cvt_l_d({{ 521 int rnd_mode = xc->readMiscReg(FCSR); 522 Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE); 523 }}); 524 } 525 } 526 } 527 528 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 529 0x4: decode FUNCTION { 530 format FloatOp { 531 0x20: cvt_s({{ 532 int rnd_mode = xc->readMiscReg(FCSR); 533 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); 534 }}); 535 536 0x21: cvt_d({{ 537 int rnd_mode = xc->readMiscReg(FCSR); 538 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); 539 }}); 540 } 541 } 542 543 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 544 //Note: "1. Format type L is legal only if 64-bit floating point operations 545 //are enabled." 546 0x5: decode FUNCTION_HI { 547 format FloatOp { 548 0x10: cvt_s_l({{ 549 int rnd_mode = xc->readMiscReg(FCSR); 550 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG); 551 }}); 552 553 0x11: cvt_d_l({{ 554 int rnd_mode = xc->readMiscReg(FCSR); 555 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG); 556 }}); 557 } 558 } 559 560 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 561 //Note: "1. Format type PS is legal only if 64-bit floating point operations 562 //are enabled. " 563 0x6: decode RS_HI { 564 0x0: decode RS_LO { 565 format Float64Op { 566 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 567 //Lower Halves Independently but we take simulator shortcut 568 Fd.df = Fs.df + Ft.df; 569 }}); 570 571 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 572 //Lower Halves Independently but we take simulator shortcut 573 Fd.df = Fs.df - Ft.df; 574 }}); 575 576 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 577 //Lower Halves Independently but we take simulator shortcut 578 Fd.df = Fs.df * Ft.df; 579 }}); 580 581 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 582 //Lower Halves Independently but we take simulator shortcut 583 Fd.df = fabs(Fs.df); 584 }}); 585 586 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 587 //Lower Halves Independently but we take simulator shortcut 588 //Fd.df = Fs<31:0> | Ft<31:0>; 589 }}); 590 591 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 592 //Lower Halves Independently but we take simulator shortcut 593 Fd.df = -1 * Fs.df; 594 }}); 595 } 596 } 597 598 0x2: decode RS_LO { 599 0x1: decode MOVCF { 600 format Float64Op { 601 0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}}); 602 0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); 603 } 604 } 605 606 format BasicOp { 607 0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); 608 0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }}); 609 } 610 611 } 612 613 0x4: decode RS_LO { 614 0x0: Float64Op::cvt_s_pu({{ 615 int rnd_mode = xc->readMiscReg(FCSR); 616 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI); 617 }}); 618 } 619 620 0x5: decode RS_LO { 621 format Float64Op { 622 0x0: cvt_s_pl({{ 623 int rnd_mode = xc->readMiscReg(FCSR); 624 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO); 625 }}); 626 0x4: pll({{ /*Fd.df = Fs<31:0> | Ft<31:0>*/}}); 627 0x5: plu({{ /*Fd.df = Fs<31:0> | Ft<63:32>*/}}); 628 0x6: pul({{ /*Fd.df = Fs<63:32> | Ft<31:0>*/}}); 629 0x7: puu({{ /*Fd.df = Fs<63:32 | Ft<63:32>*/}}); 630 } 631 } 632 } 633 } 634 } 635 } 636 637 //Table A-19 MIPS32 COP2 Encoding of rs Field 638 0x2: decode RS_MSB { 639 0x0: decode RS_HI { 640 0x0: decode RS_LO { 641 format WarnUnimpl { 642 0x0: mfc2(); 643 0x2: cfc2(); 644 0x3: mfhc2(); 645 0x4: mtc2(); 646 0x6: ctc2(); 647 0x7: mftc2(); 648 } 649 } 650 651 0x1: decode ND { 652 0x0: decode TF { 653 format WarnUnimpl { 654 0x0: bc2f(); 655 0x1: bc2t(); 656 } 657 } 658 659 0x1: decode TF { 660 format WarnUnimpl { 661 0x0: bc2fl(); 662 0x1: bc2tl(); 663 } 664 } 665 } 666 } 667 } 668 669 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 670 //Note: "COP1X instructions are legal only if 64-bit floating point 671 //operations are enabled." 672 0x3: decode FUNCTION_HI { 673 0x0: decode FUNCTION_LO { 674 format LoadMemory2 { 675 0x0: lwxc1({{ EA = Rs + Rt; }},{{ /*F_t<31:0> = Mem.sf; */}}); 676 0x1: ldxc1({{ EA = Rs + Rt; }},{{ /*F_t<63:0> = Mem.df;*/ }}); 677 0x5: luxc1({{ //Need to make EA<2:0> = 0 678 EA = Rs + Rt; 679 }}, 680 {{ /*F_t<31:0> = Mem.df; */}}); 681 } 682 } 683 684 0x1: decode FUNCTION_LO { 685 format StoreMemory2 { 686 0x0: swxc1({{ EA = Rs + Rt; }},{{ /*Mem.sf = Ft<31:0>; */}}); 687 0x1: sdxc1({{ EA = Rs + Rt; }},{{ /*Mem.df = Ft<63:0> */}}); 688 0x5: suxc1({{ //Need to make EA<2:0> = 0 689 EA = Rs + Rt; 690 }}, 691 {{ /*Mem.df = F_t<63:0>;*/}}); 692 } 693 694 0x7: WarnUnimpl::prefx(); 695 } 696 697 format FloatOp { 698 0x3: WarnUnimpl::alnv_ps(); 699 700 format BasicOp { 701 0x4: decode FUNCTION_LO { 702 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 703 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 704 0x6: madd_ps({{ 705 //Must Check for Exception Here... Supposed to Operate on Upper and 706 //Lower Halves Independently but we take simulator shortcut 707 Fd.df = (Fs.df * Fs.df) + Fr.df; 708 }}); 709 } 710 711 0x5: decode FUNCTION_LO { 712 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 713 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 714 0x6: msub_ps({{ 715 //Must Check for Exception Here... Supposed to Operate on Upper and 716 //Lower Halves Independently but we take simulator shortcut 717 Fd.df = (Fs.df * Fs.df) - Fr.df; 718 }}); 719 } 720 721 0x6: decode FUNCTION_LO { 722 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 723 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 724 0x6: nmadd_ps({{ 725 //Must Check for Exception Here... Supposed to Operate on Upper and 726 //Lower Halves Independently but we take simulator shortcut 727 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 728 }}); 729 } 730 731 0x7: decode FUNCTION_LO { 732 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 733 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 734 0x6: nmsub_ps({{ 735 //Must Check for Exception Here... Supposed to Operate on Upper and 736 //Lower Halves Independently but we take simulator shortcut 737 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 738 }}); 739 } 740 } 741 } 742 } 743 744 //MIPS obsolete instructions 745 format BranchLikely { 746 0x4: beql({{ cond = (Rs.sw == 0); }}); 747 0x5: bnel({{ cond = (Rs.sw != 0); }}); 748 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 749 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 750 } 751 } 752 753 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 754 755 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 756 0x4: decode FUNCTION_HI { 757 758 0x0: decode FUNCTION_LO { 759 format IntOp { 760 0x0: madd({{ 761 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 762 temp1 = temp1 + (Rs.sw * Rt.sw); 763 xc->setMiscReg(Hi,temp1<63:32>); 764 xc->setMiscReg(Lo,temp1<31:0>); 765 }}); 766 767 0x1: maddu({{ 768 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 769 temp1 = temp1 + (Rs.uw * Rt.uw); 770 xc->setMiscReg(Hi,temp1<63:32>); 771 xc->setMiscReg(Lo,temp1<31:0>); 772 }}); 773 774 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 775 776 0x4: msub({{ 777 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 778 temp1 = temp1 - (Rs.sw * Rt.sw); 779 xc->setMiscReg(Hi,temp1<63:32>); 780 xc->setMiscReg(Lo,temp1<31:0>); 781 }}); 782 783 0x5: msubu({{ 784 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 785 temp1 = temp1 - (Rs.uw * Rt.uw); 786 xc->setMiscReg(Hi,temp1<63:32>); 787 xc->setMiscReg(Lo,temp1<31:0>); 788 }}); 789 } 790 } 791 792 0x4: decode FUNCTION_LO { 793 format BasicOp { 794 0x0: clz({{ 795 /*int cnt = 0; 796 int idx = 0; 797 while ( Rs.uw<idx> != 1) { 798 cnt++; 799 idx--; 800 } 801 802 Rd.uw = cnt;*/ 803 }}); 804 805 0x1: clo({{ 806 /*int cnt = 0; 807 int idx = 0; 808 while ( Rs.uw<idx> != 0) { 809 cnt++; 810 idx--; 811 } 812 813 Rd.uw = cnt;*/ 814 }}); 815 } 816 } 817 818 0x7: decode FUNCTION_LO { 819 0x7: WarnUnimpl::sdbbp(); 820 } 821 } 822 823 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 824 0x7: decode FUNCTION_HI { 825 826 0x0: decode FUNCTION_LO { 827 format WarnUnimpl { 828 0x1: ext(); 829 0x4: ins(); 830 } 831 } 832 833 0x1: decode FUNCTION_LO { 834 format WarnUnimpl { 835 0x0: fork(); 836 0x1: yield(); 837 } 838 } 839 840 841 //Table A-10 MIPS32 BSHFL Encoding of sa Field 842 0x4: decode SA { 843 844 0x02: WarnUnimpl::wsbh(); 845 846 format BasicOp { 847 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}}); 848 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}}); 849 } 850 } 851 852 0x6: decode FUNCTION_LO { 853 0x7: BasicOp::rdhwr({{ /*Rt = xc->hwRegs[RD];*/ }}); 854 } 855 } 856 } 857 858 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 859 format LoadMemory { 860 0x0: lb({{ Rt.sw = Mem.sb; }}); 861 0x1: lh({{ Rt.sw = Mem.sh; }}); 862 0x2: lwl({{ Rt.sw = Mem.sw; }});//, WordAlign); 863 0x3: lw({{ Rt.sw = Mem.sb; }}); 864 0x4: lbu({{ Rt.uw = Mem.ub; }}); 865 0x5: lhu({{ Rt.uw = Mem.uh; }}); 866 0x6: lwr({{ Rt.uw = Mem.uw; }});//, WordAlign); 867 } 868 869 0x7: FailUnimpl::reserved(); 870 } 871 872 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 873 format StoreMemory { 874 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 875 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 876 0x2: swl({{ Mem.ub = Rt<31:0>; }});//,WordAlign); 877 0x3: sw({{ Mem.ub = Rt<31:0>; }}); 878 0x6: swr({{ Mem.ub = Rt<31:0>; }});//,WordAlign); 879 } 880 881 format WarnUnimpl { 882 0x7: cache(); 883 } 884 885 } 886 887 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 888 0x0: WarnUnimpl::ll(); 889 890 format LoadMemory { 891 0x1: lwc1({{ /*F_t<31:0> = Mem.sf; */}}); 892 0x5: ldc1({{ /*F_t<63:0> = Mem.df; */}}); 893 } 894 } 895 896 897 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 898 0x0: WarnUnimpl::sc(); 899 900 format StoreMemory { 901 0x1: swc1({{ //Mem.sf = Ft<31:0>; }}); 902 0x5: sdc1({{ //Mem.df = Ft<63:0>; }}); 903 } 904 } 905} 906 907 908