decoder.isa revision 2100
1// -*- mode:c++ -*- 2 3//////////////////////////////////////////////////////////////////// 4// 5// The actual MIPS32 ISA decoder 6// ----------------------------- 7// The following instructions are specified in the MIPS32 ISA 8// Specification. Decoding closely follows the style specified 9// in the MIPS32 ISAthe specification document starting with Table 10// A-2 (document available @ www.mips.com) 11// 12//@todo: Distinguish "unknown/future" use insts from "reserved" 13// ones 14decode OPCODE_HI default Unknown::unknown() { 15 16 // Derived From ... Table A-2 MIPS32 ISA Manual 17 0x0: decode OPCODE_LO default FailUnimpl::reserved(){ 18 19 0x0: decode FUNCTION_HI { 20 0x0: decode FUNCTION_LO { 21 0x1: decode MOVCI { 22 format BasicOp { 23 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}}); 24 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}}); 25 } 26 } 27 28 format BasicOp { 29 30 //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 31 //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." 32 33 0x0: sll({{ Rd = Rt.uw << SA; }}); 34 35 0x2: decode SRL { 36 0: srl({{ Rd = Rt.uw >> SA; }}); 37 38 //Hardcoded assuming 32-bit ISA, probably need parameter here 39 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 40 } 41 42 0x3: sra({{ Rd = Rt.sw >> SA; }}); 43 44 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 45 46 0x6: decode SRLV { 47 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 48 49 //Hardcoded assuming 32-bit ISA, probably need parameter here 50 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 51 } 52 53 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); 54 } 55 } 56 57 0x1: decode FUNCTION_LO { 58 59 //Table A-3 Note: "Specific encodings of the hint field are used 60 //to distinguish JR from JR.HB and JALR from JALR.HB" 61 format Jump { 62 0x0: jr(IsReturn); 63 0x1: jalr(IsCall,IsReturn); 64 } 65 66 format BasicOp { 67 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 68 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 69 } 70 71 72 format WarnUnimpl { 73 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative 74 0x5: break(); 75 0x7: sync(); 76 } 77 } 78 79 0x2: decode FUNCTION_LO { 80 format BasicOp { 81 0x0: mfhi({{ Rd = xc->miscRegs.hi; }}); 82 0x1: mthi({{ xc->miscRegs.hi = Rs; }}); 83 0x2: mflo({{ Rd = xc->miscRegs.lo; }}); 84 0x3: mtlo({{ xc->miscRegs.lo = Rs; }}); 85 } 86 } 87 88 0x3: decode FUNCTION_LO { 89 format IntOp { 90 0x0: mult({{ 91 INT64 temp1 = Rs.sw * Rt.sw; 92 xc->miscRegs.hi->temp1<63:32>; 93 xc->miscRegs.lo->temp1<31:0>; 94 }}); 95 96 0x1: multu({{ 97 INT64 temp1 = Rs.uw * Rt.uw; 98 xc->miscRegs.hi->temp1<63:32>; 99 xc->miscRegs.lo->temp1<31:0> 100 Rd.sw = Rs.uw * Rt.uw; 101 }}); 102 103 0x2: div({{ 104 xc->miscRegs.hi = Rs.sw % Rt.sw; 105 xc->miscRegs.lo = Rs.sw / Rt.sw; 106 }}); 107 108 0x3: divu({{ 109 xc->miscRegs.hi = Rs.uw % Rt.uw; 110 xc->miscRegs.lo = Rs.uw / Rt.uw; 111 }}); 112 } 113 } 114 115 0x4: decode FUNCTION_LO { 116 format IntOp { 117 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}}); 118 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}}); 119 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}}); 120 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}}); 121 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}}); 122 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}}); 123 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}}); 124 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}}); 125 } 126 } 127 128 0x5: decode FUNCTION_LO { 129 format IntOp{ 130 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 131 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 132 } 133 } 134 135 0x6: decode FUNCTION_LO { 136 format Trap { 137 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 138 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 139 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 140 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 141 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 142 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 143 } 144 } 145 } 146 147 0x1: decode REGIMM_HI { 148 0x0: decode REGIMM_LO { 149 format Branch { 150 0x0: bltz({{ cond = (Rs.sw < 0); }}); 151 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 152 153 } 154 155 format BranchLikely { 156 //MIPS obsolete instructions 157 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 158 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 159 } 160 } 161 162 0x1: decode REGIMM_LO { 163 format Trap { 164 0x0: tgei({{ cond = (Rs.sw >= INTIMM; }}); 165 0x1: tgeiu({{ cond = (Rs.uw < INTIMM); }}); 166 0x2: tlti({{ cond = (Rs.sw < INTIMM); }}); 167 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 168 0x4: teqi({{ cond = (Rs.sw == INTIMM); }}); 169 0x6: tnei({{ cond = (Rs.sw != INTIMM); }}); 170 } 171 } 172 173 0x2: decode REGIMM_LO { 174 format Branch { 175 0x0: bltzal({{ cond = (Rs.sw < 0); }}); 176 0x1: bgezal({{ cond = (Rs.sw >= 0); }}); 177 } 178 179 format BranchLikely { 180 //MIPS obsolete instructions 181 0x2: bltzall({{ cond = (Rs.sw < 0); }}); 182 0x3: bgezall({{ cond = (Rs.sw >= 0); }}); 183 } 184 } 185 186 0x3: decode REGIMM_LO { 187 format WarnUnimpl { 188 0x7: synci(); 189 } 190 } 191 } 192 193 format Jump { 194 0x2: j(); 195 0x3: jal(IsCall); 196 } 197 198 format Branch { 199 0x4: beq({{ cond = (Rs.sw == 0); }}); 200 0x5: bne({{ cond = (Rs.sw != 0); }}); 201 0x6: blez({{ cond = (Rs.sw <= 0); }}); 202 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 203 } 204 } 205 206 0x1: decode OPCODE_LO default FailUnimpl::reserved(){ 207 format IntOp { 208 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }}); 209 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}}); 210 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }}); 211 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }}); 212 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); 213 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); 214 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); 215 0x7: lui({{ Rt = INTIMM << 16}}); 216 } 217 } 218 219 0x2: decode OPCODE_LO default FailUnimpl::reserved(){ 220 221 //Table A-11 MIPS32 COP0 Encoding of rs Field 222 0x0: decode RS_MSB { 223 0x0: decode RS { 224 225 format BasicOp { 226 0x0: mfc0({{ 227 //The contents of the coprocessor 0 register specified by the 228 //combination of rd and sel are loaded into general register 229 //rt. Note that not all coprocessor 0 registers support the 230 //sel field. In those instances, the sel field must be zero. 231 232 if (SEL > 0) 233 panic("Can't Handle Cop0 with register select yet\n"); 234 235 uint64_t reg_num = Rd.uw; 236 237 Rt = xc->miscRegs.cop0[reg_num]; 238 }}); 239 240 0x4: mtc0({{ 241 //The contents of the coprocessor 0 register specified by the 242 //combination of rd and sel are loaded into general register 243 //rt. Note that not all coprocessor 0 registers support the 244 //sel field. In those instances, the sel field must be zero. 245 246 if (SEL > 0) 247 panic("Can't Handle Cop0 with register select yet\n"); 248 249 uint64_t reg_num = Rd.uw; 250 251 xc->miscRegs.cop0[reg_num] = Rt; 252 }}); 253 254 0x8: mftr({{ 255 //The contents of the coprocessor 0 register specified by the 256 //combination of rd and sel are loaded into general register 257 //rt. Note that not all coprocessor 0 registers support the 258 //sel field. In those instances, the sel field must be zero. 259 260 //MT Code Needed Here 261 }}); 262 263 0xC: mttr({{ 264 //The contents of the coprocessor 0 register specified by the 265 //combination of rd and sel are loaded into general register 266 //rt. Note that not all coprocessor 0 registers support the 267 //sel field. In those instances, the sel field must be zero. 268 269 //MT Code Needed Here 270 }}); 271 272 273 0xA: rdpgpr({{ 274 //Accessing Previous Shadow Set Register Number 275 uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 276 uint64_t reg_num = Rt.uw; 277 278 Rd = xc->shadowIntRegFile[prev][reg_num]; 279 }}); 280 } 281 282 0xB: decode RD { 283 284 0x0: decode SC { 285 format BasicOp { 286 0x0: dvpe({{ 287 Rt.sw = xc->miscRegs.cop0.MVPControl; 288 xc->miscRegs.cop0.MVPControl[EVP] = 0; 289 }}); 290 291 0x1: evpe({{ 292 Rt.sw = xc->miscRegs.cop0.MVPControl; 293 xc->miscRegs.cop0.MVPControl[EVP] = 1; 294 }}); 295 } 296 } 297 298 0x1: decode SC { 299 format BasicOp { 300 0x0: dmt({{ 301 Rt.sw = xc->miscRegs.cop0.VPEControl; 302 xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0; 303 }}); 304 305 0x1: emt({{ 306 Rt.sw = xc->miscRegs.cop0.VPEControl; 307 xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1; 308 }}); 309 } 310 } 311 312 0xC: decode SC { 313 format BasicOp { 314 0x0: di({{ 315 Rt.sw = xc->miscRegs.cop0.Status; 316 xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0; 317 }}); 318 319 0x1: ei({{ 320 Rt.sw = xc->miscRegs.cop0.Status; 321 xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1; 322 }}); 323 } 324 } 325 } 326 327 0xE: BasicOp::wrpgpr({{ 328 //Accessing Previous Shadow Set Register Number 329 uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 330 uint64_t reg_num = Rd.uw; 331 332 xc->shadowIntRegFile[prev][reg_num] = Rt; 333 }}); 334 } 335 336 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 337 0x1: decode FUNCTION { 338 format Trap { 339 0x01: tlbr({{ }}); 340 0x02: tlbwi({{ }}); 341 0x06: tlbwr({{ }}); 342 0x08: tlbp({{ }}); 343 } 344 345 format WarnUnimpl { 346 0x18: eret(); 347 0x1F: deret(); 348 0x20: wait(); 349 } 350 } 351 } 352 353 //Table A-13 MIPS32 COP1 Encoding of rs Field 354 0x1: decode RS_MSB { 355 356 0x0: decode RS_HI { 357 0x0: decode RS_LO { 358 format FloatOp { 359 0x0: mfc1({{ Rt = Fs<31:0>; }}); 360 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}}); 361 0x3: mfhc1({{ Rt = Fs<63:32>;}}); 362 0x4: mtc1({{ Fs<31:0> = Rt}}); 363 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}}); 364 0x7: mftc1({{ Fs<63:32> = Rt}}); 365 } 366 } 367 368 0x1: decode ND { 369 0x0: decode TF { 370 format Branch { 371 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }}); 372 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }}); 373 } 374 } 375 376 0x1: decode TF { 377 format BranchLikely { 378 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }}); 379 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }}); 380 } 381 } 382 } 383 } 384 385 0x1: decode RS_HI { 386 0x2: decode RS_LO { 387 388 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 389 //(( single-word )) 390 0x0: decode RS_HI { 391 0x0: decode RS_LO { 392 format FloatOp { 393 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); 394 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); 395 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); 396 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); 397 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); 398 0x5: abss({{ Fd.sf = abs(Fs.sf);}}); 399 0x6: movs({{ Fd.sf = Fs.sf;}}); 400 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); 401 } 402 } 403 404 0x1: decode RS_LO { 405 //only legal for 64 bit-FP 406 format Float64Op { 407 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}}); 408 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}}); 409 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}}); 410 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}}); 411 } 412 413 format FloatOp { 414 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}}); 415 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}}); 416 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}}); 417 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}}); 418 } 419 } 420 421 0x2: decode RS_LO { 422 0x1: decode MOVCF { 423 format FloatOp { 424 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }}); 425 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}}); 426 } 427 } 428 429 format BasicOp { 430 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 431 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); 432 } 433 434 format Float64Op { 435 0x2: recips({{ Fd = 1 / Fs; }}); 436 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}}); 437 } 438 } 439 440 0x4: decode RS_LO { 441 442 format FloatOp { 443 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr; 444 Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE); 445 }}); 446 447 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr; 448 Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE); 449 }}); 450 } 451 452 //only legal for 64 bit 453 format Float64Op { 454 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr; 455 Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE); 456 }}); 457 458 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }}); 459 } 460 } 461 } 462 463 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 464 0x1: decode RS_HI { 465 0x0: decode RS_LO { 466 format FloatOp { 467 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 468 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 469 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 470 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 471 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 472 0x5: absd({{ Fd.df = abs(Fs.df);}}); 473 0x6: movd({{ Fd.df = Fs.df;}}); 474 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 475 } 476 } 477 478 0x1: decode RS_LO { 479 //only legal for 64 bit 480 format Float64Op { 481 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 482 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}}); 483 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}}); 484 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}}); 485 } 486 487 format FloatOp { 488 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 489 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }}); 490 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }}); 491 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }}); 492 } 493 } 494 495 0x2: decode RS_LO { 496 0x1: decode MOVCF { 497 format FloatOp { 498 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }}); 499 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }}); 500 } 501 } 502 503 format BasicOp { 504 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }}); 505 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }}); 506 } 507 508 format Float64Op { 509 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 510 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 511 } 512 } 513 514 0x4: decode RS_LO { 515 format FloatOp { 516 0x0: cvt_s_d({{ 517 int rnd_mode = xc->miscRegs.fcsr; 518 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE); 519 }}); 520 521 0x4: cvt_w_d({{ 522 int rnd_mode = xc->miscRegs.fcsr; 523 Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE); 524 }}); 525 } 526 527 //only legal for 64 bit 528 format Float64Op { 529 0x5: cvt_l_d({{ 530 int rnd_mode = xc->miscRegs.fcsr; 531 Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE); 532 }}); 533 } 534 } 535 } 536 537 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 538 0x4: decode FUNCTION { 539 format FloatOp { 540 0x10: cvt_s({{ 541 int rnd_mode = xc->miscRegs.fcsr; 542 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); 543 }}); 544 545 0x10: cvt_d({{ 546 int rnd_mode = xc->miscRegs.fcsr; 547 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); 548 }}); 549 } 550 } 551 552 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 553 //Note: "1. Format type L is legal only if 64-bit floating point operations 554 //are enabled." 555 0x5: decode FUNCTION_HI { 556 format FloatOp { 557 0x10: cvt_s_l({{ 558 int rnd_mode = xc->miscRegs.fcsr; 559 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG); 560 }}); 561 562 0x11: cvt_d_l({{ 563 int rnd_mode = xc->miscRegs.fcsr; 564 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG); 565 }}); 566 } 567 } 568 569 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 570 //Note: "1. Format type PS is legal only if 64-bit floating point operations 571 //are enabled. " 572 0x6: decode RS_HI { 573 0x0: decode RS_LO { 574 format Float64Op { 575 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 576 //Lower Halves Independently but we take simulator shortcut 577 Fd.df = Fs.df + Ft.df; 578 }}); 579 580 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 581 //Lower Halves Independently but we take simulator shortcut 582 Fd.df = Fs.df - Ft.df; 583 }}); 584 585 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 586 //Lower Halves Independently but we take simulator shortcut 587 Fd.df = Fs.df * Ft.df; 588 }}); 589 590 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 591 //Lower Halves Independently but we take simulator shortcut 592 Fd.df = abs(Fs.df); 593 }}); 594 595 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 596 //Lower Halves Independently but we take simulator shortcut 597 Fd.df = Fs<31:0> | Ft<31:0>; 598 }}); 599 600 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 601 //Lower Halves Independently but we take simulator shortcut 602 Fd.df = -1 * Fs.df; 603 }}); 604 } 605 } 606 607 0x2: decode RS_LO { 608 0x1: decode MOVCF { 609 format Float64Op { 610 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 611 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 612 } 613 } 614 615 } 616 617 0x4: decode RS_LO { 618 0x0: Float64Op::cvt_s_pu({{ 619 int rnd_mode = xc->miscRegs.fcsr; 620 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI); 621 }}); 622 } 623 624 0x5: decode RS_LO { 625 format Float64Op { 626 0x0: cvt_s_pl({{ 627 int rnd_mode = xc->miscRegs.fcsr; 628 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO); 629 }}); 630 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}}); 631 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}}); 632 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}}); 633 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}}); 634 } 635 } 636 } 637 } 638 639 //Table A-19 MIPS32 COP2 Encoding of rs Field 640 0x2: decode RS_MSB { 641 0x0: decode RS_HI { 642 0x0: decode RS_LO { 643 format WarnUnimpl { 644 0x0: mfc2(); 645 0x2: cfc2(); 646 0x3: mfhc2(); 647 0x4: mtc2(); 648 0x6: ctc2(); 649 0x7: mftc2(); 650 } 651 } 652 653 0x1: decode ND { 654 0x0: decode TF { 655 format WarnUnimpl { 656 0x0: bc2f(); 657 0x1: bc2t(); 658 } 659 } 660 661 0x1: decode TF { 662 format WarnUnimpl { 663 0x0: bc2fl(); 664 0x1: bc2tl(); 665 } 666 } 667 } 668 } 669 } 670 671 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 672 //Note: "COP1X instructions are legal only if 64-bit floating point 673 //operations are enabled." 674 0x3: decode FUNCTION_HI { 675 0x0: decode FUNCTION_LO { 676 format Memory { 677 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.uf; }}); 678 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }}); 679 0x5: luxc1({{ //Need to make EA<2:0> = 0 680 EA = Rs + Rt; 681 }}, 682 {{ Ft<31:0> = Mem.df; }}); 683 } 684 } 685 686 0x1: decode FUNCTION_LO { 687 format Memory { 688 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<31:0>; }}); 689 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<63:0>}}); 690 0x5: suxc1({{ //Need to make EA<2:0> = 0 691 EA = Rs + Rt; 692 }}, 693 {{ Mem.df = Ft<63:0>;}}); 694 } 695 696 0x7: WarnUnimpl::prefx(); 697 } 698 699 format FloatOp { 700 0x3: WarnUnimpl::alnv_ps(); 701 702 format BasicOp { 703 0x4: decode FUNCTION_LO { 704 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 705 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 706 0x6: madd_ps({{ 707 //Must Check for Exception Here... Supposed to Operate on Upper and 708 //Lower Halves Independently but we take simulator shortcut 709 Fd.df = (Fs.df * Fs.df) + Fr.df; 710 }}); 711 } 712 713 0x5: decode FUNCTION_LO { 714 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 715 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 716 0x6: msub_ps({{ 717 //Must Check for Exception Here... Supposed to Operate on Upper and 718 //Lower Halves Independently but we take simulator shortcut 719 Fd.df = (Fs.df * Fs.df) - Fr.df; 720 }}); 721 } 722 723 0x6: decode FUNCTION_LO { 724 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 725 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 726 0x6: nmadd_ps({{ 727 //Must Check for Exception Here... Supposed to Operate on Upper and 728 //Lower Halves Independently but we take simulator shortcut 729 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 730 }}); 731 } 732 733 0x7: decode FUNCTION_LO { 734 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 735 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 736 0x6: nmsub_ps({{ 737 //Must Check for Exception Here... Supposed to Operate on Upper and 738 //Lower Halves Independently but we take simulator shortcut 739 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 740 }}); 741 } 742 } 743 } 744 } 745 746 //MIPS obsolete instructions 747 format BranchLikely { 748 0x4: beql({{ cond = (Rs.sw == 0); }}); 749 0x5: bnel({{ cond = (Rs.sw != 0); }}); 750 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 751 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 752 } 753 } 754 755 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 756 757 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 758 0x4: decode FUNCTION_HI { 759 760 0x0: decode FUNCTION_LO { 761 format IntOp { 762 0x0: madd({{ 763 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 764 temp1 = temp1 + (Rs.sw * Rt.sw); 765 xc->miscRegs.hi->temp1<63:32>; 766 xc->miscRegs.lo->temp1<31:0> 767 }}); 768 769 0x1: maddu({{ 770 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 771 temp1 = temp1 + (Rs.uw * Rt.uw); 772 xc->miscRegs.hi->temp1<63:32>; 773 xc->miscRegs.lo->temp1<31:0> 774 }}); 775 776 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 777 778 0x4: msub({{ 779 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 780 temp1 = temp1 - (Rs.sw * Rt.sw); 781 xc->miscRegs.hi->temp1<63:32>; 782 xc->miscRegs.lo->temp1<31:0> 783 }}); 784 785 0x5: msubu({{ 786 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 787 temp1 = temp1 - (Rs.uw * Rt.uw); 788 xc->miscRegs.hi->temp1<63:32>; 789 xc->miscRegs.lo->temp1<31:0> 790 }}); 791 } 792 } 793 794 0x4: decode FUNCTION_LO { 795 format BasicOp { 796 0x0: clz({{ 797 int cnt = 0; 798 int idx = 0; 799 while ( Rs.uw<idx>!= 1) { 800 cnt++; 801 idx--; 802 } 803 804 Rd.uw = cnt; 805 }}); 806 807 0x1: clo({{ 808 int cnt = 0; 809 int idx = 0; 810 while ( Rs.uw<idx>!= 0) { 811 cnt++; 812 idx--; 813 } 814 815 Rd.uw = cnt; 816 }}); 817 } 818 } 819 820 0x7: decode FUNCTION_LO { 821 0x7: WarnUnimpl::sdbbp(); 822 } 823 } 824 825 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 826 0x7: decode FUNCTION_HI { 827 828 0x0: decode FUNCTION_LO { 829 format WarnUnimpl { 830 0x1: ext(); 831 0x4: ins(); 832 } 833 } 834 835 0x1: decode FUNCTION_LO { 836 format WarnUnimpl { 837 0x0: fork(); 838 0x1: yield(); 839 } 840 } 841 842 843 //Table A-10 MIPS32 BSHFL Encoding of sa Field 844 0x4: decode SA { 845 846 0x02: WarnUnimpl::wsbh(); 847 848 format BasicOp { 849 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}}); 850 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}}); 851 } 852 } 853 854 0x6: decode FUNCTION_LO { 855 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}}); 856 } 857 } 858 } 859 860 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 861 format Memory { 862 0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }}); 863 0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }}); 864 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }});//, WordAlign); 865 0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }}); 866 0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }}); 867 0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }}); 868 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }});//, WordAlign); 869 } 870 871 0x7: FailUnimpl::reserved(); 872 } 873 874 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 875 format Memory { 876 0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }}); 877 0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }}); 878 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign); 879 0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }}); 880 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign); 881 } 882 883 format WarnUnimpl { 884 0x7: cache(); 885 } 886 887 } 888 889 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 890 0x0: WarnUnimpl::ll(); 891 892 format Memory { 893 0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }}); 894 0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }}); 895 } 896 } 897 898 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 899 0x0: WarnUnimpl::sc(); 900 901 format Memory { 902 0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }}); 903 0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }}); 904 } 905 906 } 907} 908 909 910