decoder.isa revision 2046 
1////////////////////////////////////////////////////////////////////
2//
3// The actual MIPS32 ISA decoder
4// -----------------------------
5// The following instructions are specified in the MIPS32 ISA
6// Specification. Decoding closely follows the style specified
7// in the MIPS32 ISAthe specification document starting with Table
8// A-2 (document available @ www.mips.com)
9//
10//@todo: Distinguish "unknown/future" use insts from "reserved"
11// ones
12decode OPCODE_HI default FailUnimpl::unknown() {
13
14    // Derived From ... Table A-2 MIPS32 ISA Manual
15    0x0: decode OPCODE_LO default FailUnimpl::reserved(){
16
17        0x0: decode FUNCTION_HI {
18            0x0: decode FUNCTION_LO {
19              0x1: decode MOVCI {
20                format BasicOp {
21                  0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}});
22                  1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}});
23                }
24              }
25
26              format BasicOp {
27
28                //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
29                //are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
30
31                0x0: sll({{ Rd = Rt.uw << SA; }});
32
33                0x2: decode SRL {
34                   0: srl({{ Rd = Rt.uw >> SA; }});
35
36                   //Hardcoded assuming 32-bit ISA, probably need parameter here
37                   1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
38                 }
39
40                 0x3: sra({{ Rd = Rt.sw >> SA; }});
41
42                 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
43
44                 0x6: decode SRLV {
45                   0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
46
47                   //Hardcoded assuming 32-bit ISA, probably need parameter here
48                   1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
49                 }
50
51                 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }});
52              }
53            }
54
55            0x1: decode FUNCTION_LO {
56
57              //Table A-3 Note: "Specific encodings of the hint field are used
58              //to distinguish JR from JR.HB and JALR from JALR.HB"
59              format Jump {
60                0x0: jr(IsReturn);
61                0x1: jalr(IsCall,IsReturn);
62              }
63
64              format BasicOp {
65                0x2: movz({{ if (Rt == 0) Rd = Rs; }});
66                0x3: movn({{ if (Rt != 0) Rd = Rs; }});
67              }
68
69              format Trap {
70                0x4: syscall({{ xc->syscall()}},IsNonSpeculative);
71                0x5: break({{ }});
72                0x7: sync({{ }});
73              }
74            }
75
76            0x2: decode FUNCTION_LO {
77              format BasicOp {
78                0x0: mfhi({{ Rd = xc->miscRegs.hi; }});
79                0x1: mthi({{ xc->miscRegs.hi = Rs; }});
80                0x2: mflo({{ Rd = xc->miscRegs.lo; }});
81                0x3: mtlo({{ xc->miscRegs.lo = Rs; }});
82              }
83            };
84
85            0x3: decode FUNCTION_LO {
86              format IntOp {
87                0x0: mult({{
88                        INT64 temp1 = Rs.sw * Rt.sw;
89                        xc->miscRegs.hi->temp1<63:32>;
90                        xc->miscRegs.lo->temp1<31:0>
91                }});
92
93                0x1: multu({{
94                        INT64 temp1 = Rs.uw * Rt.uw;
95                        xc->miscRegs.hi->temp1<63:32>;
96                        xc->miscRegs.lo->temp1<31:0>
97                        Rd.sw = Rs.uw * Rt.uw;
98                }});
99
100                0x2: div({{
101                        xc->miscRegs.hi = Rs.sw % Rt.sw;
102                        xc->miscRegs.lo = Rs.sw / Rt.sw;
103                        }});
104
105                0x3: divu({{
106                        xc->miscRegs.hi = Rs.uw % Rt.uw;
107                        xc->miscRegs.lo = Rs.uw / Rt.uw;
108                        }});
109              }
110            };
111
112            0x4: decode FUNCTION_LO {
113              format IntOp {
114                0x0: add({{  Rd.sw = Rs.sw + Rt.sw;}});
115                0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}});
116                0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}});
117                0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}});
118                0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}});
119                0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}});
120                0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}});
121                0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}});
122              }
123            }
124
125            0x5: decode FUNCTION_LO {
126              format IntOp{
127                0x2: slt({{  Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
128                0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
129              }
130            };
131
132            0x6: decode FUNCTION_LO {
133              format Trap {
134                 0x0: tge({{ }});
135                 0x1: tgeu({{ }});
136                 0x2: tlt({{ }});
137                 0x3: tltu({{ }});
138                 0x4: teq({{ }});
139                 0x6: tne({{ }});
140              }
141            }
142        }
143
144        0x1: decode REGIMM_HI {
145            0x0: decode REGIMM_LO {
146              format Branch {
147                0x0: bltz({{ cond = (Rs.sq < 0); }});
148                0x1: bgez({{ cond = (Rs.sq >= 0); }});
149
150                //MIPS obsolete instructions
151                0x2: bltzl({{ cond = (Rs.sq < 0); }});
152                0x3: bgezl({{ cond = (Rs.sq >= 0); }});
153              }
154            }
155
156            0x1: decode REGIMM_LO {
157              format Trap {
158                 0x0: tgei({{ }});
159                 0x1: tgeiu({{ }});
160                 0x2: tlti({{ }});
161                 0x3: tltiu({{ }});
162                 0x4: teqi({{ }});
163                 0x6: tnei({{ }});
164              }
165            }
166
167            0x2: decode REGIMM_LO {
168              format Branch {
169                0x0: bltzal({{ cond = (Rs.sq < 0); }});
170                0x1: bgezal({{ cond = (Rs.sq >= 0); }});
171
172                //MIPS obsolete instructions
173                0x2: bltzall({{ cond = (Rs.sq < 0); }});
174                0x3: bgezall({{ cond = (Rs.sq >= 0); }});
175              }
176            }
177
178            0x3: decode REGIMM_LO {
179              format Trap {
180                0x7: synci({{ }});
181              }
182            }
183        }
184
185        format Jump {
186            0x2: j();
187            0x3: jal(IsCall);
188        }
189
190        format Branch {
191            0x4: beq({{ cond = (Rs.sq == 0); }});
192            0x5: bne({{ cond = (Rs.sq !=  0); }});
193            0x6: blez({{ cond = (Rs.sq <= 0); }});
194            0x7: bgtz({{ cond = (Rs.sq > 0); }});
195        }
196    };
197
198    0x1: decode OPCODE_LO default FailUnimpl::reserved(){
199        format IntOp {
200            0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }});
201            0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}});
202            0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }});
203            0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }});
204            0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
205            0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
206            0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
207            0x7: lui({{ Rt = INTIMM << 16}});
208        };
209    };
210
211    0x2: decode OPCODE_LO default FailUnimpl::reserved(){
212
213      //Table A-11 MIPS32 COP0 Encoding of rs Field
214      0x0: decode RS_MSB {
215        0x0: decode RS {
216
217           format BasicOp {
218                0x0: mfc0({{ }});
219                0xC: mtc0({{ }});
220                0xA: rdpgpr({{ }});
221            }
222
223          0xB: decode SC {
224            format BasicOp {
225                0x0: di({{ }});
226                0x1: ei({{ }});
227            }
228          }
229
230          0xE: BasicOp::wrpgpr({{ }});
231        }
232
233        //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
234        0x1: decode FUNCTION {
235          format Trap {
236                0x01: tlbr({{ }});
237                0x02: tlbwi({{ }});
238                0x06: tlbwr({{ }});
239                0x08: tlbp({{ }});
240          }
241
242          format BasicOp {
243                0x18: eret({{ }});
244                0x1F: deret({{ }});
245                0x20: wait({{ }});
246          }
247        }
248      }
249
250      //Table A-13 MIPS32 COP1 Encoding of rs Field
251      0x1: decode RS_MSB {
252
253        0x0: decode RS_HI {
254          0x0: decode RS_LO {
255            0x0: mfc1({{ }});
256            0x2: cfc1({{ }});
257            0x3: mfhc1({{ }});
258            0x4: mtc1({{ }});
259            0x6: ctc1({{ }});
260            0x7: mftc1({{ }});
261          }
262
263          0x1: decode ND {
264            0x0: decode TF {
265              format Branch {
266                0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
267                0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
268              }
269            }
270
271            0x1: decode TF {
272              format Branch {
273                0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
274                0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
275              }
276            }
277          }
278        }
279
280        0x1: decode RS_HI {
281          0x2: decode RS_LO {
282
283            //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
284            //(( single-word ))
285            0x0: decode RS_HI {
286              0x0: decode RS_LO {
287                format FloatOp {
288                  0x0: add_fmt({{ }});
289                  0x1: sub_fmt({{ }});
290                  0x2: mul_fmt({{ }});
291                  0x3: div_fmt({{ }});
292                  0x4: sqrt_fmt({{ }});
293                  0x5: abs_fmt({{ }});
294                  0x6: mov_fmt({{ }});
295                  0x7: neg_fmt({{ }});
296                }
297              }
298
299              0x1: decode RS_LO {
300                //only legal for 64 bit
301                format Float64Op {
302                  0x0: round_l({{ }});
303                  0x1: trunc_l({{ }});
304                  0x2: ceil_l({{ }});
305                  0x3: floor_l({{ }});
306                }
307
308                format FloatOp {
309                  0x4: round_w({{ }});
310                  0x5: trunc_w({{ }});
311                  0x6: ceil_w({{ }});
312                  0x7: floor_w({{ }});
313                }
314              }
315
316              0x2: decode RS_LO {
317                0x1: decode MOVCF {
318                  format BasicOp {
319                    0x0: movf_fmt({{ }});
320                    0x1: movt_fmt({{ }});
321                  }
322                }
323
324                format BasicOp {
325                  0x2: movz({{ if (Rt == 0) Rd = Rs; }});
326                  0x3: movn({{ if (Rt != 0) Rd = Rs; }});
327                }
328
329                format Float64Op {
330                  0x2: recip({{ }});
331                  0x3: rsqrt{{ }});
332                }
333              }
334
335              0x4: decode RS_LO {
336                0x1: cvt_d({{ }});
337                0x4: cvt_w({{ }});
338
339                //only legal for 64 bit
340                format Float64Op {
341                  0x5: cvt_l({{ }});
342                  0x6: cvt_ps({{ }});
343                }
344              }
345            }
346
347            //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
348            0x1: decode RS_HI {
349              0x0: decode RS_LO {
350                0x0: add_fmt({{ }});
351                0x1: sub_fmt({{ }});
352                0x2: mul_fmt({{ }});
353                0x3: div_fmt({{ }});
354                0x4: sqrt_fmt({{ }});
355                0x5: abs_fmt({{ }});
356                0x6: mov_fmt({{ }});
357                0x7: neg_fmt({{ }});
358              }
359
360              0x1: decode RS_LO {
361                //only legal for 64 bit
362                format mode64 {
363                  0x0: round_l({{ }});
364                  0x1: trunc_l({{ }});
365                  0x2: ceil_l({{ }});
366                  0x3: floor_l({{ }});
367                }
368
369                0x4: round_w({{ }});
370                0x5: trunc_w({{ }});
371                0x6: ceil_w({{ }});
372                0x7: floor_w({{ }});
373              }
374
375              0x2: decode RS_LO {
376                0x1: decode MOVCF {
377                  0x0: movf_fmt({{ }});
378                  0x1: movt_fmt({{ }});
379                }
380
381                format Move {
382                  0x2: movz({{ if (Rt == 0) Rd = Rs; }});
383                  0x3: movn({{ if (Rt != 0) Rd = Rs; }});
384                }
385
386                format mode64 {
387                  0x5: recip({{ }});
388                  0x6: rsqrt{{ }});
389                }
390              }
391
392              0x4: decode RS_LO {
393                0x0: cvt_s({{ }});
394                0x4: cvt_w({{ }});
395
396                //only legal for 64 bit
397                format mode64 {
398                  0x5: cvt_l({{ }});
399                }
400              }
401            }
402
403            //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
404            0x4: decode FUNCTION {
405              0x10: cvt_s({{ }});
406              0x10: cvt_d({{ }});
407            }
408
409            //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
410            //Note: "1. Format type L is legal only if 64-bit floating point operations
411            //are enabled."
412            0x5: decode FUNCTION_HI {
413              0x10: cvt_s({{ }});
414              0x11: cvt_d({{ }});
415            }
416
417            //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
418            //Note: "1. Format type PS is legal only if 64-bit floating point operations
419            //are enabled. "
420            0x6: decode RS_HI {
421              0x0: decode RS_LO {
422                0x0: add_fmt({{ }});
423                0x1: sub_fmt({{ }});
424                0x2: mul_fmt({{ }});
425                0x5: abs_fmt({{ }});
426                0x6: mov_fmt({{ }});
427                0x7: neg_fmt({{ }});
428              }
429
430              0x2: decode RS_LO {
431                0x1: decode MOVCF {
432                  0x0: movf_fmt({{ }});
433                  0x1: movt_fmt({{ }});
434                }
435
436              }
437
438              0x4: decode RS_LO {
439                0x0: cvt_s_pu({{ }});
440              }
441
442              0x5: decode RS_LO {
443                0x0: cvt_s_pl({{ }});
444                0x4: pll_s_pl({{ }});
445                0x5: plu_s_pl({{ }});
446                0x6: pul_s_pl({{ }});
447                0x7: puu_s_pl({{ }});
448              }
449            }
450      }
451
452      //Table A-19 MIPS32 COP2 Encoding of rs Field
453      0x2: decode RS_MSB {
454        0x0: decode RS_HI {
455          0x0: decode RS_LO {
456            format WarnUnimpl {
457                0x0: mfc2({{ }});
458                0x2: cfc2({{ }});
459                0x3: mfhc2({{ }});
460                0x4: mtc2({{ }});
461                0x6: ctc2({{ }});
462                0x7: mftc2({{ }});
463            }
464          }
465
466          0x1: decode ND {
467            0x0: decode TF {
468              format Branch {
469                0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2);
470                0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
471              }
472            }
473
474            0x1: decode TF {
475              format Branch {
476                0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}});
477                0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
478              }
479            }
480          }
481        }
482      }
483
484      //Table A-20 MIPS64 COP1X Encoding of Function Field 1
485      //Note: "COP1X instructions are legal only if 64-bit floating point
486      //operations are enabled."
487      0x3: decode FUNCTION_HI {
488        0x0: decode FUNCTION_LO {
489                format Memory {
490                  0x0: lwxc1({{ }});
491                  0x1: ldxc1({{ }});
492                  0x5: luxc1({{ }});
493                }
494        }
495
496        0x1: decode FUNCTION_LO {
497                format Memory {
498                  0x0: swxc1({{ }});
499                  0x1: sdxc1({{ }});
500                  0x5: suxc1({{ }});
501                  0x7: prefx({{ }});
502                }
503        }
504
505        format FloatOp {
506                0x3: alnv_ps({{ }});
507
508                0x4: decode FUNCTION_LO {
509                  0x0: madd_s({{ }});
510                  0x1: madd_d({{ }});
511                  0x6: madd_ps({{ }});
512                }
513
514                0x5: decode FUNCTION_LO {
515                  0x0: msub_s({{ }});
516                  0x1: msub_d({{ }});
517                  0x6: msub_ps({{ }});
518                }
519
520                0x6: decode FUNCTION_LO {
521                  0x0: nmadd_s({{ }});
522                  0x1: nmadd_d({{ }});
523                  0x6: nmadd_ps({{ }});
524                }
525
526                0x7: decode FUNCTION_LO {
527                  0x0: nmsub_s({{ }});
528                  0x1: nmsub_d({{ }});
529                  0x6: nmsub_ps({{ }});
530                }
531        }
532      }
533
534      //MIPS obsolete instructions
535        format Branch {
536              0x4: beql({{ cond = (Rs.sq == 0); }});
537              0x5: bnel({{ cond = (Rs.sq != 0); }});
538              0x6: blezl({{ cond = (Rs.sq <= 0); }});
539              0x7: bgtzl({{ cond = (Rs.sq > 0); }});
540        }
541    };
542
543    0x3: decode OPCODE_LO default FailUnimpl::reserved() {
544
545        //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
546        0x4: decode FUNCTION_HI {
547
548            0x0: decode FUNCTION_LO {
549                format IntOp {
550                   0x0: madd({{
551                        INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
552                        temp1 = temp1 + (Rs.sw * Rt.sw);
553                        xc->miscRegs.hi->temp1<63:32>;
554                        xc->miscRegs.lo->temp1<31:0>
555                        }});
556
557                   0x1: maddu({{
558                        INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
559                        temp1 = temp1 + (Rs.uw * Rt.uw);
560                        xc->miscRegs.hi->temp1<63:32>;
561                        xc->miscRegs.lo->temp1<31:0>
562                        }});
563
564                   0x2: mul({{ 	Rd.sw = Rs.sw * Rt.sw; 	}});
565
566                   0x4: msub({{
567                        INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
568                        temp1 = temp1 - (Rs.sw * Rt.sw);
569                        xc->miscRegs.hi->temp1<63:32>;
570                        xc->miscRegs.lo->temp1<31:0>
571                        }});
572
573                   0x5: msubu({{
574                        INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
575                        temp1 = temp1 - (Rs.uw * Rt.uw);
576                        xc->miscRegs.hi->temp1<63:32>;
577                        xc->miscRegs.lo->temp1<31:0>
578                        }});
579                }
580            }
581
582            0x4: decode FUNCTION_LO {
583                  format BasicOp {
584                      0x0: clz({{ }});
585                      0x1: clo({{ }});
586                  }
587            }
588
589            0x7: decode FUNCTION_LO {
590              0x7: BasicOp::sdbbp({{ }});
591            }
592        }
593
594        //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture
595        0x7: decode FUNCTION_HI {
596
597          0x0: decode FUNCTION_LO {
598                format Branch {
599                    0x1: ext({{ }});
600                    0x4: ins({{ }});
601                }
602          }
603
604          //Table A-10 MIPS32 BSHFL Encoding of sa Field
605          0x4: decode SA {
606                format BasicOp {
607                    0x02: wsbh({{ }});
608                    0x10: seb({{ }});
609                    0x18: seh({{ }});
610                }
611          }
612
613          0x6: decode FUNCTION_LO {
614            0x7: BasicOp::rdhwr({{ }});
615          }
616        }
617    };
618
619    0x4: decode OPCODE_LO default FailUnimpl::reserved() {
620        format Memory {
621            0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }});
622            0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }});
623            0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign);
624            0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }});
625            0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }});
626            0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }});
627            0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign);
628        };
629
630        0x7: FailUnimpl::reserved({{ }});
631    };
632
633    0x5: decode OPCODE_LO default FailUnimpl::reserved() {
634        format Memory {
635            0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }});
636            0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }});
637            0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
638            0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});
639            0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
640        };
641
642        format WarnUnimpl {
643            0x4: reserved({{ }});
644            0x5: reserved({{ }});
645            0x7: cache({{ }});
646        };
647
648    };
649
650    0x6: decode OPCODE_LO default FailUnimpl::reserved() {
651        format Memory {
652            0x0: ll({{ }});
653            0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
654            0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }});
655        };
656    };
657
658    0x7: decode OPCODE_LO default FailUnimpl::reserved() {
659        format Memory {
660            0x0: sc({{ }});
661            0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }});
662            0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }});
663        };
664
665    }
666}
667
668
669