decoder.isa revision 5250
12686Sksewell@umich.edu// -*- mode:c++ -*- 22100SN/A 35222Sksewell@umich.edu// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved 45222Sksewell@umich.edu 55222Sksewell@umich.edu// This software is part of the M5 simulator. 65222Sksewell@umich.edu 75222Sksewell@umich.edu// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 85222Sksewell@umich.edu// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 95222Sksewell@umich.edu// TO THESE TERMS AND CONDITIONS. 105222Sksewell@umich.edu 115222Sksewell@umich.edu// Permission is granted to use, copy, create derivative works and 125222Sksewell@umich.edu// distribute this software and such derivative works for any purpose, 135222Sksewell@umich.edu// so long as (1) the copyright notice above, this grant of permission, 145222Sksewell@umich.edu// and the disclaimer below appear in all copies and derivative works 155222Sksewell@umich.edu// made, (2) the copyright notice above is augmented as appropriate to 165222Sksewell@umich.edu// reflect the addition of any new copyrightable work in a derivative 175222Sksewell@umich.edu// work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3) 185222Sksewell@umich.edu// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any 195222Sksewell@umich.edu// advertising or publicity pertaining to the use or distribution of 205222Sksewell@umich.edu// this software without specific, written prior authorization. 215222Sksewell@umich.edu 225222Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND 235222Sksewell@umich.edu// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 245222Sksewell@umich.edu// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 255222Sksewell@umich.edu// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 265222Sksewell@umich.edu// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 275222Sksewell@umich.edu// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 285222Sksewell@umich.edu// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 295222Sksewell@umich.edu// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 305222Sksewell@umich.edu// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 315222Sksewell@umich.edu// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 325222Sksewell@umich.edu// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 335222Sksewell@umich.edu// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 345222Sksewell@umich.edu 355222Sksewell@umich.edu//Authors: Korey L. Sewell 365222Sksewell@umich.edu// Brett Miller 375222Sksewell@umich.edu// Jaidev Patwardhan 382706Sksewell@umich.edu 392022SN/A//////////////////////////////////////////////////////////////////// 402022SN/A// 412043SN/A// The actual MIPS32 ISA decoder 422024SN/A// ----------------------------- 432024SN/A// The following instructions are specified in the MIPS32 ISA 442043SN/A// Specification. Decoding closely follows the style specified 452686Sksewell@umich.edu// in the MIPS32 ISA specification document starting with Table 464661Sksewell@umich.edu// A-2 (document available @ http://www.mips.com) 472022SN/A// 482083SN/Adecode OPCODE_HI default Unknown::unknown() { 492686Sksewell@umich.edu //Table A-2 502101SN/A 0x0: decode OPCODE_LO { 512043SN/A 0x0: decode FUNCTION_HI { 522043SN/A 0x0: decode FUNCTION_LO { 532101SN/A 0x1: decode MOVCI { 542101SN/A format BasicOp { 552686Sksewell@umich.edu 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }}); 562686Sksewell@umich.edu 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }}); 572101SN/A } 582101SN/A } 592101SN/A 602046SN/A format BasicOp { 612686Sksewell@umich.edu //Table A-3 Note: "Specific encodings of the rd, rs, and 622686Sksewell@umich.edu //rt fields are used to distinguish SLL, SSNOP, and EHB 632686Sksewell@umich.edu //functions 642470SN/A 0x0: decode RS { 652686Sksewell@umich.edu 0x0: decode RT_RD { 664661Sksewell@umich.edu 0x0: decode SA default Nop::nop() { 675222Sksewell@umich.edu 0x1: ssnop({{;}}); 685222Sksewell@umich.edu 0x3: ehb({{;}}); 692686Sksewell@umich.edu } 702686Sksewell@umich.edu default: sll({{ Rd = Rt.uw << SA; }}); 712470SN/A } 722241SN/A } 732101SN/A 742495SN/A 0x2: decode RS_SRL { 752495SN/A 0x0:decode SRL { 762495SN/A 0: srl({{ Rd = Rt.uw >> SA; }}); 772101SN/A 782495SN/A //Hardcoded assuming 32-bit ISA, probably need parameter here 792495SN/A 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 802495SN/A } 812101SN/A } 822101SN/A 832495SN/A 0x3: decode RS { 842495SN/A 0x0: sra({{ 852495SN/A uint32_t temp = Rt >> SA; 862495SN/A if ( (Rt & 0x80000000) > 0 ) { 872495SN/A uint32_t mask = 0x80000000; 882495SN/A for(int i=0; i < SA; i++) { 892495SN/A temp |= mask; 902495SN/A mask = mask >> 1; 912495SN/A } 922495SN/A } 932495SN/A Rd = temp; 942495SN/A }}); 952495SN/A } 962101SN/A 972101SN/A 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 982101SN/A 992101SN/A 0x6: decode SRLV { 1002101SN/A 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 1012101SN/A 1022101SN/A //Hardcoded assuming 32-bit ISA, probably need parameter here 1032101SN/A 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 1042101SN/A } 1052101SN/A 1062495SN/A 0x7: srav({{ 1072495SN/A int shift_amt = Rs<4:0>; 1082495SN/A 1092495SN/A uint32_t temp = Rt >> shift_amt; 1102495SN/A 1112495SN/A if ( (Rt & 0x80000000) > 0 ) { 1122495SN/A uint32_t mask = 0x80000000; 1132495SN/A for(int i=0; i < shift_amt; i++) { 1142495SN/A temp |= mask; 1152495SN/A mask = mask >> 1; 1162495SN/A } 1172495SN/A } 1182495SN/A 1192495SN/A Rd = temp; 1202495SN/A }}); 1212043SN/A } 1222043SN/A } 1232025SN/A 1242043SN/A 0x1: decode FUNCTION_LO { 1252686Sksewell@umich.edu //Table A-3 Note: "Specific encodings of the hint field are 1262686Sksewell@umich.edu //used to distinguish JR from JR.HB and JALR from JALR.HB" 1272123SN/A format Jump { 1282101SN/A 0x0: decode HINT { 1295222Sksewell@umich.edu 0x1: jr_hb({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");}; }}, IsReturn, ClearHazards); 1305222Sksewell@umich.edu default: jr({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");};}}, IsReturn); 1312101SN/A } 1322042SN/A 1332101SN/A 0x1: decode HINT { 1344661Sksewell@umich.edu 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall 1352686Sksewell@umich.edu , ClearHazards); 1364661Sksewell@umich.edu default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall); 1372101SN/A } 1382101SN/A } 1392042SN/A 1402101SN/A format BasicOp { 1412686Sksewell@umich.edu 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 1422686Sksewell@umich.edu 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 1435222Sksewell@umich.edu#if FULL_SYSTEM 1445222Sksewell@umich.edu 0x4: syscall({{ 1455222Sksewell@umich.edu fault = new SystemCallFault(); 1465222Sksewell@umich.edu }}); 1475222Sksewell@umich.edu#else 1482965Sksewell@umich.edu 0x4: syscall({{ xc->syscall(R2); }}, 1495222Sksewell@umich.edu IsSerializing, IsNonSpeculative); 1505222Sksewell@umich.edu#endif 1512686Sksewell@umich.edu 0x7: sync({{ ; }}, IsMemBarrier); 1525222Sksewell@umich.edu 0x5: break({{fault = new BreakpointFault();}}); 1532101SN/A } 1542083SN/A 1552043SN/A } 1562025SN/A 1572043SN/A 0x2: decode FUNCTION_LO { 1585222Sksewell@umich.edu 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, IntMultOp, IsIprAccess); 1594661Sksewell@umich.edu 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); 1605222Sksewell@umich.edu 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, IntMultOp, IsIprAccess); 1614661Sksewell@umich.edu 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); 1622083SN/A } 1632025SN/A 1642043SN/A 0x3: decode FUNCTION_LO { 1654661Sksewell@umich.edu format HiLoRdSelValOp { 1665222Sksewell@umich.edu 0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp); 1675222Sksewell@umich.edu 0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp); 1684661Sksewell@umich.edu } 1694661Sksewell@umich.edu 1702686Sksewell@umich.edu format HiLoOp { 1714661Sksewell@umich.edu 0x2: div({{ if (Rt.sd != 0) { 1724661Sksewell@umich.edu HI0 = Rs.sd % Rt.sd; 1734661Sksewell@umich.edu LO0 = Rs.sd / Rt.sd; 1744661Sksewell@umich.edu } 1755222Sksewell@umich.edu }}, IntDivOp); 1765222Sksewell@umich.edu 1774661Sksewell@umich.edu 0x3: divu({{ if (Rt.ud != 0) { 1784661Sksewell@umich.edu HI0 = Rs.ud % Rt.ud; 1794661Sksewell@umich.edu LO0 = Rs.ud / Rt.ud; 1804661Sksewell@umich.edu } 1815222Sksewell@umich.edu }}, IntDivOp); 1822101SN/A } 1832084SN/A } 1842025SN/A 1852495SN/A 0x4: decode HINT { 1862495SN/A 0x0: decode FUNCTION_LO { 1872495SN/A format IntOp { 1885222Sksewell@umich.edu 0x0: add({{ /* More complicated since an ADD can cause an arithmetic overflow exception */ 1895222Sksewell@umich.edu int64_t Src1 = Rs.sw; 1905222Sksewell@umich.edu int64_t Src2 = Rt.sw; 1915222Sksewell@umich.edu int64_t temp_result; 1925222Sksewell@umich.edu#if FULL_SYSTEM 1935222Sksewell@umich.edu if(((Src1 >> 31) & 1) == 1) 1945222Sksewell@umich.edu Src1 |= 0x100000000LL; 1955222Sksewell@umich.edu#endif 1965222Sksewell@umich.edu temp_result = Src1 + Src2; 1975222Sksewell@umich.edu#if FULL_SYSTEM 1985222Sksewell@umich.edu if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){ 1995222Sksewell@umich.edu#endif 2005222Sksewell@umich.edu Rd.sw = temp_result; 2015222Sksewell@umich.edu#if FULL_SYSTEM 2025222Sksewell@umich.edu } else{ 2035222Sksewell@umich.edu fault = new ArithmeticFault(); 2045222Sksewell@umich.edu } 2055222Sksewell@umich.edu#endif 2065222Sksewell@umich.edu 2075222Sksewell@umich.edu }}); 2082495SN/A 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 2095222Sksewell@umich.edu 0x2: sub({{ 2105222Sksewell@umich.edu /* More complicated since an SUB can cause an arithmetic overflow exception */ 2115222Sksewell@umich.edu int64_t Src1 = Rs.sw; 2125222Sksewell@umich.edu int64_t Src2 = Rt.sw; 2135222Sksewell@umich.edu int64_t temp_result = Src1 - Src2; 2145222Sksewell@umich.edu#if FULL_SYSTEM 2155222Sksewell@umich.edu if(((temp_result >> 31) & 1) == ((temp_result>>32) & 1)){ 2165222Sksewell@umich.edu#endif 2175222Sksewell@umich.edu Rd.sw = temp_result; 2185222Sksewell@umich.edu#if FULL_SYSTEM 2195222Sksewell@umich.edu } else{ 2205222Sksewell@umich.edu fault = new ArithmeticFault(); 2215222Sksewell@umich.edu } 2225222Sksewell@umich.edu#endif 2235222Sksewell@umich.edu }}); 2242495SN/A 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 2252495SN/A 0x4: and({{ Rd = Rs & Rt;}}); 2262495SN/A 0x5: or({{ Rd = Rs | Rt;}}); 2272495SN/A 0x6: xor({{ Rd = Rs ^ Rt;}}); 2282495SN/A 0x7: nor({{ Rd = ~(Rs | Rt);}}); 2292495SN/A } 2302101SN/A } 2312043SN/A } 2322025SN/A 2332495SN/A 0x5: decode HINT { 2342495SN/A 0x0: decode FUNCTION_LO { 2352495SN/A format IntOp{ 2362495SN/A 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 2372495SN/A 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 2382495SN/A } 2392101SN/A } 2402084SN/A } 2412024SN/A 2422043SN/A 0x6: decode FUNCTION_LO { 2432239SN/A format Trap { 2442239SN/A 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 2452101SN/A 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 2462101SN/A 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 2475222Sksewell@umich.edu 0x3: tltu({{ cond = (Rs.uw < Rt.uw); }}); 2482101SN/A 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 2492101SN/A 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 2502101SN/A } 2512043SN/A } 2522043SN/A } 2532025SN/A 2542043SN/A 0x1: decode REGIMM_HI { 2552043SN/A 0x0: decode REGIMM_LO { 2562101SN/A format Branch { 2572101SN/A 0x0: bltz({{ cond = (Rs.sw < 0); }}); 2582101SN/A 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 2592686Sksewell@umich.edu 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely); 2602686Sksewell@umich.edu 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely); 2612101SN/A } 2622043SN/A } 2632025SN/A 2642043SN/A 0x1: decode REGIMM_LO { 2655222Sksewell@umich.edu format TrapImm { 2665222Sksewell@umich.edu 0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }}); 2675222Sksewell@umich.edu 0x1: tgeiu({{ cond = (Rs.uw >= (uint32_t)((int32_t)((int16_t)INTIMM))); }}); 2685222Sksewell@umich.edu 0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }}); 2695222Sksewell@umich.edu 0x3: tltiu({{ cond = (Rs.uw < (uint32_t)((int32_t)((int16_t)INTIMM))); }}); 2705222Sksewell@umich.edu 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM);}}); 2715222Sksewell@umich.edu 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM);}}); 2722101SN/A } 2732043SN/A } 2742043SN/A 2752043SN/A 0x2: decode REGIMM_LO { 2762101SN/A format Branch { 2772686Sksewell@umich.edu 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link); 2782686Sksewell@umich.edu 0x1: decode RS { 2792686Sksewell@umich.edu 0x0: bal ({{ cond = 1; }}, IsCall, Link); 2802686Sksewell@umich.edu default: bgezal({{ cond = (Rs.sw >= 0); }}, Link); 2812686Sksewell@umich.edu } 2822686Sksewell@umich.edu 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely); 2832686Sksewell@umich.edu 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely); 2842101SN/A } 2852043SN/A } 2862043SN/A 2872043SN/A 0x3: decode REGIMM_LO { 2884661Sksewell@umich.edu // from Table 5-4 MIPS32 REGIMM Encoding of rt Field (DSP ASE MANUAL) 2894661Sksewell@umich.edu 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 2902101SN/A format WarnUnimpl { 2912101SN/A 0x7: synci(); 2922101SN/A } 2932043SN/A } 2942043SN/A } 2952043SN/A 2962123SN/A format Jump { 2972239SN/A 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 2982686Sksewell@umich.edu 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall, 2992686Sksewell@umich.edu Link); 3002043SN/A } 3012043SN/A 3022100SN/A format Branch { 3032686Sksewell@umich.edu 0x4: decode RS_RT { 3042686Sksewell@umich.edu 0x0: b({{ cond = 1; }}); 3052686Sksewell@umich.edu default: beq({{ cond = (Rs.sw == Rt.sw); }}); 3062686Sksewell@umich.edu } 3072239SN/A 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 3082686Sksewell@umich.edu 0x6: blez({{ cond = (Rs.sw <= 0); }}); 3092686Sksewell@umich.edu 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 3102043SN/A } 3112084SN/A } 3122024SN/A 3132101SN/A 0x1: decode OPCODE_LO { 3142686Sksewell@umich.edu format IntImmOp { 3155222Sksewell@umich.edu 0x0: addi({{ 3165222Sksewell@umich.edu int64_t Src1 = Rs.sw; 3175222Sksewell@umich.edu int64_t Src2 = imm; 3185222Sksewell@umich.edu int64_t temp_result; 3195222Sksewell@umich.edu#if FULL_SYSTEM 3205222Sksewell@umich.edu if(((Src1 >> 31) & 1) == 1) 3215222Sksewell@umich.edu Src1 |= 0x100000000LL; 3225222Sksewell@umich.edu#endif 3235222Sksewell@umich.edu temp_result = Src1 + Src2; 3245222Sksewell@umich.edu#if FULL_SYSTEM 3255222Sksewell@umich.edu if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){ 3265222Sksewell@umich.edu#endif 3275222Sksewell@umich.edu Rt.sw = temp_result; 3285222Sksewell@umich.edu#if FULL_SYSTEM 3295222Sksewell@umich.edu } else{ 3305222Sksewell@umich.edu fault = new ArithmeticFault(); 3315222Sksewell@umich.edu } 3325222Sksewell@umich.edu#endif 3335222Sksewell@umich.edu }}); 3342239SN/A 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 3352239SN/A 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 3364661Sksewell@umich.edu 3374661Sksewell@umich.edu //Edited to include MIPS AVP Pass/Fail instructions and 3384661Sksewell@umich.edu //default to the sltiu instruction 3394661Sksewell@umich.edu 0x3: decode RS_RT_INTIMM { 3404661Sksewell@umich.edu 0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }}); 3414661Sksewell@umich.edu 0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }}); 3424661Sksewell@umich.edu default: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); 3434661Sksewell@umich.edu } 3444661Sksewell@umich.edu 3452495SN/A 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 3462495SN/A 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 3472495SN/A 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); 3482495SN/A 3492495SN/A 0x7: decode RS { 3502495SN/A 0x0: lui({{ Rt = imm << 16}}); 3512495SN/A } 3522084SN/A } 3532084SN/A } 3542024SN/A 3552101SN/A 0x2: decode OPCODE_LO { 3562101SN/A //Table A-11 MIPS32 COP0 Encoding of rs Field 3572101SN/A 0x0: decode RS_MSB { 3582101SN/A 0x0: decode RS { 3595222Sksewell@umich.edu format CP0Control { 3605222Sksewell@umich.edu 0x0: mfc0({{ Rt = CP0_RD_SEL; 3615222Sksewell@umich.edu /* Hack for PageMask */ 3625222Sksewell@umich.edu if(RD == 5) // PageMask 3635222Sksewell@umich.edu if(Config3_SP == 0 || PageGrain_ESP == 0) 3645222Sksewell@umich.edu Rt &= 0xFFFFE7FF; 3655222Sksewell@umich.edu }}); 3665222Sksewell@umich.edu 0x4: mtc0({{ CP0_RD_SEL = Rt; 3672052SN/A 3685222Sksewell@umich.edu if(RD == 11) // Compare{ 3695222Sksewell@umich.edu if(Cause_TI == 1){ 3705222Sksewell@umich.edu Cause_TI = 0; 3715222Sksewell@umich.edu MiscReg cause = xc->readMiscRegNoEffect(MipsISA::Cause); 3725222Sksewell@umich.edu int Offset = 10; // corresponding to Cause_IP0 3735222Sksewell@umich.edu Offset += ((IntCtl_IPTI) - 2); 3745222Sksewell@umich.edu replaceBits(cause,Offset,Offset,0); 3755222Sksewell@umich.edu xc->setMiscRegNoEffect(MipsISA::Cause,cause); 3765222Sksewell@umich.edu } 3774661Sksewell@umich.edu 3785222Sksewell@umich.edu }}); 3795222Sksewell@umich.edu } 3805222Sksewell@umich.edu format CP0Unimpl { 3815222Sksewell@umich.edu 0x1: dmfc0(); 3825222Sksewell@umich.edu 0x5: dmtc0(); 3835222Sksewell@umich.edu default: unknown(); 3845222Sksewell@umich.edu } 3854661Sksewell@umich.edu format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions 3864661Sksewell@umich.edu 0x8: decode MT_U { 3874661Sksewell@umich.edu 0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) + 3884661Sksewell@umich.edu Ctrl_Base_DepTag); 3894661Sksewell@umich.edu }}); 3904661Sksewell@umich.edu 0x1: decode SEL { 3914661Sksewell@umich.edu 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }}); 3924661Sksewell@umich.edu 0x1: decode RT { 3934661Sksewell@umich.edu 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }}); 3944661Sksewell@umich.edu 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }}); 3954661Sksewell@umich.edu 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }}); 3964661Sksewell@umich.edu 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }}); 3974661Sksewell@umich.edu 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }}); 3984661Sksewell@umich.edu 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }}); 3994661Sksewell@umich.edu 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }}); 4004661Sksewell@umich.edu 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }}); 4014661Sksewell@umich.edu 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }}); 4024661Sksewell@umich.edu 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }}); 4034661Sksewell@umich.edu 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }}); 4044661Sksewell@umich.edu 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }}); 4054661Sksewell@umich.edu 0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }}); 4065222Sksewell@umich.edu default: CP0Unimpl::unknown(); 4072686Sksewell@umich.edu } 4084661Sksewell@umich.edu 0x2: decode MT_H { 4094661Sksewell@umich.edu 0x0: mftc1({{ data = xc->readRegOtherThread(RT + 4104661Sksewell@umich.edu FP_Base_DepTag); 4114661Sksewell@umich.edu }}); 4124661Sksewell@umich.edu 0x1: mfthc1({{ data = xc->readRegOtherThread(RT + 4134661Sksewell@umich.edu FP_Base_DepTag); 4144661Sksewell@umich.edu }}); 4155222Sksewell@umich.edu } 4164661Sksewell@umich.edu 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR + 4174661Sksewell@umich.edu FP_Base_DepTag); 4184661Sksewell@umich.edu switch (RT) 4194661Sksewell@umich.edu { 4204661Sksewell@umich.edu case 0: 4214661Sksewell@umich.edu data = xc->readRegOtherThread(MipsISA::FIR + 4224661Sksewell@umich.edu Ctrl_Base_DepTag); 4234661Sksewell@umich.edu break; 4244661Sksewell@umich.edu case 25: 4254661Sksewell@umich.edu data = 0 | fcsr_val & 0xFE000000 >> 24 4264661Sksewell@umich.edu | fcsr_val & 0x00800000 >> 23; 4274661Sksewell@umich.edu break; 4284661Sksewell@umich.edu case 26: 4294661Sksewell@umich.edu data = 0 | fcsr_val & 0x0003F07C; 4304661Sksewell@umich.edu break; 4314661Sksewell@umich.edu case 28: 4324661Sksewell@umich.edu data = 0 | fcsr_val & 0x00000F80 4334661Sksewell@umich.edu | fcsr_val & 0x01000000 >> 21 4344661Sksewell@umich.edu | fcsr_val & 0x00000003; 4354661Sksewell@umich.edu break; 4364661Sksewell@umich.edu case 31: 4374661Sksewell@umich.edu data = fcsr_val; 4384661Sksewell@umich.edu break; 4394661Sksewell@umich.edu default: 4404661Sksewell@umich.edu fatal("FP Control Value (%d) Not Valid"); 4414661Sksewell@umich.edu } 4424661Sksewell@umich.edu }}); 4435222Sksewell@umich.edu default: CP0Unimpl::unknown(); 4442101SN/A } 4455222Sksewell@umich.edu } 4462686Sksewell@umich.edu } 4472027SN/A 4484661Sksewell@umich.edu format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions 4494661Sksewell@umich.edu 0xC: decode MT_U { 4504661Sksewell@umich.edu 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag, 4514661Sksewell@umich.edu Rt); 4524661Sksewell@umich.edu }}); 4534661Sksewell@umich.edu 0x1: decode SEL { 4544661Sksewell@umich.edu 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }}); 4554661Sksewell@umich.edu 0x1: decode RT { 4564661Sksewell@umich.edu 0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt); 4574661Sksewell@umich.edu }}); 4584661Sksewell@umich.edu 0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0, 4594661Sksewell@umich.edu Rt); 4604661Sksewell@umich.edu }}); 4614661Sksewell@umich.edu 0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0, 4624661Sksewell@umich.edu Rt); 4634661Sksewell@umich.edu }}); 4644661Sksewell@umich.edu 0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1, 4654661Sksewell@umich.edu Rt); 4664661Sksewell@umich.edu }}); 4674661Sksewell@umich.edu 0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1, 4684661Sksewell@umich.edu Rt); 4694661Sksewell@umich.edu }}); 4704661Sksewell@umich.edu 0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1, 4714661Sksewell@umich.edu Rt); 4724661Sksewell@umich.edu }}); 4734661Sksewell@umich.edu 0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2, 4744661Sksewell@umich.edu Rt); 4754661Sksewell@umich.edu }}); 4764661Sksewell@umich.edu 0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2, 4774661Sksewell@umich.edu Rt); 4784661Sksewell@umich.edu }}); 4794661Sksewell@umich.edu 0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2, 4804661Sksewell@umich.edu Rt); 4814661Sksewell@umich.edu }}); 4824661Sksewell@umich.edu 0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3, 4834661Sksewell@umich.edu Rt); 4844661Sksewell@umich.edu }}); 4854661Sksewell@umich.edu 0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3, 4864661Sksewell@umich.edu Rt); 4874661Sksewell@umich.edu }}); 4884661Sksewell@umich.edu 0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt); 4894661Sksewell@umich.edu }}); 4904661Sksewell@umich.edu 0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }}); 4915222Sksewell@umich.edu default: CP0Unimpl::unknown(); 4925222Sksewell@umich.edu 4934661Sksewell@umich.edu } 4944661Sksewell@umich.edu 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD + 4954661Sksewell@umich.edu FP_Base_DepTag); 4964661Sksewell@umich.edu data = insertBits(data, top_bit, bottom_bit, Rt); 4974661Sksewell@umich.edu xc->setRegOtherThread(RD + FP_Base_DepTag, data); 4984661Sksewell@umich.edu }}); 4994661Sksewell@umich.edu 0x3: cttc1({{ uint32_t data; 5004661Sksewell@umich.edu switch (RD) 5014661Sksewell@umich.edu { 5024661Sksewell@umich.edu case 25: 5034661Sksewell@umich.edu data = 0 | (Rt.uw<7:1> << 25) // move 31...25 5044661Sksewell@umich.edu | (FCSR & 0x01000000) // bit 24 5054661Sksewell@umich.edu | (FCSR & 0x004FFFFF);// bit 22...0 5064661Sksewell@umich.edu break; 5074661Sksewell@umich.edu 5084661Sksewell@umich.edu case 26: 5094661Sksewell@umich.edu data = 0 | (FCSR & 0xFFFC0000) // move 31...18 5104661Sksewell@umich.edu | Rt.uw<17:12> << 12 // bit 17...12 5114661Sksewell@umich.edu | (FCSR & 0x00000F80) << 7// bit 11...7 5124661Sksewell@umich.edu | Rt.uw<6:2> << 2 // bit 6...2 5134661Sksewell@umich.edu | (FCSR & 0x00000002); // bit 1...0 5144661Sksewell@umich.edu break; 5154661Sksewell@umich.edu 5164661Sksewell@umich.edu case 28: 5174661Sksewell@umich.edu data = 0 | (FCSR & 0xFE000000) // move 31...25 5184661Sksewell@umich.edu | Rt.uw<2:2> << 24 // bit 24 5194661Sksewell@umich.edu | (FCSR & 0x00FFF000) << 23// bit 23...12 5204661Sksewell@umich.edu | Rt.uw<11:7> << 7 // bit 24 5214661Sksewell@umich.edu | (FCSR & 0x000007E) 5224661Sksewell@umich.edu | Rt.uw<1:0>;// bit 22...0 5234661Sksewell@umich.edu break; 5244661Sksewell@umich.edu 5254661Sksewell@umich.edu case 31: 5264661Sksewell@umich.edu data = Rt.uw; 5274661Sksewell@umich.edu break; 5284661Sksewell@umich.edu 5294661Sksewell@umich.edu default: 5304661Sksewell@umich.edu panic("FP Control Value (%d) Not Available. Ignoring Access to" 5314661Sksewell@umich.edu "Floating Control Status Register", FS); 5324661Sksewell@umich.edu } 5334661Sksewell@umich.edu xc->setRegOtherThread(FCSR, data); 5344661Sksewell@umich.edu }}); 5355222Sksewell@umich.edu default: CP0Unimpl::unknown(); 5364661Sksewell@umich.edu } 5374661Sksewell@umich.edu } 5382101SN/A } 5394661Sksewell@umich.edu 5404661Sksewell@umich.edu 5414661Sksewell@umich.edu 0xB: decode RD { 5424661Sksewell@umich.edu format MT_Control { 5434661Sksewell@umich.edu 0x0: decode POS { 5444661Sksewell@umich.edu 0x0: decode SEL { 5454661Sksewell@umich.edu 0x1: decode SC { 5464661Sksewell@umich.edu 0x0: dvpe({{ Rt = MVPControl; 5474661Sksewell@umich.edu if (VPEConf0<VPEC0_MVP:> == 1) { 5484661Sksewell@umich.edu MVPControl = insertBits(MVPControl, MVPC_EVP, 0); 5494661Sksewell@umich.edu } 5504661Sksewell@umich.edu }}); 5514661Sksewell@umich.edu 0x1: evpe({{ Rt = MVPControl; 5524661Sksewell@umich.edu if (VPEConf0<VPEC0_MVP:> == 1) { 5534661Sksewell@umich.edu MVPControl = insertBits(MVPControl, MVPC_EVP, 1); 5544661Sksewell@umich.edu } 5554661Sksewell@umich.edu }}); 5565222Sksewell@umich.edu default:CP0Unimpl::unknown(); 5574661Sksewell@umich.edu } 5585222Sksewell@umich.edu default:CP0Unimpl::unknown(); 5594661Sksewell@umich.edu } 5605222Sksewell@umich.edu default:CP0Unimpl::unknown(); 5615222Sksewell@umich.edu } 5624661Sksewell@umich.edu 5634661Sksewell@umich.edu 0x1: decode POS { 5644661Sksewell@umich.edu 0xF: decode SEL { 5654661Sksewell@umich.edu 0x1: decode SC { 5664661Sksewell@umich.edu 0x0: dmt({{ Rt = VPEControl; 5674661Sksewell@umich.edu VPEControl = insertBits(VPEControl, VPEC_TE, 0); 5684661Sksewell@umich.edu }}); 5694661Sksewell@umich.edu 0x1: emt({{ Rt = VPEControl; 5704661Sksewell@umich.edu VPEControl = insertBits(VPEControl, VPEC_TE, 1); 5714661Sksewell@umich.edu }}); 5725222Sksewell@umich.edu default:CP0Unimpl::unknown(); 5734661Sksewell@umich.edu } 5745222Sksewell@umich.edu default:CP0Unimpl::unknown(); 5754661Sksewell@umich.edu } 5765222Sksewell@umich.edu default:CP0Unimpl::unknown(); 5774661Sksewell@umich.edu } 5784661Sksewell@umich.edu } 5794661Sksewell@umich.edu 0xC: decode POS { 5804661Sksewell@umich.edu 0x0: decode SC { 5814661Sksewell@umich.edu 0x0: CP0Control::di({{ 5824661Sksewell@umich.edu if(Config_AR >= 1) // Rev 2.0 or beyond? 5834661Sksewell@umich.edu { 5844661Sksewell@umich.edu Rt = Status; 5854661Sksewell@umich.edu Status_IE = 0; 5864661Sksewell@umich.edu } 5874661Sksewell@umich.edu else // Enable this else branch once we actually set values for Config on init 5884661Sksewell@umich.edu { 5894661Sksewell@umich.edu fault = new ReservedInstructionFault(); 5904661Sksewell@umich.edu } 5914661Sksewell@umich.edu }}); 5924661Sksewell@umich.edu 0x1: CP0Control::ei({{ 5934661Sksewell@umich.edu if(Config_AR >= 1) 5944661Sksewell@umich.edu { 5954661Sksewell@umich.edu Rt = Status; 5964661Sksewell@umich.edu Status_IE = 1; 5974661Sksewell@umich.edu } 5984661Sksewell@umich.edu else 5994661Sksewell@umich.edu { 6004661Sksewell@umich.edu fault = new ReservedInstructionFault(); 6014661Sksewell@umich.edu } 6024661Sksewell@umich.edu }}); 6035222Sksewell@umich.edu default:CP0Unimpl::unknown(); 6044661Sksewell@umich.edu } 6054661Sksewell@umich.edu } 6065222Sksewell@umich.edu default: CP0Unimpl::unknown(); 6074661Sksewell@umich.edu } 6084661Sksewell@umich.edu format CP0Control { 6094661Sksewell@umich.edu 0xA: rdpgpr({{ 6104661Sksewell@umich.edu if(Config_AR >= 1) 6114661Sksewell@umich.edu { // Rev 2 of the architecture 6125222Sksewell@umich.edu Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS); 6134661Sksewell@umich.edu } 6144661Sksewell@umich.edu else 6154661Sksewell@umich.edu { 6164661Sksewell@umich.edu fault = new ReservedInstructionFault(); 6174661Sksewell@umich.edu } 6184661Sksewell@umich.edu }}); 6194661Sksewell@umich.edu 0xE: wrpgpr({{ 6204661Sksewell@umich.edu if(Config_AR >= 1) 6214661Sksewell@umich.edu { // Rev 2 of the architecture 6225222Sksewell@umich.edu xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt); 6235222Sksewell@umich.edu // warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl); 6244661Sksewell@umich.edu } 6254661Sksewell@umich.edu else 6264661Sksewell@umich.edu { 6274661Sksewell@umich.edu fault = new ReservedInstructionFault(); 6284661Sksewell@umich.edu } 6294661Sksewell@umich.edu 6304661Sksewell@umich.edu }}); 6314661Sksewell@umich.edu } 6324661Sksewell@umich.edu 6335222Sksewell@umich.edu } 6342101SN/A 6352101SN/A //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 6362101SN/A 0x1: decode FUNCTION { 6374661Sksewell@umich.edu format CP0Control { 6384661Sksewell@umich.edu 0x18: eret({{ 6395222Sksewell@umich.edu DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 6405222Sksewell@umich.edu // Ugly hack to get the value of Status_EXL 6415222Sksewell@umich.edu if(Status_EXL == 1){ 6425222Sksewell@umich.edu DPRINTF(MipsPRA,"ERET EXL Hack\n"); 6435222Sksewell@umich.edu } 6444661Sksewell@umich.edu if(Status_ERL == 1){ 6454661Sksewell@umich.edu Status_ERL = 0; 6464661Sksewell@umich.edu NPC = ErrorEPC; 6475222Sksewell@umich.edu NNPC = ErrorEPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break 6484661Sksewell@umich.edu } 6495222Sksewell@umich.edu else { 6504661Sksewell@umich.edu NPC = EPC; 6515222Sksewell@umich.edu NNPC = EPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break 6524661Sksewell@umich.edu Status_EXL = 0; 6535222Sksewell@umich.edu if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){ 6544661Sksewell@umich.edu SRSCtl_CSS = SRSCtl_PSS; 6555250Sksewell@umich.edu //xc->setShadowSet(SRSCtl_PSS); 6564661Sksewell@umich.edu } 6574661Sksewell@umich.edu } 6585222Sksewell@umich.edu LLFlag = 0; 6595222Sksewell@umich.edu }},IsReturn,IsSerializing,IsERET); 6605222Sksewell@umich.edu 6615222Sksewell@umich.edu 0x1F: deret({{ 6625222Sksewell@umich.edu // if(EJTagImplemented()) { 6635222Sksewell@umich.edu if(Debug_DM == 1){ 6645222Sksewell@umich.edu Debug_DM = 1; 6655222Sksewell@umich.edu Debug_IEXI = 0; 6665222Sksewell@umich.edu NPC = DEPC; 6675222Sksewell@umich.edu } 6685222Sksewell@umich.edu else 6695222Sksewell@umich.edu { 6705222Sksewell@umich.edu // Undefined; 6715222Sksewell@umich.edu } 6725222Sksewell@umich.edu //} // EJTag Implemented 6735222Sksewell@umich.edu //else { 6745222Sksewell@umich.edu // Reserved Instruction Exception 6755222Sksewell@umich.edu //} 6765222Sksewell@umich.edu }},IsReturn,IsSerializing,IsERET); 6775222Sksewell@umich.edu } 6785222Sksewell@umich.edu format CP0TLB { 6795222Sksewell@umich.edu 0x01: tlbr({{ 6805222Sksewell@umich.edu MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF); 6815222Sksewell@umich.edu if(PTEntry == NULL) 6825222Sksewell@umich.edu { 6835222Sksewell@umich.edu fatal("Invalid PTE Entry received on a TLBR instruction\n"); 6845222Sksewell@umich.edu } 6855222Sksewell@umich.edu /* Setup PageMask */ 6865222Sksewell@umich.edu PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11 6875222Sksewell@umich.edu /* Setup EntryHi */ 6885222Sksewell@umich.edu EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 6895222Sksewell@umich.edu /* Setup Entry Lo0 */ 6905222Sksewell@umich.edu EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G); 6915222Sksewell@umich.edu /* Setup Entry Lo1 */ 6925222Sksewell@umich.edu EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G); 6935222Sksewell@umich.edu }}); // Need to hook up to TLB 6945222Sksewell@umich.edu 6955222Sksewell@umich.edu 0x02: tlbwi({{ 6965222Sksewell@umich.edu //Create PTE 6975222Sksewell@umich.edu MipsISA::PTE NewEntry; 6985222Sksewell@umich.edu //Write PTE 6995222Sksewell@umich.edu NewEntry.Mask = (Addr)(PageMask >> 11); 7005222Sksewell@umich.edu NewEntry.VPN = (Addr)(EntryHi >> 11); 7015222Sksewell@umich.edu /* PageGrain _ ESP Config3 _ SP */ 7025222Sksewell@umich.edu if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) { 7035222Sksewell@umich.edu NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes 7045222Sksewell@umich.edu NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled 7055222Sksewell@umich.edu } 7065222Sksewell@umich.edu NewEntry.asid = (uint8_t)(EntryHi & 0xFF); 7075222Sksewell@umich.edu 7085222Sksewell@umich.edu NewEntry.PFN0 = (Addr)(EntryLo0 >> 6); 7095222Sksewell@umich.edu NewEntry.PFN1 = (Addr)(EntryLo1 >> 6); 7105222Sksewell@umich.edu NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 7115222Sksewell@umich.edu NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 7125222Sksewell@umich.edu NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 7135222Sksewell@umich.edu NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 7145222Sksewell@umich.edu NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 7155222Sksewell@umich.edu NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 7165222Sksewell@umich.edu NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 7175222Sksewell@umich.edu /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */ 7185222Sksewell@umich.edu /* Addr Shift Amount for 1KB or larger pages */ 7195222Sksewell@umich.edu // warn("PTE->Mask: %x\n",pte->Mask); 7205222Sksewell@umich.edu if((NewEntry.Mask & 0xFFFF) == 3){ 7215222Sksewell@umich.edu NewEntry.AddrShiftAmount = 12; 7225222Sksewell@umich.edu } else if((NewEntry.Mask & 0xFFFF) == 0x0000){ 7235222Sksewell@umich.edu NewEntry.AddrShiftAmount = 10; 7245222Sksewell@umich.edu } else if((NewEntry.Mask & 0xFFFC) == 0x000C){ 7255222Sksewell@umich.edu NewEntry.AddrShiftAmount = 14; 7265222Sksewell@umich.edu } else if((NewEntry.Mask & 0xFFF0) == 0x0030){ 7275222Sksewell@umich.edu NewEntry.AddrShiftAmount = 16; 7285222Sksewell@umich.edu } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){ 7295222Sksewell@umich.edu NewEntry.AddrShiftAmount = 18; 7305222Sksewell@umich.edu } else if((NewEntry.Mask & 0xFF00) == 0x0300){ 7315222Sksewell@umich.edu NewEntry.AddrShiftAmount = 20; 7325222Sksewell@umich.edu } else if((NewEntry.Mask & 0xFC00) == 0x0C00){ 7335222Sksewell@umich.edu NewEntry.AddrShiftAmount = 22; 7345222Sksewell@umich.edu } else if((NewEntry.Mask & 0xF000) == 0x3000){ 7355222Sksewell@umich.edu NewEntry.AddrShiftAmount = 24; 7365222Sksewell@umich.edu } else if((NewEntry.Mask & 0xC000) == 0xC000){ 7375222Sksewell@umich.edu NewEntry.AddrShiftAmount = 26; 7385222Sksewell@umich.edu } else if((NewEntry.Mask & 0x30000) == 0x30000){ 7395222Sksewell@umich.edu NewEntry.AddrShiftAmount = 28; 7405222Sksewell@umich.edu } else { 7415222Sksewell@umich.edu fatal("Invalid Mask Pattern Detected!\n"); 7425222Sksewell@umich.edu } 7435222Sksewell@umich.edu NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1); 7445222Sksewell@umich.edu 7455222Sksewell@umich.edu MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr(); 7465222Sksewell@umich.edu MiscReg c3=xc->readMiscReg(MipsISA::Config3); 7475222Sksewell@umich.edu MiscReg pg=xc->readMiscReg(MipsISA::PageGrain); 7485222Sksewell@umich.edu int SP=0; 7495222Sksewell@umich.edu if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){ 7505222Sksewell@umich.edu SP=1; 7515222Sksewell@umich.edu } 7525222Sksewell@umich.edu Ptr->insertAt(NewEntry,Index & 0x7FFFFFFF,SP); 7535222Sksewell@umich.edu }}); 7545222Sksewell@umich.edu 0x06: tlbwr({{ 7555222Sksewell@umich.edu //Create PTE 7565222Sksewell@umich.edu MipsISA::PTE NewEntry; 7575222Sksewell@umich.edu //Write PTE 7585222Sksewell@umich.edu NewEntry.Mask = (Addr)(PageMask >> 11); 7595222Sksewell@umich.edu NewEntry.VPN = (Addr)(EntryHi >> 11); 7605222Sksewell@umich.edu /* PageGrain _ ESP Config3 _ SP */ 7615222Sksewell@umich.edu if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) { 7625222Sksewell@umich.edu NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes 7635222Sksewell@umich.edu NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled 7645222Sksewell@umich.edu } 7655222Sksewell@umich.edu NewEntry.asid = (uint8_t)(EntryHi & 0xFF); 7665222Sksewell@umich.edu 7675222Sksewell@umich.edu NewEntry.PFN0 = (Addr)(EntryLo0 >> 6); 7685222Sksewell@umich.edu NewEntry.PFN1 = (Addr)(EntryLo1 >> 6); 7695222Sksewell@umich.edu NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 7705222Sksewell@umich.edu NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 7715222Sksewell@umich.edu NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 7725222Sksewell@umich.edu NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 7735222Sksewell@umich.edu NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 7745222Sksewell@umich.edu NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 7755222Sksewell@umich.edu NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 7765222Sksewell@umich.edu /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */ 7775222Sksewell@umich.edu /* Addr Shift Amount for 1KB or larger pages */ 7785222Sksewell@umich.edu // warn("PTE->Mask: %x\n",pte->Mask); 7795222Sksewell@umich.edu if((NewEntry.Mask & 0xFFFF) == 3){ 7805222Sksewell@umich.edu NewEntry.AddrShiftAmount = 12; 7815222Sksewell@umich.edu } else if((NewEntry.Mask & 0xFFFF) == 0x0000){ 7825222Sksewell@umich.edu NewEntry.AddrShiftAmount = 10; 7835222Sksewell@umich.edu } else if((NewEntry.Mask & 0xFFFC) == 0x000C){ 7845222Sksewell@umich.edu NewEntry.AddrShiftAmount = 14; 7855222Sksewell@umich.edu } else if((NewEntry.Mask & 0xFFF0) == 0x0030){ 7865222Sksewell@umich.edu NewEntry.AddrShiftAmount = 16; 7875222Sksewell@umich.edu } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){ 7885222Sksewell@umich.edu NewEntry.AddrShiftAmount = 18; 7895222Sksewell@umich.edu } else if((NewEntry.Mask & 0xFF00) == 0x0300){ 7905222Sksewell@umich.edu NewEntry.AddrShiftAmount = 20; 7915222Sksewell@umich.edu } else if((NewEntry.Mask & 0xFC00) == 0x0C00){ 7925222Sksewell@umich.edu NewEntry.AddrShiftAmount = 22; 7935222Sksewell@umich.edu } else if((NewEntry.Mask & 0xF000) == 0x3000){ 7945222Sksewell@umich.edu NewEntry.AddrShiftAmount = 24; 7955222Sksewell@umich.edu } else if((NewEntry.Mask & 0xC000) == 0xC000){ 7965222Sksewell@umich.edu NewEntry.AddrShiftAmount = 26; 7975222Sksewell@umich.edu } else if((NewEntry.Mask & 0x30000) == 0x30000){ 7985222Sksewell@umich.edu NewEntry.AddrShiftAmount = 28; 7995222Sksewell@umich.edu } else { 8005222Sksewell@umich.edu fatal("Invalid Mask Pattern Detected!\n"); 8015222Sksewell@umich.edu } 8025222Sksewell@umich.edu NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1); 8035222Sksewell@umich.edu 8045222Sksewell@umich.edu MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr(); 8055222Sksewell@umich.edu MiscReg c3=xc->readMiscReg(MipsISA::Config3); 8065222Sksewell@umich.edu MiscReg pg=xc->readMiscReg(MipsISA::PageGrain); 8075222Sksewell@umich.edu int SP=0; 8085222Sksewell@umich.edu if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){ 8095222Sksewell@umich.edu SP=1; 8105222Sksewell@umich.edu } 8115222Sksewell@umich.edu Ptr->insertAt(NewEntry,Random,SP); 8124661Sksewell@umich.edu }}); 8132101SN/A 8145222Sksewell@umich.edu 0x08: tlbp({{ 8155222Sksewell@umich.edu int TLB_Index; 8165222Sksewell@umich.edu Addr VPN; 8175222Sksewell@umich.edu if(PageGrain_ESP == 1 && Config3_SP ==1){ 8185222Sksewell@umich.edu VPN = EntryHi >> 11; 8195222Sksewell@umich.edu } else { 8205222Sksewell@umich.edu VPN = ((EntryHi >> 11) & 0xFFFFFFFC); // Mask off lower 2 bits 8215222Sksewell@umich.edu } 8225222Sksewell@umich.edu TLB_Index = xc->tcBase()->getITBPtr()->probeEntry(VPN,EntryHi_ASID); 8235222Sksewell@umich.edu if(TLB_Index != -1){ // Check TLB for entry matching EntryHi 8245222Sksewell@umich.edu Index=TLB_Index; 8255222Sksewell@umich.edu // warn("\ntlbp: Match Found!\n"); 8265222Sksewell@umich.edu } else {// else, set Index = 1<<31 8275222Sksewell@umich.edu Index = (1<<31); 8285222Sksewell@umich.edu } 8295222Sksewell@umich.edu }}); 8304661Sksewell@umich.edu } 8315222Sksewell@umich.edu format CP0Unimpl { 8325222Sksewell@umich.edu 0x20: wait(); 8335222Sksewell@umich.edu } 8345222Sksewell@umich.edu default: CP0Unimpl::unknown(); 8354661Sksewell@umich.edu 8362101SN/A } 8372043SN/A } 8382027SN/A 8392101SN/A //Table A-13 MIPS32 COP1 Encoding of rs Field 8402101SN/A 0x1: decode RS_MSB { 8412041SN/A 8422101SN/A 0x0: decode RS_HI { 8432101SN/A 0x0: decode RS_LO { 8442686Sksewell@umich.edu format CP1Control { 8452742Sksewell@umich.edu 0x0: mfc1 ({{ Rt.uw = Fs.uw; }}); 8462495SN/A 8472495SN/A 0x2: cfc1({{ 8482573SN/A switch (FS) 8492573SN/A { 8502573SN/A case 0: 8512616SN/A Rt = FIR; 8522573SN/A break; 8532573SN/A case 25: 8542616SN/A Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23; 8552573SN/A break; 8562573SN/A case 26: 8572616SN/A Rt = 0 | (FCSR & 0x0003F07C); 8582573SN/A break; 8592573SN/A case 28: 8602616SN/A Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003); 8612573SN/A break; 8622573SN/A case 31: 8632616SN/A Rt = FCSR; 8642573SN/A break; 8652573SN/A default: 8665222Sksewell@umich.edu warn("FP Control Value (%d) Not Valid"); 8672573SN/A } 8685222Sksewell@umich.edu // warn("FCSR: %x, FS: %d, FIR: %x, Rt: %x\n",FCSR, FS, FIR, Rt); 8692573SN/A }}); 8702573SN/A 8712686Sksewell@umich.edu 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); 8722686Sksewell@umich.edu 8732686Sksewell@umich.edu 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); 8742686Sksewell@umich.edu 8752573SN/A 0x6: ctc1({{ 8762573SN/A switch (FS) 8772573SN/A { 8782573SN/A case 25: 8792616SN/A FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25 8802616SN/A | (FCSR & 0x01000000) // bit 24 8812616SN/A | (FCSR & 0x004FFFFF);// bit 22...0 8822573SN/A break; 8832573SN/A 8842573SN/A case 26: 8852616SN/A FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18 8862573SN/A | Rt.uw<17:12> << 12 // bit 17...12 8872616SN/A | (FCSR & 0x00000F80) << 7// bit 11...7 8882573SN/A | Rt.uw<6:2> << 2 // bit 6...2 8892616SN/A | (FCSR & 0x00000002); // bit 1...0 8902573SN/A break; 8912573SN/A 8922573SN/A case 28: 8932616SN/A FCSR = 0 | (FCSR & 0xFE000000) // move 31...25 8942573SN/A | Rt.uw<2:2> << 24 // bit 24 8952616SN/A | (FCSR & 0x00FFF000) << 23// bit 23...12 8962573SN/A | Rt.uw<11:7> << 7 // bit 24 8972616SN/A | (FCSR & 0x000007E) 8982573SN/A | Rt.uw<1:0>;// bit 22...0 8992573SN/A break; 9002573SN/A 9012573SN/A case 31: 9022616SN/A FCSR = Rt.uw; 9032573SN/A break; 9042573SN/A 9052573SN/A default: 9062495SN/A panic("FP Control Value (%d) Not Available. Ignoring Access to" 9072616SN/A "Floating Control Status Register", FS); 9082495SN/A } 9092495SN/A }}); 9102686Sksewell@umich.edu 9112686Sksewell@umich.edu 0x7: mthc1({{ 9122686Sksewell@umich.edu uint64_t fs_hi = Rt.uw; 9132686Sksewell@umich.edu uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF; 9142686Sksewell@umich.edu Fs.ud = (fs_hi << 32) | fs_lo; 9152686Sksewell@umich.edu }}); 9162686Sksewell@umich.edu 9172101SN/A } 9185222Sksewell@umich.edu format CP1Unimpl { 9195222Sksewell@umich.edu 0x1: dmfc1(); 9205222Sksewell@umich.edu 0x5: dmtc1(); 9215222Sksewell@umich.edu } 9225222Sksewell@umich.edu } 9232025SN/A 9245222Sksewell@umich.edu 0x1: 9255222Sksewell@umich.edu decode RS_LO { 9265222Sksewell@umich.edu 0x0: 9275222Sksewell@umich.edu decode ND { 9285222Sksewell@umich.edu format Branch { 9295222Sksewell@umich.edu 0x0: decode TF { 9305222Sksewell@umich.edu 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 9315222Sksewell@umich.edu }}); 9325222Sksewell@umich.edu 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 9335222Sksewell@umich.edu }}); 9345222Sksewell@umich.edu } 9355222Sksewell@umich.edu 0x1: decode TF { 9365222Sksewell@umich.edu 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 9375222Sksewell@umich.edu }}, Likely); 9385222Sksewell@umich.edu 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 9395222Sksewell@umich.edu }}, Likely); 9405222Sksewell@umich.edu } 9415222Sksewell@umich.edu } 9425222Sksewell@umich.edu } 9435222Sksewell@umich.edu format CP1Unimpl { 9445222Sksewell@umich.edu 0x1: bc1any2(); 9455222Sksewell@umich.edu 0x2: bc1any4(); 9465222Sksewell@umich.edu default: unknown(); 9475222Sksewell@umich.edu } 9485222Sksewell@umich.edu } 9492043SN/A } 9502027SN/A 9512101SN/A 0x1: decode RS_HI { 9522101SN/A 0x2: decode RS_LO { 9532101SN/A //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 9542686Sksewell@umich.edu //(( single-precision floating point)) 9552572SN/A 0x0: decode FUNCTION_HI { 9562572SN/A 0x0: decode FUNCTION_LO { 9572101SN/A format FloatOp { 9582601SN/A 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); 9592601SN/A 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); 9602601SN/A 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); 9612601SN/A 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); 9622601SN/A 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); 9632601SN/A 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); 9642686Sksewell@umich.edu 0x7: neg_s({{ Fd.sf = -Fs.sf;}}); 9652101SN/A } 9662742Sksewell@umich.edu 9672742Sksewell@umich.edu 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}}); 9682101SN/A } 9692027SN/A 9702572SN/A 0x1: decode FUNCTION_LO { 9712686Sksewell@umich.edu format FloatConvertOp { 9722686Sksewell@umich.edu 0x0: round_l_s({{ val = Fs.sf; }}, ToLong, 9732686Sksewell@umich.edu Round); 9742686Sksewell@umich.edu 0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong, 9752686Sksewell@umich.edu Trunc); 9762686Sksewell@umich.edu 0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong, 9772686Sksewell@umich.edu Ceil); 9782686Sksewell@umich.edu 0x3: floor_l_s({{ val = Fs.sf; }}, ToLong, 9792686Sksewell@umich.edu Floor); 9802686Sksewell@umich.edu 0x4: round_w_s({{ val = Fs.sf; }}, ToWord, 9812686Sksewell@umich.edu Round); 9822686Sksewell@umich.edu 0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord, 9832686Sksewell@umich.edu Trunc); 9842686Sksewell@umich.edu 0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord, 9852686Sksewell@umich.edu Ceil); 9862686Sksewell@umich.edu 0x7: floor_w_s({{ val = Fs.sf; }}, ToWord, 9872686Sksewell@umich.edu Floor); 9882101SN/A } 9892101SN/A } 9902027SN/A 9912572SN/A 0x2: decode FUNCTION_LO { 9922101SN/A 0x1: decode MOVCF { 9932686Sksewell@umich.edu format BasicOp { 9942686Sksewell@umich.edu 0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }}); 9952686Sksewell@umich.edu 0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }}); 9962101SN/A } 9972101SN/A } 9982027SN/A 9992686Sksewell@umich.edu format BasicOp { 10002686Sksewell@umich.edu 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 10012686Sksewell@umich.edu 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 10022686Sksewell@umich.edu } 10032686Sksewell@umich.edu 10042602SN/A format FloatOp { 10052602SN/A 0x5: recip_s({{ Fd = 1 / Fs; }}); 10062602SN/A 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}}); 10072101SN/A } 10085222Sksewell@umich.edu format CP1Unimpl { 10095222Sksewell@umich.edu default: unknown(); 10105222Sksewell@umich.edu } 10112101SN/A } 10125222Sksewell@umich.edu 0x3: CP1Unimpl::unknown(); 10132027SN/A 10142572SN/A 0x4: decode FUNCTION_LO { 10152603SN/A format FloatConvertOp { 10162686Sksewell@umich.edu 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble); 10172686Sksewell@umich.edu 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord); 10182686Sksewell@umich.edu 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong); 10192101SN/A } 10202055SN/A 10212686Sksewell@umich.edu 0x6: FloatOp::cvt_ps_s({{ 10222686Sksewell@umich.edu Fd.ud = (uint64_t) Fs.uw << 32 | 10232686Sksewell@umich.edu (uint64_t) Ft.uw; 10242101SN/A }}); 10255222Sksewell@umich.edu format CP1Unimpl { 10265222Sksewell@umich.edu default: unknown(); 10275222Sksewell@umich.edu } 10282101SN/A } 10295222Sksewell@umich.edu 0x5: CP1Unimpl::unknown(); 10302602SN/A 10312602SN/A 0x6: decode FUNCTION_LO { 10322603SN/A format FloatCompareOp { 10332686Sksewell@umich.edu 0x0: c_f_s({{ cond = 0; }}, SinglePrecision, 10342686Sksewell@umich.edu UnorderedFalse); 10352686Sksewell@umich.edu 0x1: c_un_s({{ cond = 0; }}, SinglePrecision, 10362686Sksewell@umich.edu UnorderedTrue); 10372686Sksewell@umich.edu 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, 10382686Sksewell@umich.edu UnorderedFalse); 10392686Sksewell@umich.edu 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 10402686Sksewell@umich.edu UnorderedTrue); 10412686Sksewell@umich.edu 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 10422686Sksewell@umich.edu UnorderedFalse); 10432686Sksewell@umich.edu 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 10442686Sksewell@umich.edu UnorderedTrue); 10452686Sksewell@umich.edu 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }}, 10462686Sksewell@umich.edu UnorderedFalse); 10472686Sksewell@umich.edu 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }}, 10482686Sksewell@umich.edu UnorderedTrue); 10492602SN/A } 10502602SN/A } 10512602SN/A 10522602SN/A 0x7: decode FUNCTION_LO { 10532686Sksewell@umich.edu format FloatCompareOp { 10542686Sksewell@umich.edu 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 10552686Sksewell@umich.edu UnorderedFalse, QnanException); 10562686Sksewell@umich.edu 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 10572686Sksewell@umich.edu UnorderedTrue, QnanException); 10582686Sksewell@umich.edu 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}}, 10592686Sksewell@umich.edu UnorderedFalse, QnanException); 10602686Sksewell@umich.edu 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, 10612686Sksewell@umich.edu UnorderedTrue, QnanException); 10622686Sksewell@umich.edu 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }}, 10632686Sksewell@umich.edu UnorderedFalse, QnanException); 10642686Sksewell@umich.edu 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }}, 10652686Sksewell@umich.edu UnorderedTrue, QnanException); 10662686Sksewell@umich.edu 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }}, 10672686Sksewell@umich.edu UnorderedFalse, QnanException); 10682686Sksewell@umich.edu 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }}, 10692686Sksewell@umich.edu UnorderedTrue, QnanException); 10702602SN/A } 10712602SN/A } 10722101SN/A } 10732055SN/A 10742101SN/A //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 10752572SN/A 0x1: decode FUNCTION_HI { 10762572SN/A 0x0: decode FUNCTION_LO { 10772101SN/A format FloatOp { 10782686Sksewell@umich.edu 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }}); 10792686Sksewell@umich.edu 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 10802686Sksewell@umich.edu 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 10812686Sksewell@umich.edu 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); 10822686Sksewell@umich.edu 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); 10832686Sksewell@umich.edu 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); 10842686Sksewell@umich.edu 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); 10852101SN/A } 10862742Sksewell@umich.edu 10872742Sksewell@umich.edu 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); 10882101SN/A } 10892027SN/A 10902572SN/A 0x1: decode FUNCTION_LO { 10912686Sksewell@umich.edu format FloatConvertOp { 10922686Sksewell@umich.edu 0x0: round_l_d({{ val = Fs.df; }}, ToLong, 10932686Sksewell@umich.edu Round); 10942686Sksewell@umich.edu 0x1: trunc_l_d({{ val = Fs.df; }}, ToLong, 10952686Sksewell@umich.edu Trunc); 10962686Sksewell@umich.edu 0x2: ceil_l_d({{ val = Fs.df; }}, ToLong, 10972686Sksewell@umich.edu Ceil); 10982686Sksewell@umich.edu 0x3: floor_l_d({{ val = Fs.df; }}, ToLong, 10992686Sksewell@umich.edu Floor); 11002686Sksewell@umich.edu 0x4: round_w_d({{ val = Fs.df; }}, ToWord, 11012686Sksewell@umich.edu Round); 11022686Sksewell@umich.edu 0x5: trunc_w_d({{ val = Fs.df; }}, ToWord, 11032686Sksewell@umich.edu Trunc); 11042686Sksewell@umich.edu 0x6: ceil_w_d({{ val = Fs.df; }}, ToWord, 11052686Sksewell@umich.edu Ceil); 11062686Sksewell@umich.edu 0x7: floor_w_d({{ val = Fs.df; }}, ToWord, 11072686Sksewell@umich.edu Floor); 11082101SN/A } 11092101SN/A } 11102027SN/A 11112572SN/A 0x2: decode FUNCTION_LO { 11122101SN/A 0x1: decode MOVCF { 11132686Sksewell@umich.edu format BasicOp { 11142686Sksewell@umich.edu 0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ? 11152686Sksewell@umich.edu Fs.df : Fd.df; 11162686Sksewell@umich.edu }}); 11172686Sksewell@umich.edu 0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ? 11182686Sksewell@umich.edu Fs.df : Fd.df; 11192686Sksewell@umich.edu }}); 11202101SN/A } 11212101SN/A } 11222027SN/A 11232101SN/A format BasicOp { 11242686Sksewell@umich.edu 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }}); 11252686Sksewell@umich.edu 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }}); 11262101SN/A } 11272027SN/A 11282605SN/A format FloatOp { 11292686Sksewell@umich.edu 0x5: recip_d({{ Fd.df = 1 / Fs.df }}); 11302605SN/A 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }}); 11312101SN/A } 11325222Sksewell@umich.edu format CP1Unimpl { 11335222Sksewell@umich.edu default: unknown(); 11345222Sksewell@umich.edu } 11355222Sksewell@umich.edu 11362101SN/A } 11372572SN/A 0x4: decode FUNCTION_LO { 11382686Sksewell@umich.edu format FloatConvertOp { 11392686Sksewell@umich.edu 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle); 11402686Sksewell@umich.edu 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 11412686Sksewell@umich.edu 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); 11422101SN/A } 11435222Sksewell@umich.edu default: CP1Unimpl::unknown(); 11442101SN/A } 11452602SN/A 11462602SN/A 0x6: decode FUNCTION_LO { 11472604SN/A format FloatCompareOp { 11482686Sksewell@umich.edu 0x0: c_f_d({{ cond = 0; }}, DoublePrecision, 11492686Sksewell@umich.edu UnorderedFalse); 11502686Sksewell@umich.edu 0x1: c_un_d({{ cond = 0; }}, DoublePrecision, 11512686Sksewell@umich.edu UnorderedTrue); 11522686Sksewell@umich.edu 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, 11532686Sksewell@umich.edu UnorderedFalse); 11542686Sksewell@umich.edu 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 11552686Sksewell@umich.edu UnorderedTrue); 11562686Sksewell@umich.edu 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 11572686Sksewell@umich.edu UnorderedFalse); 11582686Sksewell@umich.edu 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 11592686Sksewell@umich.edu UnorderedTrue); 11602686Sksewell@umich.edu 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }}, 11612686Sksewell@umich.edu UnorderedFalse); 11622686Sksewell@umich.edu 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }}, 11632686Sksewell@umich.edu UnorderedTrue); 11642602SN/A } 11652602SN/A } 11662602SN/A 11672602SN/A 0x7: decode FUNCTION_LO { 11682686Sksewell@umich.edu format FloatCompareOp { 11692686Sksewell@umich.edu 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 11702686Sksewell@umich.edu UnorderedFalse, QnanException); 11712686Sksewell@umich.edu 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 11722686Sksewell@umich.edu UnorderedTrue, QnanException); 11732686Sksewell@umich.edu 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }}, 11742686Sksewell@umich.edu UnorderedFalse, QnanException); 11752686Sksewell@umich.edu 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }}, 11762686Sksewell@umich.edu UnorderedTrue, QnanException); 11772686Sksewell@umich.edu 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }}, 11782686Sksewell@umich.edu UnorderedFalse, QnanException); 11792686Sksewell@umich.edu 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }}, 11802686Sksewell@umich.edu UnorderedTrue, QnanException); 11812686Sksewell@umich.edu 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }}, 11822686Sksewell@umich.edu UnorderedFalse, QnanException); 11832686Sksewell@umich.edu 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }}, 11842686Sksewell@umich.edu UnorderedTrue, QnanException); 11852602SN/A } 11862602SN/A } 11875222Sksewell@umich.edu default: CP1Unimpl::unknown(); 11882101SN/A } 11895222Sksewell@umich.edu 0x2: CP1Unimpl::unknown(); 11905222Sksewell@umich.edu 0x3: CP1Unimpl::unknown(); 11915222Sksewell@umich.edu 0x7: CP1Unimpl::unknown(); 11922027SN/A 11932101SN/A //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 11942101SN/A 0x4: decode FUNCTION { 11952605SN/A format FloatConvertOp { 11962686Sksewell@umich.edu 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 11972686Sksewell@umich.edu 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 11985222Sksewell@umich.edu 0x26: CP1Unimpl::cvt_ps_w(); 11992101SN/A } 12005222Sksewell@umich.edu default: CP1Unimpl::unknown(); 12012101SN/A } 12022027SN/A 12032101SN/A //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 12042101SN/A //Note: "1. Format type L is legal only if 64-bit floating point operations 12052101SN/A //are enabled." 12062101SN/A 0x5: decode FUNCTION_HI { 12072686Sksewell@umich.edu format FloatConvertOp { 12082686Sksewell@umich.edu 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 12092686Sksewell@umich.edu 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 12105222Sksewell@umich.edu 0x26: CP1Unimpl::cvt_ps_l(); 12112101SN/A } 12125222Sksewell@umich.edu default: CP1Unimpl::unknown(); 12132101SN/A } 12142101SN/A 12152101SN/A //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 12162101SN/A //Note: "1. Format type PS is legal only if 64-bit floating point operations 12172101SN/A //are enabled. " 12182572SN/A 0x6: decode FUNCTION_HI { 12192572SN/A 0x0: decode FUNCTION_LO { 12202101SN/A format Float64Op { 12212605SN/A 0x0: add_ps({{ 12222607SN/A Fd1.sf = Fs1.sf + Ft2.sf; 12232607SN/A Fd2.sf = Fs2.sf + Ft2.sf; 12242101SN/A }}); 12252605SN/A 0x1: sub_ps({{ 12262607SN/A Fd1.sf = Fs1.sf - Ft2.sf; 12272607SN/A Fd2.sf = Fs2.sf - Ft2.sf; 12282101SN/A }}); 12292605SN/A 0x2: mul_ps({{ 12302607SN/A Fd1.sf = Fs1.sf * Ft2.sf; 12312607SN/A Fd2.sf = Fs2.sf * Ft2.sf; 12322101SN/A }}); 12332605SN/A 0x5: abs_ps({{ 12342607SN/A Fd1.sf = fabs(Fs1.sf); 12352607SN/A Fd2.sf = fabs(Fs2.sf); 12362101SN/A }}); 12372605SN/A 0x6: mov_ps({{ 12382607SN/A Fd1.sf = Fs1.sf; 12392607SN/A Fd2.sf = Fs2.sf; 12402101SN/A }}); 12412605SN/A 0x7: neg_ps({{ 12422686Sksewell@umich.edu Fd1.sf = -(Fs1.sf); 12432686Sksewell@umich.edu Fd2.sf = -(Fs2.sf); 12442101SN/A }}); 12455222Sksewell@umich.edu default: CP1Unimpl::unknown(); 12462101SN/A } 12472101SN/A } 12485222Sksewell@umich.edu 0x1: CP1Unimpl::unknown(); 12492572SN/A 0x2: decode FUNCTION_LO { 12502101SN/A 0x1: decode MOVCF { 12512101SN/A format Float64Op { 12522607SN/A 0x0: movf_ps({{ 12532686Sksewell@umich.edu Fd1 = (getCondCode(FCSR, CC) == 0) ? 12542686Sksewell@umich.edu Fs1 : Fd1; 12552686Sksewell@umich.edu Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 12562686Sksewell@umich.edu Fs2 : Fd2; 12572607SN/A }}); 12582607SN/A 0x1: movt_ps({{ 12592686Sksewell@umich.edu Fd2 = (getCondCode(FCSR, CC) == 1) ? 12602686Sksewell@umich.edu Fs1 : Fd1; 12612686Sksewell@umich.edu Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 12622686Sksewell@umich.edu Fs2 : Fd2; 12632607SN/A }}); 12642101SN/A } 12652101SN/A } 12662101SN/A 12672605SN/A format Float64Op { 12682607SN/A 0x2: movz_ps({{ 12692686Sksewell@umich.edu Fd1 = (getCondCode(FCSR, CC) == 0) ? 12702686Sksewell@umich.edu Fs1 : Fd1; 12712686Sksewell@umich.edu Fd2 = (getCondCode(FCSR, CC) == 0) ? 12722686Sksewell@umich.edu Fs2 : Fd2; 12732607SN/A }}); 12742607SN/A 0x3: movn_ps({{ 12752686Sksewell@umich.edu Fd1 = (getCondCode(FCSR, CC) == 1) ? 12762686Sksewell@umich.edu Fs1 : Fd1; 12772686Sksewell@umich.edu Fd2 = (getCondCode(FCSR, CC) == 1) ? 12782686Sksewell@umich.edu Fs2 : Fd2; 12792607SN/A }}); 12802135SN/A } 12815222Sksewell@umich.edu default: CP1Unimpl::unknown(); 12822135SN/A 12832101SN/A } 12845222Sksewell@umich.edu 0x3: CP1Unimpl::unknown(); 12852572SN/A 0x4: decode FUNCTION_LO { 12862686Sksewell@umich.edu 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }}); 12875222Sksewell@umich.edu default: CP1Unimpl::unknown(); 12882101SN/A } 12892101SN/A 12902572SN/A 0x5: decode FUNCTION_LO { 12912686Sksewell@umich.edu 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); 12922686Sksewell@umich.edu 12932101SN/A format Float64Op { 12942686Sksewell@umich.edu 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 12952686Sksewell@umich.edu Ft1.uw; 12962686Sksewell@umich.edu }}); 12972686Sksewell@umich.edu 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 12982686Sksewell@umich.edu Ft2.uw; 12992686Sksewell@umich.edu }}); 13002686Sksewell@umich.edu 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 13012686Sksewell@umich.edu Ft1.uw; 13022686Sksewell@umich.edu }}); 13032686Sksewell@umich.edu 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 13042686Sksewell@umich.edu Ft2.uw; 13052686Sksewell@umich.edu }}); 13062101SN/A } 13075222Sksewell@umich.edu default: CP1Unimpl::unknown(); 13082101SN/A } 13092602SN/A 13102602SN/A 0x6: decode FUNCTION_LO { 13112608SN/A format FloatPSCompareOp { 13122686Sksewell@umich.edu 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 13132686Sksewell@umich.edu UnorderedFalse); 13142686Sksewell@umich.edu 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 13152686Sksewell@umich.edu UnorderedTrue); 13162686Sksewell@umich.edu 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 13172686Sksewell@umich.edu {{ cond2 = (Fs2.sf == Ft2.sf); }}, 13182686Sksewell@umich.edu UnorderedFalse); 13192686Sksewell@umich.edu 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 13202686Sksewell@umich.edu {{ cond2 = (Fs2.sf == Ft2.sf); }}, 13212686Sksewell@umich.edu UnorderedTrue); 13222686Sksewell@umich.edu 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 13232686Sksewell@umich.edu {{ cond2 = (Fs2.sf < Ft2.sf); }}, 13242686Sksewell@umich.edu UnorderedFalse); 13252686Sksewell@umich.edu 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }}, 13262686Sksewell@umich.edu {{ cond2 = (Fs2.sf < Ft2.sf); }}, 13272686Sksewell@umich.edu UnorderedTrue); 13282686Sksewell@umich.edu 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }}, 13292686Sksewell@umich.edu {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 13302686Sksewell@umich.edu UnorderedFalse); 13312686Sksewell@umich.edu 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 13322686Sksewell@umich.edu {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 13332686Sksewell@umich.edu UnorderedTrue); 13342602SN/A } 13352602SN/A } 13362602SN/A 13372602SN/A 0x7: decode FUNCTION_LO { 13382686Sksewell@umich.edu format FloatPSCompareOp { 13392686Sksewell@umich.edu 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 13402686Sksewell@umich.edu UnorderedFalse, QnanException); 13412686Sksewell@umich.edu 0x1: c_ngle_ps({{ cond1 = 0; }}, 13422686Sksewell@umich.edu {{ cond2 = 0; }}, 13432686Sksewell@umich.edu UnorderedTrue, QnanException); 13442686Sksewell@umich.edu 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 13452686Sksewell@umich.edu {{ cond2 = (Fs2.sf == Ft2.sf); }}, 13462686Sksewell@umich.edu UnorderedFalse, QnanException); 13472686Sksewell@umich.edu 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 13482686Sksewell@umich.edu {{ cond2 = (Fs2.sf == Ft2.sf); }}, 13492686Sksewell@umich.edu UnorderedTrue, QnanException); 13502686Sksewell@umich.edu 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 13512686Sksewell@umich.edu {{ cond2 = (Fs2.sf < Ft2.sf); }}, 13522686Sksewell@umich.edu UnorderedFalse, QnanException); 13532686Sksewell@umich.edu 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 13542686Sksewell@umich.edu {{ cond2 = (Fs2.sf < Ft2.sf); }}, 13552686Sksewell@umich.edu UnorderedTrue, QnanException); 13562686Sksewell@umich.edu 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 13572686Sksewell@umich.edu {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 13582686Sksewell@umich.edu UnorderedFalse, QnanException); 13592686Sksewell@umich.edu 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 13602686Sksewell@umich.edu {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 13612686Sksewell@umich.edu UnorderedTrue, QnanException); 13622602SN/A } 13632602SN/A } 13642101SN/A } 13652101SN/A } 13665222Sksewell@umich.edu default: CP1Unimpl::unknown(); 13672101SN/A } 13682101SN/A } 13692101SN/A 13702101SN/A //Table A-19 MIPS32 COP2 Encoding of rs Field 13712101SN/A 0x2: decode RS_MSB { 13725222Sksewell@umich.edu format CP2Unimpl { 13732686Sksewell@umich.edu 0x0: decode RS_HI { 13742686Sksewell@umich.edu 0x0: decode RS_LO { 13752101SN/A 0x0: mfc2(); 13762101SN/A 0x2: cfc2(); 13772101SN/A 0x3: mfhc2(); 13782101SN/A 0x4: mtc2(); 13792101SN/A 0x6: ctc2(); 13802101SN/A 0x7: mftc2(); 13815222Sksewell@umich.edu default: unknown(); 13822101SN/A } 13832101SN/A 13842686Sksewell@umich.edu 0x1: decode ND { 13852686Sksewell@umich.edu 0x0: decode TF { 13862101SN/A 0x0: bc2f(); 13872101SN/A 0x1: bc2t(); 13885222Sksewell@umich.edu default: unknown(); 13892101SN/A } 13902101SN/A 13912686Sksewell@umich.edu 0x1: decode TF { 13922101SN/A 0x0: bc2fl(); 13932101SN/A 0x1: bc2tl(); 13945222Sksewell@umich.edu default: unknown(); 13952101SN/A } 13965222Sksewell@umich.edu default: unknown(); 13975222Sksewell@umich.edu 13985222Sksewell@umich.edu } 13995222Sksewell@umich.edu default: unknown(); 14005222Sksewell@umich.edu 14015222Sksewell@umich.edu } 14025222Sksewell@umich.edu default: unknown(); 14032101SN/A } 14042101SN/A } 14052101SN/A 14062101SN/A //Table A-20 MIPS64 COP1X Encoding of Function Field 1 14072101SN/A //Note: "COP1X instructions are legal only if 64-bit floating point 14082101SN/A //operations are enabled." 14092101SN/A 0x3: decode FUNCTION_HI { 14102101SN/A 0x0: decode FUNCTION_LO { 14112686Sksewell@umich.edu format LoadIndexedMemory { 14122742Sksewell@umich.edu 0x0: lwxc1({{ Fd.uw = Mem.uw;}}); 14132742Sksewell@umich.edu 0x1: ldxc1({{ Fd.ud = Mem.ud;}}); 14142750Sksewell@umich.edu 0x5: luxc1({{ Fd.ud = Mem.ud;}}, 14152742Sksewell@umich.edu {{ EA = (Rs + Rt) & ~7; }}); 14162101SN/A } 14172043SN/A } 14182027SN/A 14192101SN/A 0x1: decode FUNCTION_LO { 14202686Sksewell@umich.edu format StoreIndexedMemory { 14212742Sksewell@umich.edu 0x0: swxc1({{ Mem.uw = Fs.uw;}}); 14222742Sksewell@umich.edu 0x1: sdxc1({{ Mem.ud = Fs.ud;}}); 14232742Sksewell@umich.edu 0x5: suxc1({{ Mem.ud = Fs.ud;}}, 14242742Sksewell@umich.edu {{ EA = (Rs + Rt) & ~7; }}); 14252046SN/A } 14262084SN/A 14272686Sksewell@umich.edu 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 14282101SN/A } 14292027SN/A 14302686Sksewell@umich.edu 0x3: decode FUNCTION_LO { 14312686Sksewell@umich.edu 0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) { 14322686Sksewell@umich.edu Fd.ud = Fs.ud; 14332686Sksewell@umich.edu } else if (Rs<2:0> == 4) { 14342686Sksewell@umich.edu #if BYTE_ORDER == BIG_ENDIAN 14352686Sksewell@umich.edu Fd.ud = Fs.ud<31:0> << 32 | 14362686Sksewell@umich.edu Ft.ud<63:32>; 14372686Sksewell@umich.edu #elif BYTE_ORDER == LITTLE_ENDIAN 14382686Sksewell@umich.edu Fd.ud = Ft.ud<31:0> << 32 | 14392686Sksewell@umich.edu Fs.ud<63:32>; 14402686Sksewell@umich.edu #endif 14412686Sksewell@umich.edu } else { 14422686Sksewell@umich.edu Fd.ud = Fd.ud; 14432686Sksewell@umich.edu } 14442686Sksewell@umich.edu }}); 14452686Sksewell@umich.edu } 14462027SN/A 14472686Sksewell@umich.edu format FloatAccOp { 14482686Sksewell@umich.edu 0x4: decode FUNCTION_LO { 14492686Sksewell@umich.edu 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); 14502686Sksewell@umich.edu 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 14512686Sksewell@umich.edu 0x6: madd_ps({{ 14522686Sksewell@umich.edu Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; 14532686Sksewell@umich.edu Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df; 14542686Sksewell@umich.edu }}); 14552686Sksewell@umich.edu } 14562027SN/A 14572686Sksewell@umich.edu 0x5: decode FUNCTION_LO { 14582686Sksewell@umich.edu 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }}); 14592686Sksewell@umich.edu 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }}); 14602686Sksewell@umich.edu 0x6: msub_ps({{ 14612686Sksewell@umich.edu Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df; 14622686Sksewell@umich.edu Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df; 14632686Sksewell@umich.edu }}); 14642686Sksewell@umich.edu } 14652027SN/A 14662686Sksewell@umich.edu 0x6: decode FUNCTION_LO { 14672686Sksewell@umich.edu 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 14682686Sksewell@umich.edu 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }}); 14692686Sksewell@umich.edu 0x6: nmadd_ps({{ 14702686Sksewell@umich.edu Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df); 14712686Sksewell@umich.edu Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df); 14722686Sksewell@umich.edu }}); 14732686Sksewell@umich.edu } 14742027SN/A 14752686Sksewell@umich.edu 0x7: decode FUNCTION_LO { 14762686Sksewell@umich.edu 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 14772686Sksewell@umich.edu 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 14782686Sksewell@umich.edu 0x6: nmsub_ps({{ 14792686Sksewell@umich.edu Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df); 14802686Sksewell@umich.edu Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); 14812686Sksewell@umich.edu }}); 14822046SN/A } 14832686Sksewell@umich.edu 14842101SN/A } 14852043SN/A } 14862025SN/A 14872686Sksewell@umich.edu format Branch { 14882686Sksewell@umich.edu 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely); 14892686Sksewell@umich.edu 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely); 14902686Sksewell@umich.edu 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely); 14912686Sksewell@umich.edu 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely); 14922046SN/A } 14932084SN/A } 14942024SN/A 14952686Sksewell@umich.edu 0x3: decode OPCODE_LO { 14962043SN/A //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 14972043SN/A 0x4: decode FUNCTION_HI { 14982686Sksewell@umich.edu 0x0: decode FUNCTION_LO { 14992686Sksewell@umich.edu 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd; 15004661Sksewell@umich.edu Rd.sw = temp1<31:0>; 15015222Sksewell@umich.edu }}, IntMultOp); 15022027SN/A 15034661Sksewell@umich.edu format HiLoRdSelValOp { 15045222Sksewell@umich.edu 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }}, IntMultOp); 15055222Sksewell@umich.edu 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }}, IntMultOp); 15065222Sksewell@umich.edu 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }}, IntMultOp); 15075222Sksewell@umich.edu 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }}, IntMultOp); 15082043SN/A } 15092043SN/A } 15102027SN/A 15112043SN/A 0x4: decode FUNCTION_LO { 15122101SN/A format BasicOp { 15132686Sksewell@umich.edu 0x0: clz({{ int cnt = 32; 15144661Sksewell@umich.edu for (int idx = 31; idx >= 0; idx--) { 15154661Sksewell@umich.edu if( Rs<idx:idx> == 1) { 15164661Sksewell@umich.edu cnt = 31 - idx; 15174661Sksewell@umich.edu break; 15184661Sksewell@umich.edu } 15194661Sksewell@umich.edu } 15204661Sksewell@umich.edu Rd.uw = cnt; 15214661Sksewell@umich.edu }}); 15222686Sksewell@umich.edu 0x1: clo({{ int cnt = 32; 15234661Sksewell@umich.edu for (int idx = 31; idx >= 0; idx--) { 15244661Sksewell@umich.edu if( Rs<idx:idx> == 0) { 15254661Sksewell@umich.edu cnt = 31 - idx; 15264661Sksewell@umich.edu break; 15274661Sksewell@umich.edu } 15284661Sksewell@umich.edu } 15294661Sksewell@umich.edu Rd.uw = cnt; 15304661Sksewell@umich.edu }}); 15312101SN/A } 15322043SN/A } 15332027SN/A 15342043SN/A 0x7: decode FUNCTION_LO { 15352686Sksewell@umich.edu 0x7: FailUnimpl::sdbbp(); 15362043SN/A } 15372043SN/A } 15382024SN/A 15392686Sksewell@umich.edu //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 15402686Sksewell@umich.edu //of the Architecture 15412043SN/A 0x7: decode FUNCTION_HI { 15422101SN/A 0x0: decode FUNCTION_LO { 15432686Sksewell@umich.edu format BasicOp { 15442742Sksewell@umich.edu 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); 15452686Sksewell@umich.edu 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | 15462686Sksewell@umich.edu bits(Rs.uw, MSB-LSB, 0) << LSB | 15472686Sksewell@umich.edu bits(Rt.uw, LSB-1, 0); 15482686Sksewell@umich.edu }}); 15492046SN/A } 15502101SN/A } 15512026SN/A 15522101SN/A 0x1: decode FUNCTION_LO { 15534661Sksewell@umich.edu format MT_Control { 15544661Sksewell@umich.edu 0x0: fork({{ forkThread(xc->tcBase(), fault, RD, Rs, Rt); }}, 15554661Sksewell@umich.edu UserMode); 15564661Sksewell@umich.edu 0x1: yield({{ Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, YQMask); }}, 15574661Sksewell@umich.edu UserMode); 15584661Sksewell@umich.edu } 15594661Sksewell@umich.edu 15604661Sksewell@umich.edu //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 15614661Sksewell@umich.edu 0x2: decode OP_HI { 15624661Sksewell@umich.edu 0x0: decode OP_LO { 15634661Sksewell@umich.edu format LoadIndexedMemory { 15644661Sksewell@umich.edu 0x0: lwx({{ Rd.sw = Mem.sw; }}); 15654661Sksewell@umich.edu 0x4: lhx({{ Rd.sw = Mem.sh; }}); 15664661Sksewell@umich.edu 0x6: lbux({{ Rd.uw = Mem.ub; }}); 15674661Sksewell@umich.edu } 15684661Sksewell@umich.edu } 15694661Sksewell@umich.edu } 15704661Sksewell@umich.edu 0x4: DspIntOp::insv({{ int pos = dspctl<5:0>; 15714661Sksewell@umich.edu int size = dspctl<12:7>-1; 15724661Sksewell@umich.edu Rt.uw = insertBits( Rt.uw, pos+size, pos, Rs.uw<size:0> ); }}); 15734661Sksewell@umich.edu } 15744661Sksewell@umich.edu 15754661Sksewell@umich.edu 0x2: decode FUNCTION_LO { 15764661Sksewell@umich.edu 15774661Sksewell@umich.edu //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field (DSP ASE MANUAL) 15784661Sksewell@umich.edu 0x0: decode OP_HI { 15794661Sksewell@umich.edu 0x0: decode OP_LO { 15804661Sksewell@umich.edu format DspIntOp { 15814661Sksewell@umich.edu 0x0: addu_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, 15824661Sksewell@umich.edu NOSATURATE, UNSIGNED, &dspctl ); }}); 15834661Sksewell@umich.edu 0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, 15844661Sksewell@umich.edu NOSATURATE, UNSIGNED, &dspctl ); }}); 15854661Sksewell@umich.edu 0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, 15864661Sksewell@umich.edu SATURATE, UNSIGNED, &dspctl ); }}); 15874661Sksewell@umich.edu 0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, 15884661Sksewell@umich.edu SATURATE, UNSIGNED, &dspctl ); }}); 15894661Sksewell@umich.edu 0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, 15905222Sksewell@umich.edu MODE_L, &dspctl ); }}, IntMultOp); 15914661Sksewell@umich.edu 0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, 15925222Sksewell@umich.edu MODE_R, &dspctl ); }}, IntMultOp); 15934661Sksewell@umich.edu } 15944661Sksewell@umich.edu } 15954661Sksewell@umich.edu 0x1: decode OP_LO { 15964661Sksewell@umich.edu format DspIntOp { 15974661Sksewell@umich.edu 0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 15984661Sksewell@umich.edu NOSATURATE, UNSIGNED, &dspctl ); }}); 15994661Sksewell@umich.edu 0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 16004661Sksewell@umich.edu NOSATURATE, UNSIGNED, &dspctl ); }}); 16014661Sksewell@umich.edu 0x2: addq_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 16024661Sksewell@umich.edu NOSATURATE, SIGNED, &dspctl ); }}); 16034661Sksewell@umich.edu 0x3: subq_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 16044661Sksewell@umich.edu NOSATURATE, SIGNED, &dspctl ); }}); 16054661Sksewell@umich.edu 0x4: addu_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 16064661Sksewell@umich.edu SATURATE, UNSIGNED, &dspctl ); }}); 16074661Sksewell@umich.edu 0x5: subu_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 16084661Sksewell@umich.edu SATURATE, UNSIGNED, &dspctl ); }}); 16094661Sksewell@umich.edu 0x6: addq_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, 16104661Sksewell@umich.edu SATURATE, SIGNED, &dspctl ); }}); 16114661Sksewell@umich.edu 0x7: subq_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, 16124661Sksewell@umich.edu SATURATE, SIGNED, &dspctl ); }}); 16134661Sksewell@umich.edu } 16144661Sksewell@umich.edu } 16154661Sksewell@umich.edu 0x2: decode OP_LO { 16164661Sksewell@umich.edu format DspIntOp { 16174661Sksewell@umich.edu 0x0: addsc({{ int64_t dresult; 16184661Sksewell@umich.edu dresult = Rs.ud + Rt.ud; 16194661Sksewell@umich.edu Rd.sw = dresult<31:0>; 16204661Sksewell@umich.edu dspctl = insertBits( dspctl, 13, 13, 16214661Sksewell@umich.edu dresult<32:32> ); }}); 16224661Sksewell@umich.edu 0x1: addwc({{ int64_t dresult; 16234661Sksewell@umich.edu dresult = Rs.sd + Rt.sd + dspctl<13:13>; 16244661Sksewell@umich.edu Rd.sw = dresult<31:0>; 16254661Sksewell@umich.edu if( dresult<32:32> != dresult<31:31> ) 16264661Sksewell@umich.edu dspctl = insertBits( dspctl, 20, 20, 1 ); }}); 16274661Sksewell@umich.edu 0x2: modsub({{ Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : Rs.sw - Rt.sw<7:0>; }}); 16284661Sksewell@umich.edu 0x4: raddu_w_qb({{ Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> + 16294661Sksewell@umich.edu Rs.uw<15:8> + Rs.uw<7:0>; }}); 16304661Sksewell@umich.edu 0x6: addq_s_w({{ Rd.sw = dspAdd( Rs.sw, Rt.sw, SIMD_FMT_W, 16314661Sksewell@umich.edu SATURATE, SIGNED, &dspctl ); }}); 16324661Sksewell@umich.edu 0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W, 16334661Sksewell@umich.edu SATURATE, SIGNED, &dspctl ); }}); 16344661Sksewell@umich.edu } 16354661Sksewell@umich.edu } 16364661Sksewell@umich.edu 0x3: decode OP_LO { 16374661Sksewell@umich.edu format DspIntOp { 16384661Sksewell@umich.edu 0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, 16395222Sksewell@umich.edu MODE_L, &dspctl ); }}, IntMultOp); 16404661Sksewell@umich.edu 0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, 16415222Sksewell@umich.edu MODE_R, &dspctl ); }}, IntMultOp); 16424661Sksewell@umich.edu 0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, 16435222Sksewell@umich.edu SATURATE, NOROUND, &dspctl ); }}, IntMultOp); 16444661Sksewell@umich.edu 0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, 16455222Sksewell@umich.edu SATURATE, ROUND, &dspctl ); }}, IntMultOp); 16464661Sksewell@umich.edu } 16474661Sksewell@umich.edu } 16484661Sksewell@umich.edu } 16494661Sksewell@umich.edu 16504661Sksewell@umich.edu //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL) 16514661Sksewell@umich.edu 0x1: decode OP_HI { 16524661Sksewell@umich.edu 0x0: decode OP_LO { 16534661Sksewell@umich.edu format DspIntOp { 16544661Sksewell@umich.edu 0x0: cmpu_eq_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 16554661Sksewell@umich.edu UNSIGNED, CMP_EQ, &dspctl ); }}); 16564661Sksewell@umich.edu 0x1: cmpu_lt_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 16574661Sksewell@umich.edu UNSIGNED, CMP_LT, &dspctl ); }}); 16584661Sksewell@umich.edu 0x2: cmpu_le_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, 16594661Sksewell@umich.edu UNSIGNED, CMP_LE, &dspctl ); }}); 16604661Sksewell@umich.edu 0x3: pick_qb({{ Rd.uw = dspPick( Rs.uw, Rt.uw, 16614661Sksewell@umich.edu SIMD_FMT_QB, &dspctl ); }}); 16624661Sksewell@umich.edu 0x4: cmpgu_eq_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 16634661Sksewell@umich.edu UNSIGNED, CMP_EQ ); }}); 16644661Sksewell@umich.edu 0x5: cmpgu_lt_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 16654661Sksewell@umich.edu UNSIGNED, CMP_LT ); }}); 16664661Sksewell@umich.edu 0x6: cmpgu_le_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, 16674661Sksewell@umich.edu UNSIGNED, CMP_LE ); }}); 16684661Sksewell@umich.edu } 16694661Sksewell@umich.edu } 16704661Sksewell@umich.edu 0x1: decode OP_LO { 16714661Sksewell@umich.edu format DspIntOp { 16724661Sksewell@umich.edu 0x0: cmp_eq_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 16734661Sksewell@umich.edu SIGNED, CMP_EQ, &dspctl ); }}); 16744661Sksewell@umich.edu 0x1: cmp_lt_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 16754661Sksewell@umich.edu SIGNED, CMP_LT, &dspctl ); }}); 16764661Sksewell@umich.edu 0x2: cmp_le_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, 16774661Sksewell@umich.edu SIGNED, CMP_LE, &dspctl ); }}); 16784661Sksewell@umich.edu 0x3: pick_ph({{ Rd.uw = dspPick( Rs.uw, Rt.uw, 16794661Sksewell@umich.edu SIMD_FMT_PH, &dspctl ); }}); 16804661Sksewell@umich.edu 0x4: precrq_qb_ph({{ Rd.uw = Rs.uw<31:24> << 24 | 16814661Sksewell@umich.edu Rs.uw<15:8> << 16 | 16824661Sksewell@umich.edu Rt.uw<31:24> << 8 | 16834661Sksewell@umich.edu Rt.uw<15:8>; }}); 16844661Sksewell@umich.edu 0x5: precr_qb_ph({{ Rd.uw = Rs.uw<23:16> << 24 | 16854661Sksewell@umich.edu Rs.uw<7:0> << 16 | 16864661Sksewell@umich.edu Rt.uw<23:16> << 8 | 16874661Sksewell@umich.edu Rt.uw<7:0>; }}); 16884661Sksewell@umich.edu 0x6: packrl_ph({{ Rd.uw = dspPack( Rs.uw, Rt.uw, 16894661Sksewell@umich.edu SIMD_FMT_PH ); }}); 16904661Sksewell@umich.edu 0x7: precrqu_s_qb_ph({{ Rd.uw = dspPrecrqu( Rs.uw, Rt.uw, &dspctl ); }}); 16914661Sksewell@umich.edu } 16924661Sksewell@umich.edu } 16934661Sksewell@umich.edu 0x2: decode OP_LO { 16944661Sksewell@umich.edu format DspIntOp { 16954661Sksewell@umich.edu 0x4: precrq_ph_w({{ Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; }}); 16964661Sksewell@umich.edu 0x5: precrq_rs_ph_w({{ Rd.uw = dspPrecrq( Rs.uw, Rt.uw, SIMD_FMT_W, &dspctl ); }}); 16974661Sksewell@umich.edu } 16984661Sksewell@umich.edu } 16994661Sksewell@umich.edu 0x3: decode OP_LO { 17004661Sksewell@umich.edu format DspIntOp { 17014661Sksewell@umich.edu 0x0: cmpgdu_eq_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 17024661Sksewell@umich.edu UNSIGNED, CMP_EQ, &dspctl ); }}); 17034661Sksewell@umich.edu 0x1: cmpgdu_lt_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 17044661Sksewell@umich.edu UNSIGNED, CMP_LT, &dspctl ); }}); 17054661Sksewell@umich.edu 0x2: cmpgdu_le_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, 17064661Sksewell@umich.edu UNSIGNED, CMP_LE, &dspctl ); }}); 17074661Sksewell@umich.edu 0x6: precr_sra_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, 17084661Sksewell@umich.edu SIMD_FMT_W, NOROUND ); }}); 17094661Sksewell@umich.edu 0x7: precr_sra_r_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, 17104661Sksewell@umich.edu SIMD_FMT_W, ROUND ); }}); 17114661Sksewell@umich.edu } 17124661Sksewell@umich.edu } 17134661Sksewell@umich.edu } 17144661Sksewell@umich.edu 17154661Sksewell@umich.edu //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field (DSP ASE MANUAL) 17164661Sksewell@umich.edu 0x2: decode OP_HI { 17174661Sksewell@umich.edu 0x0: decode OP_LO { 17184661Sksewell@umich.edu format DspIntOp { 17194661Sksewell@umich.edu 0x1: absq_s_qb({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_QB, &dspctl );}}); 17204661Sksewell@umich.edu 0x2: repl_qb({{ Rd.uw = RS_RT<7:0> << 24 | 17214661Sksewell@umich.edu RS_RT<7:0> << 16 | 17224661Sksewell@umich.edu RS_RT<7:0> << 8 | 17234661Sksewell@umich.edu RS_RT<7:0>; }}); 17244661Sksewell@umich.edu 0x3: replv_qb({{ Rd.sw = Rt.uw<7:0> << 24 | 17254661Sksewell@umich.edu Rt.uw<7:0> << 16 | 17264661Sksewell@umich.edu Rt.uw<7:0> << 8 | 17274661Sksewell@umich.edu Rt.uw<7:0>; }}); 17284661Sksewell@umich.edu 0x4: precequ_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 17294661Sksewell@umich.edu SIMD_FMT_PH, SIGNED, MODE_L ); }}); 17304661Sksewell@umich.edu 0x5: precequ_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 17314661Sksewell@umich.edu SIMD_FMT_PH, SIGNED, MODE_R ); }}); 17324661Sksewell@umich.edu 0x6: precequ_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 17334661Sksewell@umich.edu SIMD_FMT_PH, SIGNED, MODE_LA ); }}); 17344661Sksewell@umich.edu 0x7: precequ_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 17354661Sksewell@umich.edu SIMD_FMT_PH, SIGNED, MODE_RA ); }}); 17364661Sksewell@umich.edu } 17374661Sksewell@umich.edu } 17384661Sksewell@umich.edu 0x1: decode OP_LO { 17394661Sksewell@umich.edu format DspIntOp { 17404661Sksewell@umich.edu 0x1: absq_s_ph({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_PH, &dspctl ); }}); 17414661Sksewell@umich.edu 0x2: repl_ph({{ Rd.uw = (sext<10>(RS_RT))<15:0> << 16 | 17424661Sksewell@umich.edu (sext<10>(RS_RT))<15:0>; }}); 17434661Sksewell@umich.edu 0x3: replv_ph({{ Rd.uw = Rt.uw<15:0> << 16 | 17444661Sksewell@umich.edu Rt.uw<15:0>; }}); 17454661Sksewell@umich.edu 0x4: preceq_w_phl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, 17464661Sksewell@umich.edu SIMD_FMT_W, SIGNED, MODE_L ); }}); 17474661Sksewell@umich.edu 0x5: preceq_w_phr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, 17484661Sksewell@umich.edu SIMD_FMT_W, SIGNED, MODE_R ); }}); 17494661Sksewell@umich.edu } 17504661Sksewell@umich.edu } 17514661Sksewell@umich.edu 0x2: decode OP_LO { 17524661Sksewell@umich.edu format DspIntOp { 17534661Sksewell@umich.edu 0x1: absq_s_w({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_W, &dspctl ); }}); 17544661Sksewell@umich.edu } 17554661Sksewell@umich.edu } 17564661Sksewell@umich.edu 0x3: decode OP_LO { 17574661Sksewell@umich.edu 0x3: IntOp::bitrev({{ Rd.uw = bitrev( Rt.uw<15:0> ); }}); 17584661Sksewell@umich.edu format DspIntOp { 17594661Sksewell@umich.edu 0x4: preceu_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 17604661Sksewell@umich.edu SIMD_FMT_PH, UNSIGNED, MODE_L ); }}); 17614661Sksewell@umich.edu 0x5: preceu_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 17624661Sksewell@umich.edu SIMD_FMT_PH, UNSIGNED, MODE_R ); }}); 17634661Sksewell@umich.edu 0x6: preceu_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 17644661Sksewell@umich.edu SIMD_FMT_PH, UNSIGNED, MODE_LA ); }}); 17654661Sksewell@umich.edu 0x7: preceu_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, 17664661Sksewell@umich.edu SIMD_FMT_PH, UNSIGNED, MODE_RA ); }}); 17674661Sksewell@umich.edu } 17684661Sksewell@umich.edu } 17694661Sksewell@umich.edu } 17704661Sksewell@umich.edu 17714661Sksewell@umich.edu //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field (DSP ASE MANUAL) 17724661Sksewell@umich.edu 0x3: decode OP_HI { 17734661Sksewell@umich.edu 0x0: decode OP_LO { 17744661Sksewell@umich.edu format DspIntOp { 17754661Sksewell@umich.edu 0x0: shll_qb({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_QB, 17764661Sksewell@umich.edu NOSATURATE, UNSIGNED, &dspctl ); }}); 17774661Sksewell@umich.edu 0x1: shrl_qb({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_QB, 17784661Sksewell@umich.edu UNSIGNED ); }}); 17794661Sksewell@umich.edu 0x2: shllv_qb({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_QB, 17804661Sksewell@umich.edu NOSATURATE, UNSIGNED, &dspctl ); }}); 17814661Sksewell@umich.edu 0x3: shrlv_qb({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_QB, 17824661Sksewell@umich.edu UNSIGNED ); }}); 17834661Sksewell@umich.edu 0x4: shra_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, 17844661Sksewell@umich.edu NOROUND, SIGNED, &dspctl ); }}); 17854661Sksewell@umich.edu 0x5: shra_r_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, 17864661Sksewell@umich.edu ROUND, SIGNED, &dspctl ); }}); 17874661Sksewell@umich.edu 0x6: shrav_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, 17884661Sksewell@umich.edu NOROUND, SIGNED, &dspctl ); }}); 17894661Sksewell@umich.edu 0x7: shrav_r_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, 17904661Sksewell@umich.edu ROUND, SIGNED, &dspctl ); }}); 17914661Sksewell@umich.edu } 17924661Sksewell@umich.edu } 17934661Sksewell@umich.edu 0x1: decode OP_LO { 17944661Sksewell@umich.edu format DspIntOp { 17954661Sksewell@umich.edu 0x0: shll_ph({{ Rd.uw = dspShll( Rt.uw, RS, SIMD_FMT_PH, 17964661Sksewell@umich.edu NOSATURATE, SIGNED, &dspctl ); }}); 17974661Sksewell@umich.edu 0x1: shra_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, 17984661Sksewell@umich.edu NOROUND, SIGNED, &dspctl ); }}); 17994661Sksewell@umich.edu 0x2: shllv_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, 18004661Sksewell@umich.edu NOSATURATE, SIGNED, &dspctl ); }}); 18014661Sksewell@umich.edu 0x3: shrav_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, 18024661Sksewell@umich.edu NOROUND, SIGNED, &dspctl ); }}); 18034661Sksewell@umich.edu 0x4: shll_s_ph({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_PH, 18044661Sksewell@umich.edu SATURATE, SIGNED, &dspctl ); }}); 18054661Sksewell@umich.edu 0x5: shra_r_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, 18064661Sksewell@umich.edu ROUND, SIGNED, &dspctl ); }}); 18074661Sksewell@umich.edu 0x6: shllv_s_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, 18084661Sksewell@umich.edu SATURATE, SIGNED, &dspctl ); }}); 18094661Sksewell@umich.edu 0x7: shrav_r_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, 18104661Sksewell@umich.edu ROUND, SIGNED, &dspctl ); }}); 18114661Sksewell@umich.edu } 18124661Sksewell@umich.edu } 18134661Sksewell@umich.edu 0x2: decode OP_LO { 18144661Sksewell@umich.edu format DspIntOp { 18154661Sksewell@umich.edu 0x4: shll_s_w({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_W, 18164661Sksewell@umich.edu SATURATE, SIGNED, &dspctl ); }}); 18174661Sksewell@umich.edu 0x5: shra_r_w({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_W, 18184661Sksewell@umich.edu ROUND, SIGNED, &dspctl ); }}); 18194661Sksewell@umich.edu 0x6: shllv_s_w({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_W, 18204661Sksewell@umich.edu SATURATE, SIGNED, &dspctl ); }}); 18214661Sksewell@umich.edu 0x7: shrav_r_w({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_W, 18224661Sksewell@umich.edu ROUND, SIGNED, &dspctl ); }}); 18234661Sksewell@umich.edu } 18244661Sksewell@umich.edu } 18254661Sksewell@umich.edu 0x3: decode OP_LO { 18264661Sksewell@umich.edu format DspIntOp { 18274661Sksewell@umich.edu 0x1: shrl_ph({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_PH, 18284661Sksewell@umich.edu UNSIGNED ); }}); 18294661Sksewell@umich.edu 0x3: shrlv_ph({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_PH, 18304661Sksewell@umich.edu UNSIGNED ); }}); 18314661Sksewell@umich.edu } 18324661Sksewell@umich.edu } 18334661Sksewell@umich.edu } 18344661Sksewell@umich.edu } 18354661Sksewell@umich.edu 18364661Sksewell@umich.edu 0x3: decode FUNCTION_LO { 18374661Sksewell@umich.edu 18384661Sksewell@umich.edu //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field (DSP ASE Rev2 Manual) 18394661Sksewell@umich.edu 0x0: decode OP_HI { 18404661Sksewell@umich.edu 0x0: decode OP_LO { 18414661Sksewell@umich.edu format DspIntOp { 18424661Sksewell@umich.edu 0x0: adduh_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, 18434661Sksewell@umich.edu NOROUND, UNSIGNED ); }}); 18444661Sksewell@umich.edu 0x1: subuh_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, 18454661Sksewell@umich.edu NOROUND, UNSIGNED ); }}); 18464661Sksewell@umich.edu 0x2: adduh_r_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, 18474661Sksewell@umich.edu ROUND, UNSIGNED ); }}); 18484661Sksewell@umich.edu 0x3: subuh_r_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, 18494661Sksewell@umich.edu ROUND, UNSIGNED ); }}); 18504661Sksewell@umich.edu } 18514661Sksewell@umich.edu } 18524661Sksewell@umich.edu 0x1: decode OP_LO { 18534661Sksewell@umich.edu format DspIntOp { 18544661Sksewell@umich.edu 0x0: addqh_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, 18554661Sksewell@umich.edu NOROUND, SIGNED ); }}); 18564661Sksewell@umich.edu 0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, 18574661Sksewell@umich.edu NOROUND, SIGNED ); }}); 18584661Sksewell@umich.edu 0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, 18594661Sksewell@umich.edu ROUND, SIGNED ); }}); 18604661Sksewell@umich.edu 0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, 18614661Sksewell@umich.edu ROUND, SIGNED ); }}); 18624661Sksewell@umich.edu 0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, 18635222Sksewell@umich.edu NOSATURATE, &dspctl ); }}, IntMultOp); 18644661Sksewell@umich.edu 0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, 18655222Sksewell@umich.edu SATURATE, &dspctl ); }}, IntMultOp); 18665222Sksewell@umich.edu 18674661Sksewell@umich.edu } 18684661Sksewell@umich.edu } 18694661Sksewell@umich.edu 0x2: decode OP_LO { 18704661Sksewell@umich.edu format DspIntOp { 18714661Sksewell@umich.edu 0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, 18724661Sksewell@umich.edu NOROUND, SIGNED ); }}); 18734661Sksewell@umich.edu 0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, 18744661Sksewell@umich.edu NOROUND, SIGNED ); }}); 18754661Sksewell@umich.edu 0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, 18764661Sksewell@umich.edu ROUND, SIGNED ); }}); 18774661Sksewell@umich.edu 0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, 18784661Sksewell@umich.edu ROUND, SIGNED ); }}); 18794661Sksewell@umich.edu 0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, 18805222Sksewell@umich.edu SATURATE, NOROUND, &dspctl ); }}, IntMultOp); 18814661Sksewell@umich.edu 0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, 18825222Sksewell@umich.edu SATURATE, ROUND, &dspctl ); }}, IntMultOp); 18834661Sksewell@umich.edu } 18844661Sksewell@umich.edu } 18852061SN/A } 18862101SN/A } 18872061SN/A 18882101SN/A //Table A-10 MIPS32 BSHFL Encoding of sa Field 18892101SN/A 0x4: decode SA { 18902046SN/A format BasicOp { 18912686Sksewell@umich.edu 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 | 18924661Sksewell@umich.edu Rt.uw<31:24> << 16 | 18934661Sksewell@umich.edu Rt.uw<7:0> << 8 | 18944661Sksewell@umich.edu Rt.uw<15:8>; 18952686Sksewell@umich.edu }}); 18962742Sksewell@umich.edu 0x10: seb({{ Rd.sw = Rt.sb; }}); 18972742Sksewell@umich.edu 0x18: seh({{ Rd.sw = Rt.sh; }}); 18982046SN/A } 18992101SN/A } 19002043SN/A 19012101SN/A 0x6: decode FUNCTION_LO { 19024661Sksewell@umich.edu 19034661Sksewell@umich.edu //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL) 19044661Sksewell@umich.edu 0x0: decode OP_HI { 19054661Sksewell@umich.edu 0x0: decode OP_LO { 19064661Sksewell@umich.edu format DspHiLoOp { 19074661Sksewell@umich.edu 0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 19085222Sksewell@umich.edu SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp); 19094661Sksewell@umich.edu 0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 19105222Sksewell@umich.edu SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp); 19114661Sksewell@umich.edu 0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw, 19125222Sksewell@umich.edu ACDST, SIMD_FMT_PH ); }}, IntMultOp); 19134661Sksewell@umich.edu 0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 19145222Sksewell@umich.edu SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp); 19154661Sksewell@umich.edu 0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 19165222Sksewell@umich.edu SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp); 19174661Sksewell@umich.edu 0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 19185222Sksewell@umich.edu SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp); 19194661Sksewell@umich.edu 0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw, 19205222Sksewell@umich.edu ACDST, SIMD_FMT_PH, &dspctl ); }}, IntMultOp); 19214661Sksewell@umich.edu 0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 19225222Sksewell@umich.edu SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp); 19234661Sksewell@umich.edu } 19244661Sksewell@umich.edu } 19254661Sksewell@umich.edu 0x1: decode OP_LO { 19264661Sksewell@umich.edu format DspHiLoOp { 19274661Sksewell@umich.edu 0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, 19285222Sksewell@umich.edu SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp); 19294661Sksewell@umich.edu 0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 19305222Sksewell@umich.edu SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp); 19314661Sksewell@umich.edu 0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 19325222Sksewell@umich.edu SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp); 19334661Sksewell@umich.edu 0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, 19345222Sksewell@umich.edu SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp); 19354661Sksewell@umich.edu 0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, 19365222Sksewell@umich.edu SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp); 19374661Sksewell@umich.edu 0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, 19385222Sksewell@umich.edu SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp); 19394661Sksewell@umich.edu } 19404661Sksewell@umich.edu } 19414661Sksewell@umich.edu 0x2: decode OP_LO { 19424661Sksewell@umich.edu format DspHiLoOp { 19434661Sksewell@umich.edu 0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 19445222Sksewell@umich.edu MODE_L, SATURATE, &dspctl ); }}, IntMultOp); 19454661Sksewell@umich.edu 0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 19465222Sksewell@umich.edu MODE_R, SATURATE, &dspctl ); }}, IntMultOp); 19474661Sksewell@umich.edu 0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 19485222Sksewell@umich.edu MODE_L, NOSATURATE, &dspctl ); }}, IntMultOp); 19494661Sksewell@umich.edu 0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, 19505222Sksewell@umich.edu MODE_R, NOSATURATE, &dspctl ); }}, IntMultOp); 19514661Sksewell@umich.edu } 19524661Sksewell@umich.edu } 19534661Sksewell@umich.edu 0x3: decode OP_LO { 19544661Sksewell@umich.edu format DspHiLoOp { 19554661Sksewell@umich.edu 0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 19565222Sksewell@umich.edu SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp); 19574661Sksewell@umich.edu 0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 19585222Sksewell@umich.edu SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp); 19594661Sksewell@umich.edu 0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 19605222Sksewell@umich.edu SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp); 19614661Sksewell@umich.edu 0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, 19625222Sksewell@umich.edu SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp); 19634661Sksewell@umich.edu } 19644661Sksewell@umich.edu } 19654661Sksewell@umich.edu } 19664661Sksewell@umich.edu 19674661Sksewell@umich.edu //Table 3.3 MIPS32 APPEND Encoding of the op Field 19684661Sksewell@umich.edu 0x1: decode OP_HI { 19694661Sksewell@umich.edu 0x0: decode OP_LO { 19704661Sksewell@umich.edu format IntOp { 19714661Sksewell@umich.edu 0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }}); 19724661Sksewell@umich.edu 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }}); 19734661Sksewell@umich.edu } 19744661Sksewell@umich.edu } 19754661Sksewell@umich.edu 0x2: decode OP_LO { 19764661Sksewell@umich.edu format IntOp { 19774661Sksewell@umich.edu 0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }}); 19784661Sksewell@umich.edu } 19794661Sksewell@umich.edu } 19804661Sksewell@umich.edu } 19814661Sksewell@umich.edu 19822101SN/A } 19834661Sksewell@umich.edu 0x7: decode FUNCTION_LO { 19844661Sksewell@umich.edu 19854661Sksewell@umich.edu //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL) 19864661Sksewell@umich.edu 0x0: decode OP_HI { 19874661Sksewell@umich.edu 0x0: decode OP_LO { 19884661Sksewell@umich.edu format DspHiLoOp { 19894661Sksewell@umich.edu 0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 19904661Sksewell@umich.edu NOROUND, NOSATURATE, &dspctl ); }}); 19914661Sksewell@umich.edu 0x1: extrv_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 19924661Sksewell@umich.edu NOROUND, NOSATURATE, &dspctl ); }}); 19934661Sksewell@umich.edu 0x2: extp({{ Rt.uw = dspExtp( dspac, RS, &dspctl ); }}); 19944661Sksewell@umich.edu 0x3: extpv({{ Rt.uw = dspExtp( dspac, Rs.uw, &dspctl ); }}); 19954661Sksewell@umich.edu 0x4: extr_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 19964661Sksewell@umich.edu ROUND, NOSATURATE, &dspctl ); }}); 19974661Sksewell@umich.edu 0x5: extrv_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 19984661Sksewell@umich.edu ROUND, NOSATURATE, &dspctl ); }}); 19994661Sksewell@umich.edu 0x6: extr_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, 20004661Sksewell@umich.edu ROUND, SATURATE, &dspctl ); }}); 20014661Sksewell@umich.edu 0x7: extrv_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, 20024661Sksewell@umich.edu ROUND, SATURATE, &dspctl ); }}); 20034661Sksewell@umich.edu } 20044661Sksewell@umich.edu } 20054661Sksewell@umich.edu 0x1: decode OP_LO { 20064661Sksewell@umich.edu format DspHiLoOp { 20074661Sksewell@umich.edu 0x2: extpdp({{ Rt.uw = dspExtpd( dspac, RS, &dspctl ); }}); 20084661Sksewell@umich.edu 0x3: extpdpv({{ Rt.uw = dspExtpd( dspac, Rs.uw, &dspctl ); }}); 20094661Sksewell@umich.edu 0x6: extr_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, RS, 20104661Sksewell@umich.edu NOROUND, SATURATE, &dspctl ); }}); 20114661Sksewell@umich.edu 0x7: extrv_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, Rs.uw, 20124661Sksewell@umich.edu NOROUND, SATURATE, &dspctl ); }}); 20134661Sksewell@umich.edu } 20144661Sksewell@umich.edu } 20154661Sksewell@umich.edu 0x2: decode OP_LO { 20164661Sksewell@umich.edu format DspIntOp { 20174661Sksewell@umich.edu 0x2: rddsp({{ Rd.uw = readDSPControl( &dspctl, RDDSPMASK ); }}); 20184661Sksewell@umich.edu 0x3: wrdsp({{ writeDSPControl( &dspctl, Rs.uw, WRDSPMASK ); }}); 20194661Sksewell@umich.edu } 20204661Sksewell@umich.edu } 20214661Sksewell@umich.edu 0x3: decode OP_LO { 20224661Sksewell@umich.edu format DspHiLoOp { 20234661Sksewell@umich.edu 0x2: shilo({{ if( sext<6>(HILOSA) < 0 ) 20244661Sksewell@umich.edu dspac = (uint64_t)dspac << -sext<6>(HILOSA); 20254661Sksewell@umich.edu else 20264661Sksewell@umich.edu dspac = (uint64_t)dspac >> sext<6>(HILOSA); }}); 20274661Sksewell@umich.edu 0x3: shilov({{ if( sext<6>(Rs.sw<5:0>) < 0 ) 20284661Sksewell@umich.edu dspac = (uint64_t)dspac << -sext<6>(Rs.sw<5:0>); 20294661Sksewell@umich.edu else 20304661Sksewell@umich.edu dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }}); 20314661Sksewell@umich.edu 0x7: mthlip({{ dspac = dspac << 32; 20324661Sksewell@umich.edu dspac |= Rs.uw; 20334661Sksewell@umich.edu dspctl = insertBits( dspctl, 5, 0, 20344661Sksewell@umich.edu dspctl<5:0>+32 ); }}); 20354661Sksewell@umich.edu } 20364661Sksewell@umich.edu } 20374661Sksewell@umich.edu } 20385222Sksewell@umich.edu 0x3: decode OP_HI { 20395222Sksewell@umich.edu 0x2: decode OP_LO { 20405222Sksewell@umich.edu 0x3: FailUnimpl::rdhwr(); 20415222Sksewell@umich.edu } 20425222Sksewell@umich.edu } 20434661Sksewell@umich.edu } 20442043SN/A } 20452084SN/A } 20462024SN/A 20472686Sksewell@umich.edu 0x4: decode OPCODE_LO { 20482124SN/A format LoadMemory { 20495222Sksewell@umich.edu 0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT); 20505222Sksewell@umich.edu 0x1: lh({{ Rt.sw = Mem.sh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 20512479SN/A 0x3: lw({{ Rt.sw = Mem.sw; }}); 20525222Sksewell@umich.edu 0x4: lbu({{ Rt.uw = Mem.ub;}}, mem_flags = NO_ALIGN_FAULT); 20535222Sksewell@umich.edu 0x5: lhu({{ Rt.uw = Mem.uh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 20542686Sksewell@umich.edu } 20552495SN/A 20562686Sksewell@umich.edu format LoadUnalignedMemory { 20572686Sksewell@umich.edu 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset); 20582686Sksewell@umich.edu Rt.uw = mem_word << mem_shift | 20595222Sksewell@umich.edu Rt.uw & mask(mem_shift); 20602686Sksewell@umich.edu }}); 20612686Sksewell@umich.edu 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset; 20622686Sksewell@umich.edu Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) | 20635222Sksewell@umich.edu mem_word >> mem_shift; 20642686Sksewell@umich.edu }}); 20654661Sksewell@umich.edu } 20662084SN/A } 20672024SN/A 20682686Sksewell@umich.edu 0x5: decode OPCODE_LO { 20692124SN/A format StoreMemory { 20705222Sksewell@umich.edu 0x0: sb({{ Mem.ub = Rt<7:0>; }}, mem_flags = NO_ALIGN_FAULT); 20715222Sksewell@umich.edu 0x1: sh({{ Mem.uh = Rt<15:0>; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 20722479SN/A 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 20732084SN/A } 20742024SN/A 20752686Sksewell@umich.edu format StoreUnalignedMemory { 20762686Sksewell@umich.edu 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset); 20772686Sksewell@umich.edu uint32_t mem_shift = 32 - reg_shift; 20782686Sksewell@umich.edu mem_word = mem_word & (mask(reg_shift) << mem_shift) | 20792686Sksewell@umich.edu Rt.uw >> reg_shift; 20802686Sksewell@umich.edu }}); 20812686Sksewell@umich.edu 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset; 20822686Sksewell@umich.edu mem_word = Rt.uw << reg_shift | 20832686Sksewell@umich.edu mem_word & (mask(reg_shift)); 20842686Sksewell@umich.edu }}); 20852084SN/A } 20865222Sksewell@umich.edu format CP0Control { 20875222Sksewell@umich.edu 0x7: cache({{ 20885222Sksewell@umich.edu Addr CacheEA = Rs.uw + OFFSET; 20895250Sksewell@umich.edu //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 20905222Sksewell@umich.edu }}); 20915222Sksewell@umich.edu } 20922084SN/A } 20932024SN/A 20942686Sksewell@umich.edu 0x6: decode OPCODE_LO { 20952686Sksewell@umich.edu format LoadMemory { 20962686Sksewell@umich.edu 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED); 20972686Sksewell@umich.edu 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 20982573SN/A 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 20992084SN/A } 21005222Sksewell@umich.edu 0x2: CP2Unimpl::lwc2(); 21015222Sksewell@umich.edu 0x6: CP2Unimpl::ldc2(); 21022686Sksewell@umich.edu 0x3: Prefetch::pref(); 21032084SN/A } 21042024SN/A 21052239SN/A 21062686Sksewell@umich.edu 0x7: decode OPCODE_LO { 21072686Sksewell@umich.edu 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}}, 21082686Sksewell@umich.edu {{ uint64_t tmp = write_result; 21092686Sksewell@umich.edu Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; 21102935Sksewell@umich.edu }}, mem_flags=LOCKED, inst_flags = IsStoreConditional); 21112055SN/A 21122686Sksewell@umich.edu format StoreMemory { 21135222Sksewell@umich.edu 0x1: swc1({{ Mem.uw = Ft.uw;}}); 21145222Sksewell@umich.edu 0x5: sdc1({{ Mem.ud = Ft.ud;}}); 21152084SN/A } 21165222Sksewell@umich.edu 21175222Sksewell@umich.edu 0x2: CP2Unimpl::swc2(); 21185222Sksewell@umich.edu 0x6: CP2Unimpl::sdc2(); 21195222Sksewell@umich.edu 21202027SN/A } 21212024SN/A} 21222022SN/A 21232027SN/A 2124