decoder.isa revision 2608
11049Sbinkertn@umich.edu // -*- mode:c++ -*-
21049Sbinkertn@umich.edu
31049Sbinkertn@umich.edu////////////////////////////////////////////////////////////////////
41049Sbinkertn@umich.edu//
51049Sbinkertn@umich.edu// The actual MIPS32 ISA decoder
61049Sbinkertn@umich.edu// -----------------------------
71049Sbinkertn@umich.edu// The following instructions are specified in the MIPS32 ISA
81049Sbinkertn@umich.edu// Specification. Decoding closely follows the style specified
91049Sbinkertn@umich.edu// in the MIPS32 ISAthe specification document starting with Table
101049Sbinkertn@umich.edu// A-2 (document available @ www.mips.com)
111049Sbinkertn@umich.edu//
121049Sbinkertn@umich.edu//@todo: Distinguish "unknown/future" use insts from "reserved"
131049Sbinkertn@umich.edu// ones
141049Sbinkertn@umich.edudecode OPCODE_HI default Unknown::unknown() {
151049Sbinkertn@umich.edu
161049Sbinkertn@umich.edu    // Derived From ... Table A-2 MIPS32 ISA Manual
171049Sbinkertn@umich.edu    0x0: decode OPCODE_LO {
181049Sbinkertn@umich.edu
191049Sbinkertn@umich.edu        0x0: decode FUNCTION_HI {
201049Sbinkertn@umich.edu            0x0: decode FUNCTION_LO {
211049Sbinkertn@umich.edu                0x1: decode MOVCI {
221049Sbinkertn@umich.edu                    format BasicOp {
231049Sbinkertn@umich.edu                        0: movf({{ if (getFPConditionCode(CC) == 0) Rd = Rs}});
241049Sbinkertn@umich.edu                        1: movt({{ if (getFPConditionCode(CC) == 1) Rd = Rs}});
251049Sbinkertn@umich.edu                    }
261049Sbinkertn@umich.edu                }
271049Sbinkertn@umich.edu
281049Sbinkertn@umich.edu                format BasicOp {
291049Sbinkertn@umich.edu
301049Sbinkertn@umich.edu                    //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
311049Sbinkertn@umich.edu                    //are used to distinguish among the SLL, NOP, SSNOP and EHB functions.
321049Sbinkertn@umich.edu                    0x0: decode RS  {
331049Sbinkertn@umich.edu                        0x0: decode RT {     //fix Nop traditional vs. Nop converted disassembly later
341049Sbinkertn@umich.edu                             0x0: decode RD  default Nop::nop(){
351049Sbinkertn@umich.edu                                  0x0: decode SA {
361049Sbinkertn@umich.edu                                      0x1: ssnop({{ ; }}); //really sll r0,r0,1
371049Sbinkertn@umich.edu                                      0x3: ehb({{ ; }});   //really sll r0,r0,3
381049Sbinkertn@umich.edu                                  }
391049Sbinkertn@umich.edu                             }
401049Sbinkertn@umich.edu
411049Sbinkertn@umich.edu                             default: sll({{ Rd = Rt.uw << SA; }});
421269Sbinkertn@umich.edu                        }
431049Sbinkertn@umich.edu
441269Sbinkertn@umich.edu                    }
451269Sbinkertn@umich.edu
461269Sbinkertn@umich.edu                    0x2: decode RS_SRL {
471269Sbinkertn@umich.edu                        0x0:decode SRL {
481269Sbinkertn@umich.edu                            0: srl({{ Rd = Rt.uw >> SA; }});
491269Sbinkertn@umich.edu
501162Sbinkertn@umich.edu                            //Hardcoded assuming 32-bit ISA, probably need parameter here
511049Sbinkertn@umich.edu                            1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
521049Sbinkertn@umich.edu                        }
531269Sbinkertn@umich.edu                    }
541269Sbinkertn@umich.edu
551269Sbinkertn@umich.edu                    0x3: decode RS {
561269Sbinkertn@umich.edu                        0x0: sra({{
571269Sbinkertn@umich.edu                            uint32_t temp = Rt >> SA;
581269Sbinkertn@umich.edu
591269Sbinkertn@umich.edu                            if ( (Rt & 0x80000000) > 0 ) {
601269Sbinkertn@umich.edu                                uint32_t mask = 0x80000000;
611269Sbinkertn@umich.edu                                for(int i=0; i < SA; i++) {
621269Sbinkertn@umich.edu                                    temp |= mask;
631269Sbinkertn@umich.edu                                    mask = mask >> 1;
641269Sbinkertn@umich.edu                                }
651269Sbinkertn@umich.edu                            }
661269Sbinkertn@umich.edu
671269Sbinkertn@umich.edu                            Rd = temp;
681269Sbinkertn@umich.edu                        }});
691269Sbinkertn@umich.edu                    }
701269Sbinkertn@umich.edu
711269Sbinkertn@umich.edu                    0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
721269Sbinkertn@umich.edu
731269Sbinkertn@umich.edu                    0x6: decode SRLV {
741269Sbinkertn@umich.edu                        0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
751269Sbinkertn@umich.edu
761049Sbinkertn@umich.edu                        //Hardcoded assuming 32-bit ISA, probably need parameter here
771269Sbinkertn@umich.edu                        1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
781269Sbinkertn@umich.edu                    }
791269Sbinkertn@umich.edu
801049Sbinkertn@umich.edu                    0x7: srav({{
811049Sbinkertn@umich.edu                        int shift_amt = Rs<4:0>;
821269Sbinkertn@umich.edu
831049Sbinkertn@umich.edu                        uint32_t temp = Rt >> shift_amt;
841269Sbinkertn@umich.edu
851269Sbinkertn@umich.edu                        if ( (Rt & 0x80000000) > 0 ) {
861165Sbinkertn@umich.edu                                uint32_t mask = 0x80000000;
871049Sbinkertn@umich.edu                                for(int i=0; i < shift_amt; i++) {
881049Sbinkertn@umich.edu                                    temp |= mask;
891049Sbinkertn@umich.edu                                    mask = mask >> 1;
901049Sbinkertn@umich.edu                                }
911049Sbinkertn@umich.edu                            }
921049Sbinkertn@umich.edu
931049Sbinkertn@umich.edu                        Rd = temp;
941049Sbinkertn@umich.edu                    }});
951049Sbinkertn@umich.edu                }
961269Sbinkertn@umich.edu            }
971049Sbinkertn@umich.edu
981049Sbinkertn@umich.edu            0x1: decode FUNCTION_LO {
991049Sbinkertn@umich.edu
1001049Sbinkertn@umich.edu                //Table A-3 Note: "Specific encodings of the hint field are used
1011049Sbinkertn@umich.edu                //to distinguish JR from JR.HB and JALR from JALR.HB"
1021049Sbinkertn@umich.edu                format Jump {
1031049Sbinkertn@umich.edu                    0x0: decode HINT {
1041049Sbinkertn@umich.edu                        0:jr({{ NNPC = Rs & ~1; }},IsReturn);
1051049Sbinkertn@umich.edu
1061049Sbinkertn@umich.edu                        1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn);
1071049Sbinkertn@umich.edu                    }
1081049Sbinkertn@umich.edu
1091049Sbinkertn@umich.edu                    0x1: decode HINT {
1101049Sbinkertn@umich.edu                        0: jalr({{ Rd = NNPC; NNPC = Rs; }},IsCall,IsReturn);
1111049Sbinkertn@umich.edu
1121049Sbinkertn@umich.edu                        1: jalr_hb({{ Rd = NNPC; NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn);
1131049Sbinkertn@umich.edu                    }
1141049Sbinkertn@umich.edu                }
1151049Sbinkertn@umich.edu
1161049Sbinkertn@umich.edu                format BasicOp {
1171049Sbinkertn@umich.edu                    0x2: movz({{ if (Rt == 0) Rd = Rs; }});
1181049Sbinkertn@umich.edu                    0x3: movn({{ if (Rt != 0) Rd = Rs; }});
1191049Sbinkertn@umich.edu                }
1201049Sbinkertn@umich.edu
1211049Sbinkertn@umich.edu                format BasicOp {
1221049Sbinkertn@umich.edu                    0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative);
1231049Sbinkertn@umich.edu                    0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative);
1241049Sbinkertn@umich.edu                    0x7: sync({{  panic("Not implemented sync yet"); }},IsNonSpeculative);
1251049Sbinkertn@umich.edu                }
1261049Sbinkertn@umich.edu            }
1271049Sbinkertn@umich.edu
1281049Sbinkertn@umich.edu            0x2: decode FUNCTION_LO {
1291049Sbinkertn@umich.edu                format BasicOp {
1301049Sbinkertn@umich.edu                    0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }});
1311049Sbinkertn@umich.edu                    0x1: mthi({{ xc->setMiscReg(Hi,Rs); }});
1321049Sbinkertn@umich.edu                    0x2: mflo({{ Rd = xc->readMiscReg(Lo); }});
1331049Sbinkertn@umich.edu                    0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }});
1341049Sbinkertn@umich.edu                }
1351049Sbinkertn@umich.edu            }
1361049Sbinkertn@umich.edu
1371049Sbinkertn@umich.edu            0x3: decode FUNCTION_LO {
1381049Sbinkertn@umich.edu                format IntOp {
1391049Sbinkertn@umich.edu                    0x0: mult({{
1401049Sbinkertn@umich.edu                        int64_t temp1 = Rs.sd * Rt.sd;
1411049Sbinkertn@umich.edu                        xc->setMiscReg(Hi,temp1<63:32>);
1421049Sbinkertn@umich.edu                        xc->setMiscReg(Lo,temp1<31:0>);
1431049Sbinkertn@umich.edu                    }});
1441049Sbinkertn@umich.edu
1451049Sbinkertn@umich.edu                    0x1: multu({{
1461049Sbinkertn@umich.edu                        uint64_t temp1 = Rs.ud * Rt.ud;
1471049Sbinkertn@umich.edu                        xc->setMiscReg(Hi,temp1<63:32>);
1481049Sbinkertn@umich.edu                        xc->setMiscReg(Lo,temp1<31:0>);
1491049Sbinkertn@umich.edu                    }});
1501049Sbinkertn@umich.edu
1511049Sbinkertn@umich.edu                    0x2: div({{
1521049Sbinkertn@umich.edu                        xc->setMiscReg(Hi,Rs.sd % Rt.sd);
1531049Sbinkertn@umich.edu                        xc->setMiscReg(Lo,Rs.sd / Rt.sd);
1541049Sbinkertn@umich.edu                    }});
1551049Sbinkertn@umich.edu
1561049Sbinkertn@umich.edu                    0x3: divu({{
1571049Sbinkertn@umich.edu                        xc->setMiscReg(Hi,Rs.ud % Rt.ud);
1581049Sbinkertn@umich.edu                        xc->setMiscReg(Lo,Rs.ud / Rt.ud);
1591049Sbinkertn@umich.edu                    }});
1601049Sbinkertn@umich.edu                }
1611049Sbinkertn@umich.edu            }
1621049Sbinkertn@umich.edu
1631049Sbinkertn@umich.edu            0x4: decode HINT {
1641049Sbinkertn@umich.edu                0x0: decode FUNCTION_LO {
1651049Sbinkertn@umich.edu                    format IntOp {
1661049Sbinkertn@umich.edu                        0x0: add({{  Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}});
1671049Sbinkertn@umich.edu                        0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
1681049Sbinkertn@umich.edu                        0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
1691049Sbinkertn@umich.edu                        0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
1701049Sbinkertn@umich.edu                        0x4: and({{ Rd = Rs & Rt;}});
1711049Sbinkertn@umich.edu                        0x5: or({{ Rd = Rs | Rt;}});
1721049Sbinkertn@umich.edu                        0x6: xor({{ Rd = Rs ^ Rt;}});
1731049Sbinkertn@umich.edu                        0x7: nor({{ Rd = ~(Rs | Rt);}});
1741049Sbinkertn@umich.edu                    }
1751049Sbinkertn@umich.edu                }
1761049Sbinkertn@umich.edu            }
1771049Sbinkertn@umich.edu
1781049Sbinkertn@umich.edu            0x5: decode HINT {
1791049Sbinkertn@umich.edu                0x0: decode FUNCTION_LO {
1801049Sbinkertn@umich.edu                    format IntOp{
1811049Sbinkertn@umich.edu                        0x2: slt({{  Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
1821049Sbinkertn@umich.edu                        0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
1831049Sbinkertn@umich.edu                    }
1841049Sbinkertn@umich.edu                }
1851049Sbinkertn@umich.edu            }
1861049Sbinkertn@umich.edu
1871049Sbinkertn@umich.edu            0x6: decode FUNCTION_LO {
1881049Sbinkertn@umich.edu                format Trap {
1891049Sbinkertn@umich.edu                    0x0: tge({{  cond = (Rs.sw >= Rt.sw); }});
1901049Sbinkertn@umich.edu                    0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
1911049Sbinkertn@umich.edu                    0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
1921049Sbinkertn@umich.edu                    0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
1931049Sbinkertn@umich.edu                    0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
1941049Sbinkertn@umich.edu                    0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
1951049Sbinkertn@umich.edu                }
1961049Sbinkertn@umich.edu            }
1971049Sbinkertn@umich.edu        }
1981049Sbinkertn@umich.edu
1991049Sbinkertn@umich.edu        0x1: decode REGIMM_HI {
2001049Sbinkertn@umich.edu            0x0: decode REGIMM_LO {
2011049Sbinkertn@umich.edu                format Branch {
2021076Sbinkertn@umich.edu                    0x0: bltz({{ cond = (Rs.sw < 0); }});
2031269Sbinkertn@umich.edu                    0x1: bgez({{ cond = (Rs.sw >= 0); }});
2041049Sbinkertn@umich.edu                }
2051301Ssaidi@eecs.umich.edu
2061301Ssaidi@eecs.umich.edu                format BranchLikely {
2071301Ssaidi@eecs.umich.edu                    0x2: bltzl({{ cond = (Rs.sw < 0); }});
2081301Ssaidi@eecs.umich.edu                    0x3: bgezl({{ cond = (Rs.sw >= 0); }});
2091165Sbinkertn@umich.edu                }
2101165Sbinkertn@umich.edu            }
2111165Sbinkertn@umich.edu
2121165Sbinkertn@umich.edu            0x1: decode REGIMM_LO {
2131165Sbinkertn@umich.edu                format Trap {
2141165Sbinkertn@umich.edu                    0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
2151165Sbinkertn@umich.edu                    0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
2161165Sbinkertn@umich.edu                    0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
2171165Sbinkertn@umich.edu                    0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
2181165Sbinkertn@umich.edu                    0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
2191165Sbinkertn@umich.edu                    0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
2201165Sbinkertn@umich.edu                }
2211165Sbinkertn@umich.edu            }
2221165Sbinkertn@umich.edu
2231301Ssaidi@eecs.umich.edu            0x2: decode REGIMM_LO {
2241165Sbinkertn@umich.edu                format Branch {
2251165Sbinkertn@umich.edu                    0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn);
2261165Sbinkertn@umich.edu                    0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn);
2271165Sbinkertn@umich.edu                }
2281165Sbinkertn@umich.edu
2291049Sbinkertn@umich.edu                format BranchLikely {
2301049Sbinkertn@umich.edu                    0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn);
2311049Sbinkertn@umich.edu                    0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn);
2321049Sbinkertn@umich.edu                }
2331269Sbinkertn@umich.edu            }
2341269Sbinkertn@umich.edu
2351269Sbinkertn@umich.edu            0x3: decode REGIMM_LO {
2361269Sbinkertn@umich.edu                format WarnUnimpl {
2371269Sbinkertn@umich.edu                    0x7: synci();
2381269Sbinkertn@umich.edu                }
2391269Sbinkertn@umich.edu            }
2401269Sbinkertn@umich.edu        }
2411269Sbinkertn@umich.edu
2421269Sbinkertn@umich.edu        format Jump {
2431269Sbinkertn@umich.edu            0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
2441269Sbinkertn@umich.edu
2451269Sbinkertn@umich.edu            0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn);
2461269Sbinkertn@umich.edu        }
2471269Sbinkertn@umich.edu
2481269Sbinkertn@umich.edu        format Branch {
2491269Sbinkertn@umich.edu            0x4: beq({{ cond = (Rs.sw == Rt.sw); }});
2501269Sbinkertn@umich.edu            0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
2511269Sbinkertn@umich.edu            0x6: decode RT {
2521269Sbinkertn@umich.edu                0x0: blez({{ cond = (Rs.sw <= 0); }});
2531269Sbinkertn@umich.edu            }
2541269Sbinkertn@umich.edu
2551269Sbinkertn@umich.edu            0x7: decode RT {
2561301Ssaidi@eecs.umich.edu                0x0: bgtz({{ cond = (Rs.sw > 0); }});
2571269Sbinkertn@umich.edu            }
2581269Sbinkertn@umich.edu        }
2591269Sbinkertn@umich.edu    }
2601269Sbinkertn@umich.edu
2611269Sbinkertn@umich.edu    0x1: decode OPCODE_LO {
2621269Sbinkertn@umich.edu        format IntOp {
2631269Sbinkertn@umich.edu            0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
2641269Sbinkertn@umich.edu            0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
2651269Sbinkertn@umich.edu            0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
2661049Sbinkertn@umich.edu            0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }});
2671049Sbinkertn@umich.edu            0x4: andi({{ Rt.sw = Rs.sw & zextImm;}});
2681049Sbinkertn@umich.edu            0x5: ori({{ Rt.sw = Rs.sw | zextImm;}});
2691049Sbinkertn@umich.edu            0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}});
2701049Sbinkertn@umich.edu
2711049Sbinkertn@umich.edu            0x7: decode RS {
2721049Sbinkertn@umich.edu                0x0: lui({{ Rt = imm << 16}});
2731049Sbinkertn@umich.edu            }
2741049Sbinkertn@umich.edu        }
2751049Sbinkertn@umich.edu    }
2761049Sbinkertn@umich.edu
2771049Sbinkertn@umich.edu    0x2: decode OPCODE_LO {
2781049Sbinkertn@umich.edu
2791049Sbinkertn@umich.edu        //Table A-11 MIPS32 COP0 Encoding of rs Field
2801049Sbinkertn@umich.edu        0x0: decode RS_MSB {
2811049Sbinkertn@umich.edu            0x0: decode RS {
2821049Sbinkertn@umich.edu                format System {
2831049Sbinkertn@umich.edu                    0x0: mfc0({{
2841049Sbinkertn@umich.edu                        //uint64_t reg_num = Rd.uw;
2851049Sbinkertn@umich.edu
2861049Sbinkertn@umich.edu                        Rt = xc->readMiscReg(RD << 5 | SEL);
2871049Sbinkertn@umich.edu                    }});
2881049Sbinkertn@umich.edu
2891049Sbinkertn@umich.edu                    0x4: mtc0({{
2901049Sbinkertn@umich.edu                        //uint64_t reg_num = Rd.uw;
2911049Sbinkertn@umich.edu
2921049Sbinkertn@umich.edu                        xc->setMiscReg(RD << 5 | SEL,Rt);
2931049Sbinkertn@umich.edu                    }});
2941049Sbinkertn@umich.edu
2951049Sbinkertn@umich.edu                    0x8: mftr({{
2961209Sbinkertn@umich.edu                        //The contents of the coprocessor 0 register specified by the
2971209Sbinkertn@umich.edu                        //combination of rd and sel are loaded into general register
2981049Sbinkertn@umich.edu                        //rt. Note that not all coprocessor 0 registers support the
2991049Sbinkertn@umich.edu                        //sel field. In those instances, the sel field must be zero.
3001049Sbinkertn@umich.edu
3011049Sbinkertn@umich.edu                        //MT Code Needed Here
3021049Sbinkertn@umich.edu                    }});
3031049Sbinkertn@umich.edu
3041049Sbinkertn@umich.edu                    0xC: mttr({{
3051049Sbinkertn@umich.edu                        //The contents of the coprocessor 0 register specified by the
3061076Sbinkertn@umich.edu                        //combination of rd and sel are loaded into general register
3071269Sbinkertn@umich.edu                        //rt. Note that not all coprocessor 0 registers support the
3081049Sbinkertn@umich.edu                        //sel field. In those instances, the sel field must be zero.
3091049Sbinkertn@umich.edu
3101049Sbinkertn@umich.edu                        //MT Code Needed Here
3111049Sbinkertn@umich.edu                    }});
3121049Sbinkertn@umich.edu
3131049Sbinkertn@umich.edu
3141076Sbinkertn@umich.edu                    0xA: rdpgpr({{
3151049Sbinkertn@umich.edu                        //Accessing Previous Shadow Set Register Number
3161049Sbinkertn@umich.edu                        //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/;
3171049Sbinkertn@umich.edu                        //uint64_t reg_num = Rt.uw;
3181049Sbinkertn@umich.edu
3191049Sbinkertn@umich.edu                        //Rd = xc->regs.IntRegFile[prev];
3201049Sbinkertn@umich.edu                       //Rd = xc->shadowIntRegFile[prev][reg_num];
3211049Sbinkertn@umich.edu                    }});
3221049Sbinkertn@umich.edu
3231049Sbinkertn@umich.edu                    0xB: decode RD {
3241049Sbinkertn@umich.edu
3251049Sbinkertn@umich.edu                        0x0: decode SC {
3261049Sbinkertn@umich.edu                            0x0: dvpe({{
3271049Sbinkertn@umich.edu                                Rt.sw = xc->readMiscReg(MVPControl);
3281049Sbinkertn@umich.edu                                xc->setMiscReg(MVPControl,0);
3291049Sbinkertn@umich.edu                            }});
3301049Sbinkertn@umich.edu
3311049Sbinkertn@umich.edu                            0x1: evpe({{
3321049Sbinkertn@umich.edu                                Rt.sw = xc->readMiscReg(MVPControl);
3331049Sbinkertn@umich.edu                                xc->setMiscReg(MVPControl,1);
3341162Sbinkertn@umich.edu                            }});
3351076Sbinkertn@umich.edu                        }
3361269Sbinkertn@umich.edu
3371049Sbinkertn@umich.edu                        0x1: decode SC {
3381049Sbinkertn@umich.edu                            0x0: dmt({{
3391049Sbinkertn@umich.edu                                Rt.sw = xc->readMiscReg(VPEControl);
3401049Sbinkertn@umich.edu                                xc->setMiscReg(VPEControl,0);
3411049Sbinkertn@umich.edu                            }});
3421162Sbinkertn@umich.edu
3431049Sbinkertn@umich.edu                            0x1: emt({{
3441049Sbinkertn@umich.edu                                Rt.sw = xc->readMiscReg(VPEControl);
3451049Sbinkertn@umich.edu                                xc->setMiscReg(VPEControl,1);
3461049Sbinkertn@umich.edu                            }});
3471162Sbinkertn@umich.edu                        }
3481076Sbinkertn@umich.edu
3491269Sbinkertn@umich.edu                        0xC: decode SC {
3501049Sbinkertn@umich.edu                            0x0: di({{
3511049Sbinkertn@umich.edu                                Rt.sw = xc->readMiscReg(Status);
3521049Sbinkertn@umich.edu                                xc->setMiscReg(Status,0);
3531049Sbinkertn@umich.edu                            }});
3541049Sbinkertn@umich.edu
3551162Sbinkertn@umich.edu                            0x1: ei({{
3561049Sbinkertn@umich.edu                                Rt.sw = xc->readMiscReg(Status);
3571076Sbinkertn@umich.edu                                xc->setMiscReg(Status,1);
3581269Sbinkertn@umich.edu                            }});
3591049Sbinkertn@umich.edu                        }
3601049Sbinkertn@umich.edu                    }
3611049Sbinkertn@umich.edu
3621049Sbinkertn@umich.edu                    0xE: wrpgpr({{
3631049Sbinkertn@umich.edu                        //Accessing Previous Shadow Set Register Number
3641162Sbinkertn@umich.edu                        //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/);
3651049Sbinkertn@umich.edu                        //uint64_t reg_num = Rd.uw;
3661049Sbinkertn@umich.edu
3671049Sbinkertn@umich.edu                        //xc->regs.IntRegFile[prev];
3681049Sbinkertn@umich.edu                        //xc->shadowIntRegFile[prev][reg_num] = Rt;
3691049Sbinkertn@umich.edu                    }});
3701049Sbinkertn@umich.edu                }
3711049Sbinkertn@umich.edu            }
3721049Sbinkertn@umich.edu
3731049Sbinkertn@umich.edu            //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
3741049Sbinkertn@umich.edu            0x1: decode FUNCTION {
3751049Sbinkertn@umich.edu                format System {
3761049Sbinkertn@umich.edu                    0x01: tlbr({{ }});
3771049Sbinkertn@umich.edu                    0x02: tlbwi({{ }});
3781049Sbinkertn@umich.edu                    0x06: tlbwr({{ }});
3791049Sbinkertn@umich.edu                    0x08: tlbp({{ }});
3801049Sbinkertn@umich.edu                }
3811162Sbinkertn@umich.edu
3821049Sbinkertn@umich.edu                format WarnUnimpl {
3831076Sbinkertn@umich.edu                    0x18: eret();
3841049Sbinkertn@umich.edu                    0x1F: deret();
3851049Sbinkertn@umich.edu                    0x20: wait();
3861049Sbinkertn@umich.edu                }
3871049Sbinkertn@umich.edu            }
3881049Sbinkertn@umich.edu        }
3891049Sbinkertn@umich.edu
3901049Sbinkertn@umich.edu        //Table A-13 MIPS32 COP1 Encoding of rs Field
3911049Sbinkertn@umich.edu        0x1: decode RS_MSB {
3921049Sbinkertn@umich.edu
3931049Sbinkertn@umich.edu            0x0: decode RS_HI {
3941049Sbinkertn@umich.edu                0x0: decode RS_LO {
3951049Sbinkertn@umich.edu                    format FloatOp {
3961049Sbinkertn@umich.edu                        0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }});
3971049Sbinkertn@umich.edu                        0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
3981049Sbinkertn@umich.edu                        0x4: mtc1 ({{ Fs.uw = Rt.uw;       }});
3991049Sbinkertn@umich.edu                        0x7: mthc1({{
4001049Sbinkertn@umich.edu                             uint64_t fs_hi = Rt.ud << 32;
4011049Sbinkertn@umich.edu                             uint64_t fs_lo = Fs.ud & 0x0000FFFF;
4021049Sbinkertn@umich.edu                             Fs.ud = fs_hi & fs_lo;
4031162Sbinkertn@umich.edu                        }});
4041076Sbinkertn@umich.edu                    }
4051269Sbinkertn@umich.edu
4061049Sbinkertn@umich.edu                    format System {
4071049Sbinkertn@umich.edu                        0x2: cfc1({{
4081049Sbinkertn@umich.edu                            uint32_t fcsr_reg = xc->readMiscReg(FCSR);
4091049Sbinkertn@umich.edu
4101049Sbinkertn@umich.edu                            switch (FS)
4111162Sbinkertn@umich.edu                            {
4121076Sbinkertn@umich.edu                              case 0:
4131269Sbinkertn@umich.edu                                Rt = xc->readMiscReg(FIR);
4141049Sbinkertn@umich.edu                                break;
4151049Sbinkertn@umich.edu                              case 25:
4161049Sbinkertn@umich.edu                                Rt = 0 | (fcsr_reg & 0xFE000000) >> 24 | (fcsr_reg & 0x00800000) >> 23;
4171049Sbinkertn@umich.edu                                break;
4181049Sbinkertn@umich.edu                              case 26:
4191162Sbinkertn@umich.edu                                Rt = 0 | (fcsr_reg & 0x0003F07C);
4201162Sbinkertn@umich.edu                                break;
4211049Sbinkertn@umich.edu                              case 28:
4221076Sbinkertn@umich.edu                                Rt = 0 | (fcsr_reg);
4231269Sbinkertn@umich.edu                                break;
4241049Sbinkertn@umich.edu                              case 31:
4251049Sbinkertn@umich.edu                                Rt = fcsr_reg;
4261049Sbinkertn@umich.edu                                break;
4271049Sbinkertn@umich.edu                              default:
4281049Sbinkertn@umich.edu                                panic("FP Control Value (%d) Not Available. Ignoring Access to"
4291162Sbinkertn@umich.edu                                      "Floating Control Status Register",fcsr_reg);
4301076Sbinkertn@umich.edu                            }
4311049Sbinkertn@umich.edu                        }});
4321049Sbinkertn@umich.edu
4331049Sbinkertn@umich.edu                        0x6: ctc1({{
4341049Sbinkertn@umich.edu                            uint32_t fcsr_reg = xc->readMiscReg(FCSR);
4351049Sbinkertn@umich.edu                            uint32_t temp;
4361049Sbinkertn@umich.edu
4371049Sbinkertn@umich.edu                            switch (FS)
4381049Sbinkertn@umich.edu                            {
4391049Sbinkertn@umich.edu                              case 25:
4401049Sbinkertn@umich.edu                                temp = 0 | (Rt.uw<7:1> << 25) // move 31...25
4411049Sbinkertn@umich.edu                                    | (fcsr_reg & 0x01000000) // bit 24
4421049Sbinkertn@umich.edu                                    | (fcsr_reg & 0x004FFFFF);// bit 22...0
4431049Sbinkertn@umich.edu                                break;
4441049Sbinkertn@umich.edu
4451049Sbinkertn@umich.edu                              case 26:
4461076Sbinkertn@umich.edu                                temp = 0 | (fcsr_reg & 0xFFFC0000) // move 31...18
4471269Sbinkertn@umich.edu                                    | Rt.uw<17:12> << 12           // bit 17...12
4481049Sbinkertn@umich.edu                                    | (fcsr_reg & 0x00000F80) << 7// bit 11...7
4491049Sbinkertn@umich.edu                                    | Rt.uw<6:2> << 2              // bit 6...2
4501049Sbinkertn@umich.edu                                    | (fcsr_reg & 0x00000002);     // bit 1...0
4511049Sbinkertn@umich.edu                                break;
4521049Sbinkertn@umich.edu
4531162Sbinkertn@umich.edu                              case 28:
4541162Sbinkertn@umich.edu                                temp = 0 | (fcsr_reg & 0xFE000000) // move 31...25
4551162Sbinkertn@umich.edu                                    | Rt.uw<2:2> << 24       // bit 24
4561049Sbinkertn@umich.edu                                    | (fcsr_reg & 0x00FFF000) << 23// bit 23...12
4571076Sbinkertn@umich.edu                                    | Rt.uw<11:7> << 7       // bit 24
4581049Sbinkertn@umich.edu                                    | (fcsr_reg & 0x000007E)
4591049Sbinkertn@umich.edu                                    | Rt.uw<1:0>;// bit 22...0
4601049Sbinkertn@umich.edu                                break;
4611049Sbinkertn@umich.edu
4621049Sbinkertn@umich.edu                              case 31:
4631049Sbinkertn@umich.edu                                temp  = Rt.uw;
4641049Sbinkertn@umich.edu                                break;
4651049Sbinkertn@umich.edu
4661049Sbinkertn@umich.edu                              default:
4671049Sbinkertn@umich.edu                                panic("FP Control Value (%d) Not Available. Ignoring Access to"
4681049Sbinkertn@umich.edu                                      "Floating Control Status Register",fcsr_reg);
4691049Sbinkertn@umich.edu                            }
4701049Sbinkertn@umich.edu
4711049Sbinkertn@umich.edu                            xc->setMiscReg(FCSR,temp);
4721049Sbinkertn@umich.edu                        }});
4731049Sbinkertn@umich.edu                    }
4741049Sbinkertn@umich.edu                }
4751049Sbinkertn@umich.edu
4761049Sbinkertn@umich.edu                0x1: decode ND {
4771076Sbinkertn@umich.edu                    0x0: decode TF {
4781269Sbinkertn@umich.edu                        format Branch {
4791049Sbinkertn@umich.edu                            0x0: bc1f({{ cond = (getFPConditionCode(CC) == 0); }});
4801049Sbinkertn@umich.edu                            0x1: bc1t({{ cond = (getFPConditionCode(CC) == 1); }});
4811049Sbinkertn@umich.edu                        }
4821049Sbinkertn@umich.edu                    }
4831269Sbinkertn@umich.edu
4841269Sbinkertn@umich.edu                    0x1: decode TF {
4851269Sbinkertn@umich.edu                        format BranchLikely {
4861269Sbinkertn@umich.edu                            0x0: bc1fl({{ cond = (getFPConditionCode(CC) == 0); }});
4871269Sbinkertn@umich.edu                            0x1: bc1tl({{ cond = (getFPConditionCode(CC) == 1); }});
4881269Sbinkertn@umich.edu                        }
4891269Sbinkertn@umich.edu                    }
4901269Sbinkertn@umich.edu                }
4911269Sbinkertn@umich.edu            }
4921269Sbinkertn@umich.edu
4931269Sbinkertn@umich.edu            0x1: decode RS_HI {
4941269Sbinkertn@umich.edu                0x2: decode RS_LO {
4951269Sbinkertn@umich.edu
4961269Sbinkertn@umich.edu                    //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
4971269Sbinkertn@umich.edu                    //(( single-word ))
4981269Sbinkertn@umich.edu                    0x0: decode FUNCTION_HI {
4991269Sbinkertn@umich.edu                        0x0: decode FUNCTION_LO {
5001269Sbinkertn@umich.edu                            format FloatOp {
5011269Sbinkertn@umich.edu                                0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}});
5021269Sbinkertn@umich.edu                                0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}});
5031269Sbinkertn@umich.edu                                0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}});
5041269Sbinkertn@umich.edu                                0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}});
5051269Sbinkertn@umich.edu                                0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}});
5061269Sbinkertn@umich.edu                                0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}});
5071269Sbinkertn@umich.edu                                0x6: mov_s({{ Fd.sf = Fs.sf;}});
5081269Sbinkertn@umich.edu                                0x7: neg_s({{ Fd.sf = -1 * Fs.sf;}});
5091269Sbinkertn@umich.edu                            }
5101269Sbinkertn@umich.edu                        }
5111269Sbinkertn@umich.edu
5121269Sbinkertn@umich.edu                        0x1: decode FUNCTION_LO {
5131269Sbinkertn@umich.edu                            format Float64Op {
5141049Sbinkertn@umich.edu                                0x0: round_l_s({{
5151049Sbinkertn@umich.edu                                    Fd.ud = fpConvert(roundFP(Fs.sf), SINGLE_TO_LONG);
5161049Sbinkertn@umich.edu                                }});
5171049Sbinkertn@umich.edu
5181049Sbinkertn@umich.edu                                0x1: trunc_l_s({{
5191049Sbinkertn@umich.edu                                    Fd.ud = fpConvert(truncFP(Fs.sf), SINGLE_TO_LONG);
5201049Sbinkertn@umich.edu                                }});
5211049Sbinkertn@umich.edu
5221049Sbinkertn@umich.edu                                0x2: ceil_l_s({{
5231049Sbinkertn@umich.edu                                    Fd.ud = fpConvert(ceil(Fs.sf),  SINGLE_TO_LONG);
5241049Sbinkertn@umich.edu                                }});
5251049Sbinkertn@umich.edu
5261162Sbinkertn@umich.edu                                0x3: floor_l_s({{
5271162Sbinkertn@umich.edu                                    Fd.ud = fpConvert(floor(Fs.sf), SINGLE_TO_LONG);
5281162Sbinkertn@umich.edu                                }});
5291162Sbinkertn@umich.edu                            }
5301269Sbinkertn@umich.edu
5311162Sbinkertn@umich.edu                            format FloatOp {
5321162Sbinkertn@umich.edu                                0x4: round_w_s({{
5331162Sbinkertn@umich.edu                                    Fd.uw = fpConvert(roundFP(Fs.sf), SINGLE_TO_WORD);
5341162Sbinkertn@umich.edu                                }});
5351049Sbinkertn@umich.edu
5361162Sbinkertn@umich.edu                                0x5: trunc_w_s({{
5371162Sbinkertn@umich.edu                                    Fd.uw = fpConvert(truncFP(Fs.sf), SINGLE_TO_WORD);
5381269Sbinkertn@umich.edu                                }});
5391162Sbinkertn@umich.edu
5401162Sbinkertn@umich.edu                                0x6: ceil_w_s({{
5411049Sbinkertn@umich.edu                                    Fd.uw = fpConvert(ceil(Fs.sf),  SINGLE_TO_WORD);
5421049Sbinkertn@umich.edu                                }});
5431049Sbinkertn@umich.edu
5441162Sbinkertn@umich.edu                                0x7: floor_w_s({{
5451162Sbinkertn@umich.edu                                    Fd.uw = fpConvert(floor(Fs.sf), SINGLE_TO_WORD);
5461269Sbinkertn@umich.edu                                }});
5471162Sbinkertn@umich.edu                            }
5481162Sbinkertn@umich.edu                        }
5491162Sbinkertn@umich.edu
5501162Sbinkertn@umich.edu                        0x2: decode FUNCTION_LO {
5511162Sbinkertn@umich.edu                            0x1: decode MOVCF {
5521162Sbinkertn@umich.edu                                format FloatOp {
5531162Sbinkertn@umich.edu                                    0x0: movf_s({{if (getFPConditionCode(CC) == 0) Fd = Fs;}});
5541269Sbinkertn@umich.edu                                    0x1: movt_s({{if (getFPConditionCode(CC) == 1) Fd = Fs;}});
5551162Sbinkertn@umich.edu                                }
5561162Sbinkertn@umich.edu                            }
5571162Sbinkertn@umich.edu
5581162Sbinkertn@umich.edu                            format FloatOp {
5591162Sbinkertn@umich.edu                                0x2: movz_s({{ if (Rt == 0) Fd = Fs; }});
5601162Sbinkertn@umich.edu                                0x3: movn_s({{ if (Rt != 0) Fd = Fs; }});
5611162Sbinkertn@umich.edu                                0x5: recip_s({{ Fd = 1 / Fs; }});
5621269Sbinkertn@umich.edu                                0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
5631162Sbinkertn@umich.edu                            }
5641162Sbinkertn@umich.edu                        }
5651049Sbinkertn@umich.edu
5661049Sbinkertn@umich.edu                        0x4: decode FUNCTION_LO {
5671049Sbinkertn@umich.edu
5681049Sbinkertn@umich.edu                            format FloatConvertOp {
5691049Sbinkertn@umich.edu                                0x1: cvt_d_s({{
5701049Sbinkertn@umich.edu                                    Fd.ud = fpConvert(Fs.sf, SINGLE_TO_DOUBLE);
5711049Sbinkertn@umich.edu                                }});
5721049Sbinkertn@umich.edu
5731049Sbinkertn@umich.edu                                0x4: cvt_w_s({{
5741049Sbinkertn@umich.edu                                    Fd.uw = fpConvert(Fs.sf, SINGLE_TO_WORD);
5751049Sbinkertn@umich.edu                                }});
5761049Sbinkertn@umich.edu                            }
5771049Sbinkertn@umich.edu
5781049Sbinkertn@umich.edu                            format FloatConvertOp {
5791049Sbinkertn@umich.edu                                0x5: cvt_l_s({{
5801049Sbinkertn@umich.edu                                    Fd.ud = fpConvert(Fs.sf, SINGLE_TO_LONG);
5811049Sbinkertn@umich.edu                                }});
5821049Sbinkertn@umich.edu
5831076Sbinkertn@umich.edu                                0x6: cvt_ps_st({{
5841076Sbinkertn@umich.edu                                    Fd.ud = (uint64_t)Fs.uw << 32 | (uint64_t)Ft.uw;
5851301Ssaidi@eecs.umich.edu                                }});
5861049Sbinkertn@umich.edu                            }
5871301Ssaidi@eecs.umich.edu                        }
5881049Sbinkertn@umich.edu
5891049Sbinkertn@umich.edu                        0x6: decode FUNCTION_LO {
5901049Sbinkertn@umich.edu                            format FloatCompareOp {
5911049Sbinkertn@umich.edu                                0x0: c_f_s({{ cond = 0; }});
5921049Sbinkertn@umich.edu
5931049Sbinkertn@umich.edu                                0x1: c_un_s({{
5941049Sbinkertn@umich.edu                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
5951049Sbinkertn@umich.edu                                        cond = 1;
5961049Sbinkertn@umich.edu                                    else
5971049Sbinkertn@umich.edu                                        cond = 0;
5981049Sbinkertn@umich.edu                                }});
5991049Sbinkertn@umich.edu
6001049Sbinkertn@umich.edu                                0x2: c_eq_s({{
6011049Sbinkertn@umich.edu                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
6021049Sbinkertn@umich.edu                                        cond = 0;
6031049Sbinkertn@umich.edu                                    else
6041049Sbinkertn@umich.edu                                        cond = (Fs.sf == Ft.sf);
6051049Sbinkertn@umich.edu                                }});
6061049Sbinkertn@umich.edu
6071049Sbinkertn@umich.edu                                0x3: c_ueq_s({{
6081049Sbinkertn@umich.edu                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
6091049Sbinkertn@umich.edu                                        cond = 1;
6101049Sbinkertn@umich.edu                                    else
6111301Ssaidi@eecs.umich.edu                                        cond = (Fs.sf == Ft.sf);
6121301Ssaidi@eecs.umich.edu                                }});
6131049Sbinkertn@umich.edu
6141049Sbinkertn@umich.edu                                0x4: c_olt_s({{
6151049Sbinkertn@umich.edu                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
6161049Sbinkertn@umich.edu                                        cond = 0;
6171049Sbinkertn@umich.edu                                    else
6181049Sbinkertn@umich.edu                                        cond = (Fs.sf < Ft.sf);
6191049Sbinkertn@umich.edu                                }});
6201049Sbinkertn@umich.edu
6211049Sbinkertn@umich.edu                                0x5: c_ult_s({{
6221049Sbinkertn@umich.edu                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
6231049Sbinkertn@umich.edu                                        cond = 1;
624                                    else
625                                        cond = (Fs.sf < Ft.sf);
626                                }});
627
628                                0x6: c_ole_s({{
629                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
630                                        cond = 0;
631                                    else
632                                        cond = (Fs.sf <= Ft.sf);
633                                }});
634
635                                0x7: c_ule_s({{
636                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
637                                        cond = 1;
638                                    else
639                                        cond = (Fs.sf <= Ft.sf);
640                                }});
641                            }
642                        }
643
644                        0x7: decode FUNCTION_LO {
645                            format FloatCompareWithXcptOp {
646                                0x0: c_sf_s({{ cond = 0; }});
647
648                                0x1: c_ngle_s({{
649                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
650                                        cond = 1;
651                                    else
652                                        cond = 0;
653                                  }});
654
655                                0x2: c_seq_s({{
656                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
657                                        cond = 0;
658                                    else
659                                        cond = (Fs.sf == Ft.sf);
660                                  }});
661
662                                0x3: c_ngl_s({{
663                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
664                                        cond = 1;
665                                    else
666                                        cond = (Fs.sf == Ft.sf);
667                                  }});
668
669                                0x4: c_lt_s({{
670                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
671                                        cond = 0;
672                                    else
673                                        cond = (Fs.sf < Ft.sf);
674                                  }});
675
676                                0x5: c_nge_s({{
677                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
678                                        cond = 1;
679                                    else
680                                        cond = (Fs.sf < Ft.sf);
681                                  }});
682
683                                0x6: c_le_s({{
684                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
685                                        cond = 0;
686                                    else
687                                        cond = (Fs.sf <= Ft.sf);
688                                  }});
689
690                                0x7: c_ngt_s({{
691                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
692                                        cond = 1;
693                                    else
694                                        cond = (Fs.sf <= Ft.sf);
695                                  }});
696                            }
697                        }
698                    }
699
700                    //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
701                    0x1: decode FUNCTION_HI {
702                        0x0: decode FUNCTION_LO {
703                            format FloatOp {
704                                0x0: add_d({{ Fd.df = Fs.df + Ft.df;}});
705                                0x1: sub_d({{ Fd.df = Fs.df - Ft.df;}});
706                                0x2: mul_d({{ Fd.df = Fs.df * Ft.df;}});
707                                0x3: div_d({{ Fd.df = Fs.df / Ft.df;}});
708                                0x4: sqrt_d({{ Fd.df = sqrt(Fs.df);}});
709                                0x5: abs_d({{ Fd.df = fabs(Fs.df);}});
710                                0x6: mov_d({{ Fd.ud = Fs.ud;}});
711                                0x7: neg_d({{ Fd.df = -1 * Fs.df;}});
712                            }
713                        }
714
715                        0x1: decode FUNCTION_LO {
716                            format FloatOp {
717                                0x0: round_l_d({{
718                                    Fd.ud = fpConvert(roundFP(Fs.ud), DOUBLE_TO_LONG);
719                                }});
720
721                                0x1: trunc_l_d({{
722                                    Fd.ud = fpConvert(truncFP(Fs.ud), DOUBLE_TO_LONG);
723                                }});
724
725                                0x2: ceil_l_d({{
726                                    Fd.ud = fpConvert(ceil(Fs.ud), DOUBLE_TO_LONG);
727                                }});
728
729                                0x3: floor_l_d({{
730                                    Fd.ud = fpConvert(floor(Fs.ud), DOUBLE_TO_LONG);
731                                }});
732                            }
733
734                            format FloatOp {
735                                0x4: round_w_d({{
736                                    Fd.uw = fpConvert(roundFP(Fs.ud), DOUBLE_TO_WORD);
737                                }});
738
739                                0x5: trunc_w_d({{
740                                    Fd.uw = fpConvert(truncFP(Fs.ud), DOUBLE_TO_WORD);
741                                }});
742
743                                0x6: ceil_w_d({{
744                                    Fd.uw = fpConvert(ceil(Fs.ud), DOUBLE_TO_WORD);
745                                }});
746
747                                0x7: floor_w_d({{
748                                    Fd.uw = fpConvert(floor(Fs.ud), DOUBLE_TO_WORD);
749                                }});
750                            }
751                        }
752
753                        0x2: decode FUNCTION_LO {
754                            0x1: decode MOVCF {
755                                format FloatOp {
756                                    0x0: movf_d({{if (getFPConditionCode(CC) == 0) Fd.df = Fs.df; }});
757                                    0x1: movt_d({{if (getFPConditionCode(CC) == 1) Fd.df = Fs.df; }});
758                                }
759                            }
760
761                            format BasicOp {
762                                0x2: movz_d({{ if (Rt == 0) Fd.df = Fs.df; }});
763                                0x3: movn_d({{ if (Rt != 0) Fd.df = Fs.df; }});
764                            }
765
766                            format FloatOp {
767                                0x5: recip_d({{ Fd.df = 1 / Fs.df}});
768                                0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }});
769                            }
770                        }
771
772                        0x4: decode FUNCTION_LO {
773                            format FloatOp {
774                                0x0: cvt_s_d({{
775                                    Fd.uw = fpConvert(Fs.ud, DOUBLE_TO_SINGLE);
776                                }});
777
778                                0x4: cvt_w_d({{
779                                    Fd.uw = fpConvert(Fs.ud, DOUBLE_TO_WORD);
780                                }});
781
782                                0x5: cvt_l_d({{
783                                    Fd.ud = fpConvert(Fs.ud, DOUBLE_TO_LONG);
784                                }});
785                            }
786                        }
787
788                        0x6: decode FUNCTION_LO {
789                            format FloatCompareOp {
790                                0x0: c_f_d({{ cond = 0; }});
791
792                                0x1: c_un_d({{
793                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
794                                        cond = 1;
795                                    else
796                                        cond = 0;
797                                }});
798
799                                0x2: c_eq_d({{
800                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
801                                        cond = 0;
802                                    else
803                                        cond = (Fs.df == Ft.df);
804                                }});
805
806                                0x3: c_ueq_d({{
807                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
808                                        cond = 1;
809                                    else
810                                        cond = (Fs.df == Ft.df);
811                                }});
812
813                                0x4: c_olt_d({{
814                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
815                                        cond = 0;
816                                    else
817                                        cond = (Fs.df < Ft.df);
818                                }});
819
820                                0x5: c_ult_d({{
821                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
822                                        cond = 1;
823                                    else
824                                        cond = (Fs.df < Ft.df);
825                                }});
826
827                                0x6: c_ole_d({{
828                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
829                                        cond = 0;
830                                    else
831                                        cond = (Fs.df <= Ft.df);
832                                }});
833
834                                0x7: c_ule_d({{
835                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
836                                        cond = 1;
837                                    else
838                                        cond = (Fs.df <= Ft.df);
839                                }});
840                            }
841                        }
842
843                        0x7: decode FUNCTION_LO {
844                            format FloatCompareWithXcptOp {
845                                0x0: c_sf_d({{ cond = 0; }});
846
847                                0x1: c_ngle_d({{
848                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
849                                        cond = 1;
850                                    else
851                                        cond = 0;
852                                  }});
853
854                                0x2: c_seq_d({{
855                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
856                                        cond = 0;
857                                    else
858                                        cond = (Fs.df == Ft.df);
859                                  }});
860
861                                0x3: c_ngl_d({{
862                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
863                                        cond = 1;
864                                    else
865                                        cond = (Fs.df == Ft.df);
866                                  }});
867
868                                0x4: c_lt_d({{
869                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
870                                        cond = 0;
871                                    else
872                                        cond = (Fs.df < Ft.df);
873                                  }});
874
875                                0x5: c_nge_d({{
876                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
877                                        cond = 1;
878                                    else
879                                        cond = (Fs.df < Ft.df);
880                                  }});
881
882                                0x6: c_le_d({{
883                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
884                                        cond = 0;
885                                    else
886                                        cond = (Fs.df <= Ft.df);
887                                  }});
888
889                                0x7: c_ngt_d({{
890                                    if (unorderedFP(Fs.df) || unorderedFP(Ft.df))
891                                        cond = 1;
892                                    else
893                                        cond = (Fs.df <= Ft.df);
894                                  }});
895                            }
896                        }
897                    }
898
899                    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
900                    0x4: decode FUNCTION {
901                        format FloatConvertOp {
902                            0x20: cvt_s_w({{
903                                Fd.uw = fpConvert(Fs.sf, WORD_TO_SINGLE);
904                            }});
905
906                            0x21: cvt_d_w({{
907                                Fd.ud = fpConvert(Fs.sf, WORD_TO_DOUBLE);
908                            }});
909                        }
910
911                        format Float64ConvertOp {
912                            0x26: cvt_ps_pw({{
913                                Fd.ud = fpConvert(Fs.ud, WORD_TO_PS);
914                            }});
915                        }
916                    }
917
918                    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
919                    //Note: "1. Format type L is legal only if 64-bit floating point operations
920                    //are enabled."
921                    0x5: decode FUNCTION_HI {
922                        format Float64ConvertOp {
923                            0x20: cvt_s_l({{
924                                Fd.uw = fpConvert(Fs.ud, LONG_TO_SINGLE);
925                            }});
926
927                            0x21: cvt_d_l({{
928                                Fd.ud = fpConvert(Fs.ud, LONG_TO_DOUBLE);
929                            }});
930
931                            0x26: cvt_ps_l({{
932                                Fd.ud = fpConvert(Fs.ud, LONG_TO_PS);
933                            }});
934                        }
935                    }
936
937                    //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
938                    //Note: "1. Format type PS is legal only if 64-bit floating point operations
939                    //are enabled. "
940                    0x6: decode FUNCTION_HI {
941                        0x0: decode FUNCTION_LO {
942                            format Float64Op {
943                                0x0: add_ps({{
944                                    Fd1.sf = Fs1.sf + Ft2.sf;
945                                    Fd2.sf = Fs2.sf + Ft2.sf;
946                                }});
947
948                                0x1: sub_ps({{
949                                    Fd1.sf = Fs1.sf - Ft2.sf;
950                                    Fd2.sf = Fs2.sf - Ft2.sf;
951                                }});
952
953                                0x2: mul_ps({{
954                                    Fd1.sf = Fs1.sf * Ft2.sf;
955                                    Fd2.sf = Fs2.sf * Ft2.sf;
956                                }});
957
958                                0x5: abs_ps({{
959                                    Fd1.sf = fabs(Fs1.sf);
960                                    Fd2.sf = fabs(Fs2.sf);
961                                }});
962
963                                0x6: mov_ps({{
964                                    Fd1.sf = Fs1.sf;
965                                    Fd2.sf = Fs2.sf;
966                                }});
967
968                                0x7: neg_ps({{
969                                    Fd1.sf = -1 * Fs1.sf;
970                                    Fd2.sf = -1 * Fs2.sf;
971                                }});
972                            }
973                        }
974
975                        0x2: decode FUNCTION_LO {
976                            0x1: decode MOVCF {
977                                format Float64Op {
978                                    0x0: movf_ps({{
979                                        if (getFPConditionCode(CC) == 0)
980                                            Fd1 = Fs1;
981                                        if (getFPConditionCode(CC+1) == 0)
982                                            Fd2 = Fs2;
983                                    }});
984
985                                    0x1: movt_ps({{
986                                        if (getFPConditionCode(CC) == 1)
987                                            Fd1 = Fs1;
988                                        if (getFPConditionCode(CC+1) == 1)
989                                            Fd2 = Fs2;
990                                    }});
991                                }
992                            }
993
994                            format Float64Op {
995                                0x2: movz_ps({{
996                                    if (getFPConditionCode(CC) == 0)
997                                        Fd1 = Fs1;
998                                    if (getFPConditionCode(CC) == 0)
999                                        Fd2 = Fs2;
1000                                }});
1001
1002                                0x3: movn_ps({{
1003                                    if (getFPConditionCode(CC) == 1)
1004                                        Fd1 = Fs1;
1005                                    if (getFPConditionCode(CC) == 1)
1006                                        Fd2 = Fs2;
1007                                }});
1008                            }
1009
1010                        }
1011
1012                        0x4: decode FUNCTION_LO {
1013                            0x0: Float64Op::cvt_s_pu({{
1014                                Fd.uw = fpConvert(Fs2.uw, PU_TO_SINGLE);
1015                            }});
1016                        }
1017
1018                        0x5: decode FUNCTION_LO {
1019                            format Float64Op {
1020                                0x0: cvt_s_pl({{
1021                                    Fd.uw = fpConvert(Fs1.uw, PL_TO_SINGLE);
1022                                }});
1023
1024                                0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 | Ft1.uw; }});
1025                                0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 | Ft2.uw; }});
1026                                0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 | Ft1.uw; }});
1027                                0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 | Ft2.uw; }});
1028                            }
1029                        }
1030
1031                        0x6: decode FUNCTION_LO {
1032                            format FloatPSCompareOp {
1033                                0x0: c_f_ps({{ cond1 = 0; cond2 = 0; }});
1034
1035                                0x1: c_un_ps({{
1036                                    if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
1037                                        cond1 = 1;
1038                                    else
1039                                        cond1 = 0;
1040
1041                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1042                                        cond2 = 1;
1043                                    else
1044                                        cond2 = 0;
1045
1046                                }});
1047
1048                                0x2: c_eq_ps({{
1049                                    if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
1050                                        cond1 = 0;
1051                                    else
1052                                        cond1 = (Fs1.sf == Ft1.sf);
1053
1054                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1055                                        cond2 = 0;
1056                                    else
1057                                        cond2 = (Fs2.sf == Ft2.sf);
1058                                }});
1059
1060                                0x3: c_ueq_ps({{
1061                                    if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
1062                                        cond1 = 1;
1063                                    else
1064                                        cond1 = (Fs1.sf == Ft1.sf);
1065
1066                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1067                                        cond2 = 1;
1068                                    else
1069                                        cond2 = (Fs2.sf == Ft2.sf);
1070                                }});
1071
1072                                0x4: c_olt_ps({{
1073                                    if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
1074                                        cond1 = 0;
1075                                    else
1076                                        cond1 = (Fs1.sf < Ft1.sf);
1077
1078                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1079                                        cond2 = 0;
1080                                    else
1081                                        cond2 = (Fs2.sf < Ft2.sf);
1082                                }});
1083
1084                                0x5: c_ult_ps({{
1085                                    if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
1086                                        cond1 = 1;
1087                                    else
1088                                        cond1 = (Fs.sf < Ft.sf);
1089
1090                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1091                                        cond2 = 1;
1092                                    else
1093                                        cond2 = (Fs2.sf < Ft2.sf);
1094                                }});
1095
1096                                0x6: c_ole_ps({{
1097                                    if (unorderedFP(Fs.sf) || unorderedFP(Ft.sf))
1098                                        cond1 = 0;
1099                                    else
1100                                        cond1 = (Fs.sf <= Ft.sf);
1101
1102                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1103                                        cond2 = 0;
1104                                    else
1105                                        cond2 = (Fs2.sf <= Ft2.sf);
1106                                }});
1107
1108                                0x7: c_ule_ps({{
1109                                    if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
1110                                        cond1 = 1;
1111                                    else
1112                                        cond1 = (Fs1.sf <= Ft1.sf);
1113
1114                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1115                                        cond2 = 1;
1116                                    else
1117                                        cond2 = (Fs2.sf <= Ft2.sf);
1118                                }});
1119                            }
1120                        }
1121
1122                        0x7: decode FUNCTION_LO {
1123                            format FloatPSCompareWithXcptOp {
1124                                0x0: c_sf_ps({{ cond1 = 0; cond2 = 0; }});
1125
1126                                0x1: c_ngle_ps({{
1127                                    if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
1128                                        cond1 = 1;
1129                                    else
1130                                        cond1 = 0;
1131
1132                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1133                                        cond2 = 1;
1134                                    else
1135                                        cond2 = 0;
1136                                  }});
1137
1138                                0x2: c_seq_ps({{
1139                                    if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
1140                                        cond1 = 0;
1141                                    else
1142                                        cond1 = (Fs1.sf == Ft1.sf);
1143
1144                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1145                                        cond2 = 0;
1146                                    else
1147                                        cond2 = (Fs2.sf == Ft2.sf);
1148                                  }});
1149
1150                                0x3: c_ngl_ps({{
1151                                    if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
1152                                        cond1 = 1;
1153                                    else
1154                                        cond1 = (Fs1.sf == Ft1.sf);
1155
1156                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1157                                        cond2 = 1;
1158                                    else
1159                                        cond2 = (Fs2.sf == Ft2.sf);
1160                                  }});
1161
1162                                0x4: c_lt_ps({{
1163                                    if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
1164                                        cond1 = 0;
1165                                    else
1166                                        cond1 = (Fs1.sf < Ft1.sf);
1167
1168                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1169                                        cond2 = 0;
1170                                    else
1171                                        cond2 = (Fs2.sf < Ft2.sf);
1172                                  }});
1173
1174                                0x5: c_nge_ps({{
1175                                    if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
1176                                        cond1 = 1;
1177                                    else
1178                                        cond1 = (Fs1.sf < Ft1.sf);
1179
1180                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1181                                        cond2 = 1;
1182                                    else
1183                                        cond2 = (Fs2.sf < Ft2.sf);
1184                                  }});
1185
1186                                0x6: c_le_ps({{
1187                                    if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
1188                                        cond1 = 0;
1189                                    else
1190                                        cond1 = (Fs1.sf <= Ft1.sf);
1191
1192                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1193                                        cond2 = 0;
1194                                    else
1195                                        cond2 = (Fs2.sf <= Ft2.sf);
1196                                  }});
1197
1198                                0x7: c_ngt_ps({{
1199                                    if (unorderedFP(Fs1.sf) || unorderedFP(Ft1.sf))
1200                                        cond1 = 1;
1201                                    else
1202                                        cond1 = (Fs1.sf <= Ft1.sf);
1203
1204                                    if (unorderedFP(Fs2.sf) || unorderedFP(Ft2.sf))
1205                                        cond2 = 1;
1206                                    else
1207                                        cond2 = (Fs2.sf <= Ft2.sf);
1208                                  }});
1209                            }
1210                        }
1211                    }
1212                }
1213            }
1214        }
1215
1216        //Table A-19 MIPS32 COP2 Encoding of rs Field
1217        0x2: decode RS_MSB {
1218            0x0: decode RS_HI {
1219                0x0: decode RS_LO {
1220                    format WarnUnimpl {
1221                        0x0: mfc2();
1222                        0x2: cfc2();
1223                        0x3: mfhc2();
1224                        0x4: mtc2();
1225                        0x6: ctc2();
1226                        0x7: mftc2();
1227                    }
1228                }
1229
1230                0x1: decode ND {
1231                    0x0: decode TF {
1232                        format WarnUnimpl {
1233                            0x0: bc2f();
1234                            0x1: bc2t();
1235                        }
1236                    }
1237
1238                    0x1: decode TF {
1239                        format WarnUnimpl {
1240                            0x0: bc2fl();
1241                            0x1: bc2tl();
1242                        }
1243                    }
1244                }
1245            }
1246        }
1247
1248        //Table A-20 MIPS64 COP1X Encoding of Function Field 1
1249        //Note: "COP1X instructions are legal only if 64-bit floating point
1250        //operations are enabled."
1251        0x3: decode FUNCTION_HI {
1252            0x0: decode FUNCTION_LO {
1253                format LoadFloatMemory {
1254                    0x0: lwxc1({{ Ft.uw = Mem.uw;}}, {{ EA = Rs + Rt; }});
1255                    0x1: ldxc1({{ Ft.ud = Mem.ud;}}, {{ EA = Rs + Rt; }});
1256                    0x5: luxc1({{ Ft.uw = Mem.ud;}}, {{ EA = Rs + Rt; }});
1257                }
1258            }
1259
1260            0x1: decode FUNCTION_LO {
1261                format StoreFloatMemory {
1262                    0x0: swxc1({{ Mem.uw = Ft.uw;}}, {{ EA = Rs + Rt; }});
1263                    0x1: sdxc1({{ Mem.ud = Ft.ud;}}, {{ EA = Rs + Rt; }});
1264                    0x5: suxc1({{ Mem.ud = Ft.ud;}}, {{ EA = Rs + Rt; }});
1265                }
1266
1267                0x7: WarnUnimpl::prefx();
1268            }
1269
1270            format FloatOp {
1271                0x3: WarnUnimpl::alnv_ps();
1272
1273                format BasicOp {
1274                    0x4: decode FUNCTION_LO {
1275                        0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }});
1276                        0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }});
1277                        0x6: madd_ps({{
1278                            Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df;
1279                            Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df;
1280                        }});
1281                    }
1282
1283                    0x5: decode FUNCTION_LO {
1284                        0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }});
1285                        0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }});
1286                        0x6: msub_ps({{
1287                            Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df;
1288                            Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df;
1289                        }});
1290                    }
1291
1292                    0x6: decode FUNCTION_LO {
1293                        0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
1294                        0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }});
1295                        0x6: nmadd_ps({{
1296                            Fd1.sf = -1 * ((Fs1.df * Ft1.df) + Fr1.df);
1297                            Fd2.sf = -1 * ((Fs2.df * Ft2.df) + Fr2.df);
1298                        }});
1299                    }
1300
1301                    0x7: decode FUNCTION_LO {
1302                        0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
1303                        0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }});
1304                        0x6: nmsub_ps({{
1305                            Fd1.sf = -1 * ((Fs1.df * Ft1.df) - Fr1.df);
1306                            Fd2.sf = -1 * ((Fs2.df * Ft2.df) - Fr2.df);
1307                        }});
1308                    }
1309                }
1310            }
1311        }
1312
1313        format BranchLikely {
1314            0x4: beql({{ cond = (Rs.sw == 0); }});
1315            0x5: bnel({{ cond = (Rs.sw != 0); }});
1316            0x6: blezl({{ cond = (Rs.sw <= 0); }});
1317            0x7: bgtzl({{ cond = (Rs.sw > 0); }});
1318        }
1319    }
1320
1321    0x3: decode OPCODE_LO default FailUnimpl::reserved() {
1322
1323        //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
1324        0x4: decode FUNCTION_HI {
1325
1326            0x0: decode FUNCTION_LO {
1327                format IntOp {
1328                    0x0: madd({{
1329                        int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
1330                        temp1 = temp1 + (Rs.sw * Rt.sw);
1331                        xc->setMiscReg(Hi,temp1<63:32>);
1332                        xc->setMiscReg(Lo,temp1<31:0>);
1333                            }});
1334
1335                    0x1: maddu({{
1336                        int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
1337                        temp1 = temp1 + (Rs.uw * Rt.uw);
1338                        xc->setMiscReg(Hi,temp1<63:32>);
1339                        xc->setMiscReg(Lo,temp1<31:0>);
1340                            }});
1341
1342                    0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; 	}});
1343
1344                    0x4: msub({{
1345                        int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
1346                        temp1 = temp1 - (Rs.sw * Rt.sw);
1347                        xc->setMiscReg(Hi,temp1<63:32>);
1348                        xc->setMiscReg(Lo,temp1<31:0>);
1349                            }});
1350
1351                    0x5: msubu({{
1352                        int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
1353                        temp1 = temp1 - (Rs.uw * Rt.uw);
1354                        xc->setMiscReg(Hi,temp1<63:32>);
1355                        xc->setMiscReg(Lo,temp1<31:0>);
1356                            }});
1357                }
1358            }
1359
1360            0x4: decode FUNCTION_LO {
1361                format BasicOp {
1362                    0x0: clz({{
1363                        int cnt = 0;
1364                        uint32_t mask = 0x80000000;
1365                        for (int i=0; i < 32; i++) {
1366                            if( (Rs & mask) == 0) {
1367                                cnt++;
1368                            } else {
1369                                break;
1370                            }
1371                        }
1372                        Rd.uw = cnt;
1373                    }});
1374
1375                    0x1: clo({{
1376                        int cnt = 0;
1377                        uint32_t mask = 0x80000000;
1378                        for (int i=0; i < 32; i++) {
1379                            if( (Rs & mask) != 0) {
1380                                cnt++;
1381                            } else {
1382                                break;
1383                            }
1384                        }
1385                        Rd.uw = cnt;
1386                    }});
1387                }
1388            }
1389
1390            0x7: decode FUNCTION_LO {
1391                0x7: WarnUnimpl::sdbbp();
1392            }
1393        }
1394
1395        //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture
1396        0x7: decode FUNCTION_HI {
1397
1398            0x0: decode FUNCTION_LO {
1399                format FailUnimpl {
1400                    0x1: ext();
1401                    0x4: ins();
1402                }
1403            }
1404
1405            0x1: decode FUNCTION_LO {
1406                format FailUnimpl {
1407                    0x0: fork();
1408                    0x1: yield();
1409                }
1410            }
1411
1412
1413            //Table A-10 MIPS32 BSHFL Encoding of sa Field
1414            0x4: decode SA {
1415
1416                0x02: FailUnimpl::wsbh();
1417
1418                format BasicOp {
1419                    0x10: seb({{ Rd.sw = Rt<7:0>}});
1420                    0x18: seh({{ Rd.sw = Rt<15:0>}});
1421                }
1422            }
1423
1424            0x6: decode FUNCTION_LO {
1425                0x7: FailUnimpl::rdhwr();//{{ /*Rt = xc->hwRegs[RD];*/ }}
1426            }
1427        }
1428    }
1429
1430    0x4: decode OPCODE_LO default FailUnimpl::reserved() {
1431        format LoadMemory {
1432            0x0: lb({{ Rt.sw = Mem.sb; }});
1433            0x1: lh({{ Rt.sw = Mem.sh; }});
1434
1435            0x2: lwl({{
1436                uint32_t mem_word = Mem.uw;
1437                uint32_t unalign_addr = Rs + disp;
1438                uint32_t offset = unalign_addr & 0x00000003;
1439#if BYTE_ORDER == BIG_ENDIAN
1440                switch(offset)
1441                {
1442                  case 0:
1443                    Rt = mem_word;
1444                    break;
1445
1446                  case 1:
1447                    Rt &= 0x000F;
1448                    Rt |= (mem_word << 4);
1449                    break;
1450
1451                  case 2:
1452                    Rt &= 0x00FF;
1453                    Rt |= (mem_word << 8);
1454                    break;
1455
1456                  case 3:
1457                    Rt &= 0x0FFF;
1458                    Rt |= (mem_word << 12);
1459                    break;
1460
1461                  default:
1462                    panic("lwl: bad offset");
1463                }
1464#elif BYTE_ORDER == LITTLE_ENDIAN
1465                switch(offset)
1466                {
1467                  case 0:
1468                    Rt &= 0x0FFF;
1469                    Rt |= (mem_word << 12);
1470                    break;
1471
1472                  case 1:
1473                    Rt &= 0x00FF;
1474                    Rt |= (mem_word << 8);
1475                    break;
1476
1477                  case 2:
1478                    Rt &= 0x000F;
1479                    Rt |= (mem_word << 4);
1480                    break;
1481
1482                  case 3:
1483                    Rt = mem_word;
1484                    break;
1485
1486                  default:
1487                    panic("lwl: bad offset");
1488                }
1489#endif
1490            }}, {{ EA = (Rs + disp) & ~3; }});
1491
1492            0x3: lw({{ Rt.sw = Mem.sw; }});
1493            0x4: lbu({{ Rt.uw = Mem.ub; }});
1494            0x5: lhu({{ Rt.uw = Mem.uh; }});
1495            0x6: lwr({{
1496                uint32_t mem_word = Mem.uw;
1497                uint32_t unalign_addr = Rs + disp;
1498                uint32_t offset = unalign_addr & 0x00000003;
1499
1500#if BYTE_ORDER == BIG_ENDIAN
1501                switch(offset)
1502                {
1503                  case 0: Rt &= 0xFFF0;  Rt |= (mem_word >> 12); break;
1504                  case 1: Rt &= 0xFF00;  Rt |= (mem_word >> 8);  break;
1505                  case 2: Rt &= 0xF000;  Rt |= (mem_word >> 4);  break;
1506                  case 3: Rt = mem_word; break;
1507                  default: panic("lwr: bad offset");
1508                }
1509#elif BYTE_ORDER == LITTLE_ENDIAN
1510                switch(offset)
1511                {
1512                  case 0: Rt = mem_word; break;
1513                  case 1: Rt &= 0xF000;  Rt |= (mem_word >> 4);  break;
1514                  case 2: Rt &= 0xFF00;  Rt |= (mem_word >> 8);  break;
1515                  case 3: Rt &= 0xFFF0;  Rt |= (mem_word >> 12); break;
1516                  default: panic("lwr: bad offset");
1517                }
1518#endif
1519            }},
1520            {{ EA = (Rs + disp) & ~3; }});
1521        }
1522
1523        0x7: FailUnimpl::reserved();
1524    }
1525
1526    0x5: decode OPCODE_LO default FailUnimpl::reserved() {
1527        format StoreMemory {
1528            0x0: sb({{ Mem.ub = Rt<7:0>; }});
1529            0x1: sh({{ Mem.uh = Rt<15:0>; }});
1530            0x2: swl({{
1531                uint32_t mem_word = 0;
1532                uint32_t aligned_addr = (Rs + disp) & ~3;
1533                uint32_t unalign_addr = Rs + disp;
1534                uint32_t offset = unalign_addr & 0x00000003;
1535
1536                DPRINTF(IEW,"Execute: aligned=0x%x unaligned=0x%x\n offset=0x%x",
1537                        aligned_addr,unalign_addr,offset);
1538
1539                fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags);
1540
1541#if BYTE_ORDER == BIG_ENDIAN
1542                switch(offset)
1543                {
1544                  case 0:
1545                    Mem = Rt;
1546                    break;
1547
1548                  case 1:
1549                    mem_word &= 0xF000;
1550                    mem_word |= (Rt >> 4);
1551                    Mem = mem_word;
1552                    break;
1553
1554                  case 2:
1555                    mem_word &= 0xFF00;
1556                    mem_word |= (Rt >> 8);
1557                    Mem = mem_word;
1558                    break;
1559
1560                  case 3:
1561                    mem_word &= 0xFFF0;
1562                    mem_word |= (Rt >> 12);
1563                    Mem = mem_word;
1564                   break;
1565
1566                  default:
1567                    panic("swl: bad offset");
1568                }
1569#elif BYTE_ORDER == LITTLE_ENDIAN
1570                switch(offset)
1571                {
1572                  case 0:
1573                    mem_word &= 0xFFF0;
1574                    mem_word |= (Rt >> 12);
1575                    Mem = mem_word;
1576                    break;
1577
1578                  case 1:
1579                    mem_word &= 0xFF00;
1580                    mem_word |= (Rt >> 8);
1581                    Mem = mem_word;
1582                    break;
1583
1584                  case 2:
1585                    mem_word &= 0xF000;
1586                    mem_word |= (Rt >> 4);
1587                    Mem = mem_word;
1588                    break;
1589
1590                  case 3:
1591                    Mem = Rt;
1592                   break;
1593
1594                  default:
1595                    panic("swl: bad offset");
1596                }
1597#endif
1598            }},{{ EA = (Rs + disp) & ~3; }},mem_flags = NO_ALIGN_FAULT);
1599
1600            0x3: sw({{ Mem.uw = Rt<31:0>; }});
1601
1602            0x6: swr({{
1603                uint32_t mem_word = 0;
1604                uint32_t aligned_addr = (Rs + disp) & ~3;
1605                uint32_t unalign_addr = Rs + disp;
1606                uint32_t offset = unalign_addr & 0x00000003;
1607
1608                fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags);
1609
1610#if BYTE_ORDER == BIG_ENDIAN
1611                switch(offset)
1612                {
1613                  case 0:
1614                    mem_word &= 0x0FFF;
1615                    mem_word |= (Rt << 12);
1616                    Mem = mem_word;
1617                    break;
1618
1619                  case 1:
1620                    mem_word &= 0x00FF;
1621                    mem_word |= (Rt << 8);
1622                    Mem = mem_word;
1623                    break;
1624
1625                  case 2:
1626                    mem_word &= 0x000F;
1627                    mem_word |= (Rt << 4);
1628                    Mem = mem_word;
1629                    break;
1630
1631                  case 3:
1632                    Mem = Rt;
1633                    break;
1634
1635                  default:
1636                    panic("swr: bad offset");
1637                }
1638#elif BYTE_ORDER == LITTLE_ENDIAN
1639                switch(offset)
1640                {
1641                  case 0:
1642                    Mem = Rt;
1643                    break;
1644
1645                  case 1:
1646                    mem_word &= 0x000F;
1647                    mem_word |= (Rt << 4);
1648                    Mem = mem_word;
1649                    break;
1650
1651                  case 2:
1652                    mem_word &= 0x00FF;
1653                    mem_word |= (Rt << 8);
1654                    Mem = mem_word;
1655                    break;
1656
1657                  case 3:
1658                    mem_word &= 0x0FFF;
1659                    mem_word |= (Rt << 12);
1660                    Mem = mem_word;
1661                    break;
1662
1663                  default:
1664                    panic("swr: bad offset");
1665                }
1666#endif
1667            }},{{ EA = (Rs + disp) & ~3;}},mem_flags = NO_ALIGN_FAULT);
1668        }
1669
1670        format WarnUnimpl {
1671            0x7: cache();
1672        }
1673
1674    }
1675
1676    0x6: decode OPCODE_LO default FailUnimpl::reserved() {
1677        0x0: LoadMemory::ll({{Rt.uw = Mem.uw}},mem_flags=LOCKED);
1678
1679        format LoadFloatMemory {
1680            0x1: lwc1({{ Ft.uw = Mem.uw;    }});
1681            0x5: ldc1({{ Ft.ud = Mem.ud; }});
1682        }
1683    }
1684
1685
1686    0x7: decode OPCODE_LO default FailUnimpl::reserved() {
1687        0x0: StoreMemory::sc({{ Mem.uw = Rt.uw; Rt.uw = 1; }});
1688
1689        format StoreFloatMemory {
1690            0x1: swc1({{ Mem.uw = Ft.uw; }});
1691            0x5: sdc1({{ Mem.ud = Ft.ud; }});
1692        }
1693    }
1694}
1695
1696
1697