decoder.isa revision 2602
13536SN/A// -*- mode:c++ -*- 27752SWilliam.Wang@arm.com 37752SWilliam.Wang@arm.com//////////////////////////////////////////////////////////////////// 47752SWilliam.Wang@arm.com// 57752SWilliam.Wang@arm.com// The actual MIPS32 ISA decoder 67752SWilliam.Wang@arm.com// ----------------------------- 77752SWilliam.Wang@arm.com// The following instructions are specified in the MIPS32 ISA 87752SWilliam.Wang@arm.com// Specification. Decoding closely follows the style specified 97752SWilliam.Wang@arm.com// in the MIPS32 ISAthe specification document starting with Table 107752SWilliam.Wang@arm.com// A-2 (document available @ www.mips.com) 117752SWilliam.Wang@arm.com// 127752SWilliam.Wang@arm.com//@todo: Distinguish "unknown/future" use insts from "reserved" 137752SWilliam.Wang@arm.com// ones 143536SN/Adecode OPCODE_HI default Unknown::unknown() { 153536SN/A 163536SN/A // Derived From ... Table A-2 MIPS32 ISA Manual 173536SN/A 0x0: decode OPCODE_LO { 183536SN/A 193536SN/A 0x0: decode FUNCTION_HI { 203536SN/A 0x0: decode FUNCTION_LO { 213536SN/A 0x1: decode MOVCI { 223536SN/A format BasicOp { 233536SN/A 0: movf({{ if (xc->readMiscReg(FPCR) != CC) Rd = Rs}}); 243536SN/A 1: movt({{ if (xc->readMiscReg(FPCR) == CC) Rd = Rs}}); 253536SN/A } 263536SN/A } 273536SN/A 283536SN/A format BasicOp { 293536SN/A 303536SN/A //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 313536SN/A //are used to distinguish among the SLL, NOP, SSNOP and EHB functions. 323536SN/A 0x0: decode RS { 333536SN/A 0x0: decode RT { //fix Nop traditional vs. Nop converted disassembly later 343536SN/A 0x0: decode RD default Nop::nop(){ 353536SN/A 0x0: decode SA { 363536SN/A 0x1: ssnop({{ ; }}); //really sll r0,r0,1 373536SN/A 0x3: ehb({{ ; }}); //really sll r0,r0,3 383536SN/A } 393536SN/A } 403536SN/A 417752SWilliam.Wang@arm.com default: sll({{ Rd = Rt.uw << SA; }}); 423536SN/A } 433536SN/A 443536SN/A } 458332Snate@binkert.org 468332Snate@binkert.org 0x2: decode RS_SRL { 473536SN/A 0x0:decode SRL { 483536SN/A 0: srl({{ Rd = Rt.uw >> SA; }}); 493536SN/A 503536SN/A //Hardcoded assuming 32-bit ISA, probably need parameter here 513536SN/A 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 523536SN/A } 533536SN/A } 545543SN/A 555543SN/A 0x3: decode RS { 563536SN/A 0x0: sra({{ 573536SN/A uint32_t temp = Rt >> SA; 583536SN/A 593536SN/A if ( (Rt & 0x80000000) > 0 ) { 603536SN/A uint32_t mask = 0x80000000; 613536SN/A for(int i=0; i < SA; i++) { 623536SN/A temp |= mask; 633536SN/A mask = mask >> 1; 643536SN/A } 653536SN/A } 663536SN/A 675543SN/A Rd = temp; 685543SN/A }}); 693536SN/A } 703536SN/A 713536SN/A 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 723536SN/A 733536SN/A 0x6: decode SRLV { 743536SN/A 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 753536SN/A 763536SN/A //Hardcoded assuming 32-bit ISA, probably need parameter here 773536SN/A 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 783536SN/A } 793536SN/A 803536SN/A 0x7: srav({{ 813536SN/A int shift_amt = Rs<4:0>; 823536SN/A 833536SN/A uint32_t temp = Rt >> shift_amt; 843536SN/A 855543SN/A if ( (Rt & 0x80000000) > 0 ) { 863536SN/A uint32_t mask = 0x80000000; 873536SN/A for(int i=0; i < shift_amt; i++) { 883536SN/A temp |= mask; 893536SN/A mask = mask >> 1; 903536SN/A } 913536SN/A } 923536SN/A 933536SN/A Rd = temp; 943536SN/A }}); 953536SN/A } 963536SN/A } 973536SN/A 983536SN/A 0x1: decode FUNCTION_LO { 993536SN/A 1003536SN/A //Table A-3 Note: "Specific encodings of the hint field are used 1013536SN/A //to distinguish JR from JR.HB and JALR from JALR.HB" 1023536SN/A format Jump { 1033536SN/A 0x0: decode HINT { 1043536SN/A 0:jr({{ NNPC = Rs & ~1; }},IsReturn); 1055543SN/A 1065543SN/A 1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn); 1073536SN/A } 1083536SN/A 1093536SN/A 0x1: decode HINT { 1103536SN/A 0: jalr({{ Rd = NNPC; NNPC = Rs; }},IsCall,IsReturn); 1113536SN/A 1123536SN/A 1: jalr_hb({{ Rd = NNPC; NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn); 1133536SN/A } 1143536SN/A } 1153536SN/A 1163536SN/A format BasicOp { 1173536SN/A 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 1183536SN/A 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 1193536SN/A } 1203536SN/A 1213536SN/A format BasicOp { 1223536SN/A 0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative); 1233536SN/A 0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative); 1243536SN/A 0x7: sync({{ panic("Not implemented sync yet"); }},IsNonSpeculative); 1253536SN/A } 1263536SN/A } 1273536SN/A 1283536SN/A 0x2: decode FUNCTION_LO { 1293536SN/A format BasicOp { 1303536SN/A 0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }}); 1313536SN/A 0x1: mthi({{ xc->setMiscReg(Hi,Rs); }}); 1323536SN/A 0x2: mflo({{ Rd = xc->readMiscReg(Lo); }}); 1335569SN/A 0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }}); 1343536SN/A } 1353536SN/A } 1363536SN/A 1378229Snate@binkert.org 0x3: decode FUNCTION_LO { 1388229Snate@binkert.org format IntOp { 1398229Snate@binkert.org 0x0: mult({{ 1407752SWilliam.Wang@arm.com int64_t temp1 = Rs.sd * Rt.sd; 1417752SWilliam.Wang@arm.com xc->setMiscReg(Hi,temp1<63:32>); 1423536SN/A xc->setMiscReg(Lo,temp1<31:0>); 1433536SN/A }}); 1443536SN/A 1453536SN/A 0x1: multu({{ 1468541Sgblack@eecs.umich.edu uint64_t temp1 = Rs.ud * Rt.ud; 1478229Snate@binkert.org xc->setMiscReg(Hi,temp1<63:32>); 1483536SN/A xc->setMiscReg(Lo,temp1<31:0>); 1497752SWilliam.Wang@arm.com }}); 1508232Snate@binkert.org 1518232Snate@binkert.org 0x2: div({{ 1528229Snate@binkert.org xc->setMiscReg(Hi,Rs.sd % Rt.sd); 1533536SN/A xc->setMiscReg(Lo,Rs.sd / Rt.sd); 1543536SN/A }}); 1558782Sgblack@eecs.umich.edu 1563536SN/A 0x3: divu({{ 1573536SN/A xc->setMiscReg(Hi,Rs.ud % Rt.ud); 1583536SN/A xc->setMiscReg(Lo,Rs.ud / Rt.ud); 1597752SWilliam.Wang@arm.com }}); 1603536SN/A } 1615569SN/A } 1627752SWilliam.Wang@arm.com 1633536SN/A 0x4: decode HINT { 1643536SN/A 0x0: decode FUNCTION_LO { 1653536SN/A format IntOp { 1665569SN/A 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}}); 1675569SN/A 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 1685569SN/A 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}}); 1693536SN/A 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 1703536SN/A 0x4: and({{ Rd = Rs & Rt;}}); 1713536SN/A 0x5: or({{ Rd = Rs | Rt;}}); 1728782Sgblack@eecs.umich.edu 0x6: xor({{ Rd = Rs ^ Rt;}}); 1738782Sgblack@eecs.umich.edu 0x7: nor({{ Rd = ~(Rs | Rt);}}); 1748782Sgblack@eecs.umich.edu } 1758782Sgblack@eecs.umich.edu } 1763536SN/A } 1778782Sgblack@eecs.umich.edu 1788782Sgblack@eecs.umich.edu 0x5: decode HINT { 1798782Sgblack@eecs.umich.edu 0x0: decode FUNCTION_LO { 1808782Sgblack@eecs.umich.edu format IntOp{ 1818782Sgblack@eecs.umich.edu 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 1828782Sgblack@eecs.umich.edu 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 1838782Sgblack@eecs.umich.edu } 1848782Sgblack@eecs.umich.edu } 1858782Sgblack@eecs.umich.edu } 1868782Sgblack@eecs.umich.edu 1878782Sgblack@eecs.umich.edu 0x6: decode FUNCTION_LO { 1888782Sgblack@eecs.umich.edu format Trap { 1898782Sgblack@eecs.umich.edu 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 1908782Sgblack@eecs.umich.edu 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 1913536SN/A 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 1928782Sgblack@eecs.umich.edu 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 1938782Sgblack@eecs.umich.edu 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 1943536SN/A 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 1953536SN/A } 1965569SN/A } 1975569SN/A } 1985569SN/A 1995569SN/A 0x1: decode REGIMM_HI { 2003536SN/A 0x0: decode REGIMM_LO { 2013536SN/A format Branch { 2023536SN/A 0x0: bltz({{ cond = (Rs.sw < 0); }}); 2037752SWilliam.Wang@arm.com 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 2047752SWilliam.Wang@arm.com } 2053579SN/A 2063536SN/A format BranchLikely { 2077752SWilliam.Wang@arm.com //MIPS obsolete instructions 2087752SWilliam.Wang@arm.com 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 2097752SWilliam.Wang@arm.com 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 2107752SWilliam.Wang@arm.com } 2117752SWilliam.Wang@arm.com } 2127752SWilliam.Wang@arm.com 2137752SWilliam.Wang@arm.com 0x1: decode REGIMM_LO { 2147752SWilliam.Wang@arm.com format Trap { 2157752SWilliam.Wang@arm.com 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 2167752SWilliam.Wang@arm.com 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 2177752SWilliam.Wang@arm.com 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 2187752SWilliam.Wang@arm.com 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 2197752SWilliam.Wang@arm.com 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 2207752SWilliam.Wang@arm.com 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 2217752SWilliam.Wang@arm.com } 2227752SWilliam.Wang@arm.com } 2237752SWilliam.Wang@arm.com 2247752SWilliam.Wang@arm.com 0x2: decode REGIMM_LO { 2257752SWilliam.Wang@arm.com format Branch { 2263536SN/A 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn); 2277752SWilliam.Wang@arm.com 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn); 2287752SWilliam.Wang@arm.com } 2297752SWilliam.Wang@arm.com 2307752SWilliam.Wang@arm.com format BranchLikely { 2317752SWilliam.Wang@arm.com //Will be removed in future MIPS releases 2327752SWilliam.Wang@arm.com 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn); 2337752SWilliam.Wang@arm.com 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn); 2347752SWilliam.Wang@arm.com } 2357752SWilliam.Wang@arm.com } 2367752SWilliam.Wang@arm.com 2377752SWilliam.Wang@arm.com 0x3: decode REGIMM_LO { 2387752SWilliam.Wang@arm.com format WarnUnimpl { 2397752SWilliam.Wang@arm.com 0x7: synci(); 2403536SN/A } 2413536SN/A } 2427752SWilliam.Wang@arm.com } 2437752SWilliam.Wang@arm.com 2447752SWilliam.Wang@arm.com format Jump { 2457752SWilliam.Wang@arm.com 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 2463536SN/A 2473536SN/A 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn); 2485569SN/A } 2495569SN/A 2505569SN/A format Branch { 2515569SN/A 0x4: beq({{ cond = (Rs.sw == Rt.sw); }}); 2523536SN/A 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 2533536SN/A 0x6: decode RT { 2543536SN/A 0x0: blez({{ cond = (Rs.sw <= 0); }}); 2557752SWilliam.Wang@arm.com } 2567752SWilliam.Wang@arm.com 2577752SWilliam.Wang@arm.com 0x7: decode RT { 2587752SWilliam.Wang@arm.com 0x0: bgtz({{ cond = (Rs.sw > 0); }}); 2597752SWilliam.Wang@arm.com } 2607752SWilliam.Wang@arm.com } 2617752SWilliam.Wang@arm.com } 2627752SWilliam.Wang@arm.com 2637752SWilliam.Wang@arm.com 0x1: decode OPCODE_LO { 2647752SWilliam.Wang@arm.com format IntOp { 2657752SWilliam.Wang@arm.com 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}}); 2667752SWilliam.Wang@arm.com 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 2677752SWilliam.Wang@arm.com 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 2687752SWilliam.Wang@arm.com 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); 2697752SWilliam.Wang@arm.com 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 2707752SWilliam.Wang@arm.com 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 2717752SWilliam.Wang@arm.com 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); 2727752SWilliam.Wang@arm.com 2737752SWilliam.Wang@arm.com 0x7: decode RS { 2747752SWilliam.Wang@arm.com 0x0: lui({{ Rt = imm << 16}}); 2757752SWilliam.Wang@arm.com } 2767752SWilliam.Wang@arm.com } 2777752SWilliam.Wang@arm.com } 2787752SWilliam.Wang@arm.com 2797752SWilliam.Wang@arm.com 0x2: decode OPCODE_LO { 2807752SWilliam.Wang@arm.com 2817752SWilliam.Wang@arm.com //Table A-11 MIPS32 COP0 Encoding of rs Field 2827752SWilliam.Wang@arm.com 0x0: decode RS_MSB { 2837752SWilliam.Wang@arm.com 0x0: decode RS { 2847752SWilliam.Wang@arm.com format System { 2857752SWilliam.Wang@arm.com 0x0: mfc0({{ 2867752SWilliam.Wang@arm.com //uint64_t reg_num = Rd.uw; 2877752SWilliam.Wang@arm.com 2887752SWilliam.Wang@arm.com Rt = xc->readMiscReg(RD << 5 | SEL); 2897752SWilliam.Wang@arm.com }}); 2907752SWilliam.Wang@arm.com 2917752SWilliam.Wang@arm.com 0x4: mtc0({{ 2927752SWilliam.Wang@arm.com //uint64_t reg_num = Rd.uw; 2933536SN/A 2943536SN/A xc->setMiscReg(RD << 5 | SEL,Rt); 2957752SWilliam.Wang@arm.com }}); 2967752SWilliam.Wang@arm.com 2973536SN/A 0x8: mftr({{ 2983536SN/A //The contents of the coprocessor 0 register specified by the 2993536SN/A //combination of rd and sel are loaded into general register 3003536SN/A //rt. Note that not all coprocessor 0 registers support the 3013536SN/A //sel field. In those instances, the sel field must be zero. 3023536SN/A 3033550SN/A //MT Code Needed Here 3043536SN/A }}); 3053550SN/A 3063536SN/A 0xC: mttr({{ 3073536SN/A //The contents of the coprocessor 0 register specified by the 3083550SN/A //combination of rd and sel are loaded into general register 3093536SN/A //rt. Note that not all coprocessor 0 registers support the 3103536SN/A //sel field. In those instances, the sel field must be zero. 3113536SN/A 3123536SN/A //MT Code Needed Here 3133536SN/A }}); 3143536SN/A 3157720SN/A 3167720SN/A 0xA: rdpgpr({{ 3173536SN/A //Accessing Previous Shadow Set Register Number 3183536SN/A //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/; 3193536SN/A //uint64_t reg_num = Rt.uw; 3203536SN/A 3217720SN/A //Rd = xc->regs.IntRegFile[prev]; 3228541Sgblack@eecs.umich.edu //Rd = xc->shadowIntRegFile[prev][reg_num]; 3233536SN/A }}); 3243536SN/A 3253536SN/A 0xB: decode RD { 3267720SN/A 3273536SN/A 0x0: decode SC { 3283536SN/A 0x0: dvpe({{ 3293536SN/A Rt.sw = xc->readMiscReg(MVPControl); 3303536SN/A xc->setMiscReg(MVPControl,0); 3313550SN/A }}); 3323536SN/A 3337720SN/A 0x1: evpe({{ 3343536SN/A Rt.sw = xc->readMiscReg(MVPControl); 3353536SN/A xc->setMiscReg(MVPControl,1); 3367720SN/A }}); 3373536SN/A } 3383536SN/A 3393536SN/A 0x1: decode SC { 3403536SN/A 0x0: dmt({{ 3413536SN/A Rt.sw = xc->readMiscReg(VPEControl); 3423536SN/A xc->setMiscReg(VPEControl,0); 3437752SWilliam.Wang@arm.com }}); 3443536SN/A 3453536SN/A 0x1: emt({{ 346 Rt.sw = xc->readMiscReg(VPEControl); 347 xc->setMiscReg(VPEControl,1); 348 }}); 349 } 350 351 0xC: decode SC { 352 0x0: di({{ 353 Rt.sw = xc->readMiscReg(Status); 354 xc->setMiscReg(Status,0); 355 }}); 356 357 0x1: ei({{ 358 Rt.sw = xc->readMiscReg(Status); 359 xc->setMiscReg(Status,1); 360 }}); 361 } 362 } 363 364 0xE: wrpgpr({{ 365 //Accessing Previous Shadow Set Register Number 366 //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/); 367 //uint64_t reg_num = Rd.uw; 368 369 //xc->regs.IntRegFile[prev]; 370 //xc->shadowIntRegFile[prev][reg_num] = Rt; 371 }}); 372 } 373 } 374 375 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 376 0x1: decode FUNCTION { 377 format System { 378 0x01: tlbr({{ }}); 379 0x02: tlbwi({{ }}); 380 0x06: tlbwr({{ }}); 381 0x08: tlbp({{ }}); 382 } 383 384 format WarnUnimpl { 385 0x18: eret(); 386 0x1F: deret(); 387 0x20: wait(); 388 } 389 } 390 } 391 392 //Table A-13 MIPS32 COP1 Encoding of rs Field 393 0x1: decode RS_MSB { 394 395 0x0: decode RS_HI { 396 0x0: decode RS_LO { 397 format FloatOp { 398 0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }}); 399 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); 400 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); 401 0x7: mthc1({{ 402 uint64_t fs_hi = Rt.ud << 32; 403 uint64_t fs_lo = Fs.ud & 0x0000FFFF; 404 Fs.ud = fs_hi & fs_lo; 405 }}); 406 } 407 408 format System { 409 0x2: cfc1({{ 410 uint32_t fcsr_reg = xc->readMiscReg(FCSR); 411 412 switch (FS) 413 { 414 case 0: 415 Rt = xc->readMiscReg(FIR); 416 break; 417 case 25: 418 Rt = 0 | (fcsr_reg & 0xFE000000) >> 24 | (fcsr_reg & 0x00800000) >> 23; 419 break; 420 case 26: 421 Rt = 0 | (fcsr_reg & 0x0003F07C); 422 break; 423 case 28: 424 Rt = 0 | (fcsr_reg); 425 break; 426 case 31: 427 Rt = fcsr_reg; 428 break; 429 default: 430 panic("FP Control Value (%d) Not Available. Ignoring Access to" 431 "Floating Control Status Register",fcsr_reg); 432 } 433 }}); 434 435 0x6: ctc1({{ 436 uint32_t fcsr_reg = xc->readMiscReg(FCSR); 437 uint32_t temp; 438 439 switch (FS) 440 { 441 case 25: 442 temp = 0 | (Rt.uw<7:1> << 25) // move 31...25 443 | (fcsr_reg & 0x01000000) // bit 24 444 | (fcsr_reg & 0x004FFFFF);// bit 22...0 445 break; 446 447 case 26: 448 temp = 0 | (fcsr_reg & 0xFFFC0000) // move 31...18 449 | Rt.uw<17:12> << 12 // bit 17...12 450 | (fcsr_reg & 0x00000F80) << 7// bit 11...7 451 | Rt.uw<6:2> << 2 // bit 6...2 452 | (fcsr_reg & 0x00000002); // bit 1...0 453 break; 454 455 case 28: 456 temp = 0 | (fcsr_reg & 0xFE000000) // move 31...25 457 | Rt.uw<2:2> << 24 // bit 24 458 | (fcsr_reg & 0x00FFF000) << 23// bit 23...12 459 | Rt.uw<11:7> << 7 // bit 24 460 | (fcsr_reg & 0x000007E) 461 | Rt.uw<1:0>;// bit 22...0 462 break; 463 464 case 31: 465 temp = Rt.uw; 466 break; 467 468 default: 469 panic("FP Control Value (%d) Not Available. Ignoring Access to" 470 "Floating Control Status Register",fcsr_reg); 471 } 472 473 xc->setMiscReg(FCSR,temp); 474 }}); 475 } 476 } 477 478 0x1: decode ND { 479 0x0: decode TF { 480 format Branch { 481 0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 482 0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 483 } 484 } 485 486 0x1: decode TF { 487 format BranchLikely { 488 0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 489 0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 490 } 491 } 492 } 493 } 494 495 0x1: decode RS_HI { 496 0x2: decode RS_LO { 497 498 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 499 //(( single-word )) 500 0x0: decode FUNCTION_HI { 501 0x0: decode FUNCTION_LO { 502 format FloatOp { 503 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); 504 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); 505 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); 506 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); 507 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); 508 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); 509 0x6: mov_s({{ Fd.sf = Fs.sf;}}); 510 0x7: neg_s({{ Fd.sf = -1 * Fs.sf;}}); 511 } 512 } 513 514 0x1: decode FUNCTION_LO { 515 format Float64Op { 516 0x0: round_l_s({{ 517 Fd.ud = fpConvert(roundFP(Fs.sf), SINGLE_TO_LONG); 518 }}); 519 520 0x1: trunc_l_s({{ 521 Fd.ud = fpConvert(truncFP(Fs.sf), SINGLE_TO_LONG); 522 }}); 523 524 0x2: ceil_l_s({{ 525 Fd.ud = fpConvert(ceil(Fs.sf), SINGLE_TO_LONG); 526 }}); 527 528 0x3: floor_l_s({{ 529 Fd.ud = fpConvert(floor(Fs.sf), SINGLE_TO_LONG); 530 }}); 531 } 532 533 format FloatOp { 534 0x4: round_w_s({{ 535 Fd.uw = fpConvert(roundFP(Fs.sf), SINGLE_TO_WORD); 536 }}); 537 538 0x5: trunc_w_s({{ 539 Fd.uw = fpConvert(truncFP(Fs.sf), SINGLE_TO_WORD); 540 }}); 541 542 0x6: ceil_w_s({{ 543 Fd.uw = fpConvert(ceil(Fs.sf), SINGLE_TO_WORD); 544 }}); 545 546 0x7: floor_w_s({{ 547 Fd.uw = fpConvert(floor(Fs.sf), SINGLE_TO_WORD); 548 }}); 549 } 550 } 551 552 0x2: decode FUNCTION_LO { 553 0x1: decode MOVCF { 554 format FloatOp { 555 0x0: movf_s({{if (FPConditionCode(CC) == 0) Fd = Fs;}}); 556 0x1: movt_s({{if (FPConditionCode(CC) == 1) Fd = Fs;}}); 557 } 558 } 559 560 format FloatOp { 561 0x2: movz_s({{ if (Rt == 0) Fd = Fs; }}); 562 0x3: movn_s({{ if (Rt != 0) Fd = Fs; }}); 563 0x5: recip_s({{ Fd = 1 / Fs; }}); 564 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}}); 565 } 566 } 567 568 0x4: decode FUNCTION_LO { 569 570 format FloatOp { 571 0x1: cvt_d_s({{ 572 Fd.ud = fpConvert(Fs.sf, SINGLE_TO_DOUBLE); 573 }}); 574 575 0x4: cvt_w_s({{ 576 Fd.uw = fpConvert(Fs.sf, SINGLE_TO_WORD); 577 }}); 578 } 579 580 format Float64Op { 581 0x5: cvt_l_s({{ 582 Fd.ud = fpConvert(Fs.sf, SINGLE_TO_LONG); 583 }}); 584 585 0x6: cvt_ps_st({{ 586 Fd.ud = (uint64_t)Fs.uw << 32 | (uint64_t)Ft.uw; 587 }}); 588 } 589 } 590 591 0x6: decode FUNCTION_LO { 592 format FloatOp { 593 0x0: c_f_s({{ ; }}); 594 0x1: c_un_s({{ ; }}); 595 0x2: c_eq_s({{ ; }}); 596 0x3: c_ueq_s({{ ; }}); 597 0x4: c_olt_s({{ ; }}); 598 0x5: c_ult_s({{ ; }}); 599 0x6: c_ole_s({{ ; }}); 600 0x7: c_ule_s({{ ; }}); 601 } 602 } 603 604 0x7: decode FUNCTION_LO { 605 format FloatOp { 606 0x0: c_sf_s({{ ; }}); 607 0x1: c_ngle_s({{ ; }}); 608 0x2: c_seq_s({{ ; }}); 609 0x3: c_ngl_s({{ ; }}); 610 0x4: c_lt_s({{ ; }}); 611 0x5: c_nge_s({{ ; }}); 612 0x6: c_le_s({{ ; }}); 613 0x7: c_ngt_s({{ ; }}); 614 } 615 } 616 } 617 618 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 619 0x1: decode FUNCTION_HI { 620 0x0: decode FUNCTION_LO { 621 format FloatOp { 622 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 623 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 624 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 625 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 626 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 627 0x5: absd({{ Fd.df = fabs(Fs.df);}}); 628 0x6: movd({{ Fd.ud = Fs.ud;}}); 629 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 630 } 631 } 632 633 0x1: decode FUNCTION_LO { 634 format Float64Op { 635 0x0: round_l_d({{ 636 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_NEAREST); 637 }}); 638 639 0x1: trunc_l_d({{ 640 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_ZERO); 641 }}); 642 643 0x2: ceil_l_d({{ 644 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_UP); 645 }}); 646 647 0x3: floor_l_d({{ 648 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_DOWN); 649 }}); 650 } 651 652 format FloatOp { 653 0x4: round_w_d({{ 654 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_NEAREST); 655 }}); 656 657 0x5: trunc_w_d({{ 658 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_ZERO); 659 }}); 660 661 0x6: ceil_w_d({{ 662 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_UP); 663 }}); 664 665 0x7: floor_w_d({{ 666 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_DOWN); 667 }}); 668 } 669 } 670 671 0x2: decode FUNCTION_LO { 672 0x1: decode MOVCF { 673 format FloatOp { 674 0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }}); 675 0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }}); 676 } 677 } 678 679 format BasicOp { 680 0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }}); 681 0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }}); 682 } 683 684 format Float64Op { 685 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 686 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 687 } 688 } 689 690 0x4: decode FUNCTION_LO { 691 format FloatOp { 692 0x0: cvt_s_d({{ 693 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 694 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_SINGLE, rnd_mode); 695 }}); 696 697 0x4: cvt_w_d({{ 698 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 699 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, rnd_mode); 700 }}); 701 } 702 703 //only legal for 64 bit 704 format Float64Op { 705 0x5: cvt_l_d({{ 706 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 707 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, rnd_mode); 708 }}); 709 } 710 } 711 712 0x6: decode FUNCTION_LO { 713 format FloatOp { 714 0x0: c_f_d({{ ; }}); 715 0x1: c_un_d({{ ; }}); 716 0x2: c_eq_d({{ ; }}); 717 0x3: c_ueq_d({{ ; }}); 718 0x4: c_olt_d({{ ; }}); 719 0x5: c_ult_d({{ ; }}); 720 0x6: c_ole_d({{ ; }}); 721 0x7: c_ule_d({{ ; }}); 722 } 723 } 724 725 0x7: decode FUNCTION_LO { 726 format FloatOp { 727 0x0: c_sf_d({{ ; }}); 728 0x1: c_ngle_d({{ ; }}); 729 0x2: c_seq_d({{ ; }}); 730 0x3: c_ngl_d({{ ; }}); 731 0x4: c_lt_d({{ ; }}); 732 0x5: c_nge_d({{ ; }}); 733 0x6: c_le_d({{ ; }}); 734 0x7: c_ngt_d({{ ; }}); 735 } 736 } 737 } 738 739 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 740 0x4: decode FUNCTION { 741 format FloatOp { 742 0x20: cvt_s_w({{ 743 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 744 Fd.uw = convert_and_round(Fs.sf, WORD_TO_SINGLE, rnd_mode); 745 }}); 746 747 0x21: cvt_d_w({{ 748 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 749 Fd.ud = convert_and_round(Fs.sf, WORD_TO_DOUBLE, rnd_mode); 750 }}); 751 } 752 } 753 754 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 755 //Note: "1. Format type L is legal only if 64-bit floating point operations 756 //are enabled." 757 0x5: decode FUNCTION_HI { 758 format Float64Op { 759 0x10: cvt_s_l({{ 760 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 761 Fd.uw = convert_and_round(Fs.ud, LONG_TO_SINGLE, rnd_mode); 762 }}); 763 764 0x11: cvt_d_l({{ 765 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 766 Fd.ud = convert_and_round(Fs.ud, LONG_TO_DOUBLE, rnd_mode); 767 }}); 768 } 769 } 770 771 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 772 //Note: "1. Format type PS is legal only if 64-bit floating point operations 773 //are enabled. " 774 0x6: decode FUNCTION_HI { 775 0x0: decode FUNCTION_LO { 776 format Float64Op { 777 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 778 //Lower Halves Independently but we take simulator shortcut 779 Fd.df = Fs.df + Ft.df; 780 }}); 781 782 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 783 //Lower Halves Independently but we take simulator shortcut 784 Fd.df = Fs.df - Ft.df; 785 }}); 786 787 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 788 //Lower Halves Independently but we take simulator shortcut 789 Fd.df = Fs.df * Ft.df; 790 }}); 791 792 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 793 //Lower Halves Independently but we take simulator shortcut 794 Fd.df = fabs(Fs.df); 795 }}); 796 797 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 798 //Lower Halves Independently but we take simulator shortcut 799 //Fd.df = Fs<31:0> | Ft<31:0>; 800 }}); 801 802 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 803 //Lower Halves Independently but we take simulator shortcut 804 Fd.df = -1 * Fs.df; 805 }}); 806 } 807 } 808 809 0x2: decode FUNCTION_LO { 810 0x1: decode MOVCF { 811 format Float64Op { 812 0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}}); 813 0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); 814 } 815 } 816 817 format BasicOp { 818 0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); 819 0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }}); 820 } 821 822 } 823 824 0x4: decode FUNCTION_LO { 825 0x0: Float64Op::cvt_s_pu({{ 826 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 827 Fd.uw = convert_and_round(Fs.ud, PUPPER_TO_SINGLE, rnd_mode); 828 }}); 829 } 830 831 0x5: decode FUNCTION_LO { 832 format Float64Op { 833 0x0: cvt_s_pl({{ 834 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 835 Fd.uw = convert_and_round(Fs.ud, PLOWER_TO_SINGLE, 836 rnd_mode); 837 }}); 838 839 0x4: pll({{ Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<31:0>; }}); 840 0x5: plu({{ Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>;}}); 841 0x6: pul({{ Fd.ud = Fs.ud<63:32> << 32 | Ft.ud<31:0>; }}); 842 0x7: puu({{ Fd.ud = Fs.ud<63:32> << 32 | Ft.ud<63:32>;}}); 843 } 844 } 845 846 0x6: decode FUNCTION_LO { 847 format FloatOp { 848 0x0: c_f_ps({{ ; }}); 849 0x1: c_un_ps({{ ; }}); 850 0x2: c_eq_ps({{ ; }}); 851 0x3: c_ueq_ps({{ ; }}); 852 0x4: c_olt_ps({{ ; }}); 853 0x5: c_ult_ps({{ ; }}); 854 0x6: c_ole_ps({{ ; }}); 855 0x7: c_ule_ps({{ ; }}); 856 } 857 } 858 859 0x7: decode FUNCTION_LO { 860 format FloatOp { 861 0x0: c_sf_ps({{ ; }}); 862 0x1: c_ngle_ps({{ ; }}); 863 0x2: c_seq_ps({{ ; }}); 864 0x3: c_ngl_ps({{ ; }}); 865 0x4: c_lt_ps({{ ; }}); 866 0x5: c_nge_ps({{ ; }}); 867 0x6: c_le_ps({{ ; }}); 868 0x7: c_ngt_ps({{ ; }}); 869 } 870 } 871 872 } 873 } 874 } 875 } 876 877 //Table A-19 MIPS32 COP2 Encoding of rs Field 878 0x2: decode RS_MSB { 879 0x0: decode RS_HI { 880 0x0: decode RS_LO { 881 format WarnUnimpl { 882 0x0: mfc2(); 883 0x2: cfc2(); 884 0x3: mfhc2(); 885 0x4: mtc2(); 886 0x6: ctc2(); 887 0x7: mftc2(); 888 } 889 } 890 891 0x1: decode ND { 892 0x0: decode TF { 893 format WarnUnimpl { 894 0x0: bc2f(); 895 0x1: bc2t(); 896 } 897 } 898 899 0x1: decode TF { 900 format WarnUnimpl { 901 0x0: bc2fl(); 902 0x1: bc2tl(); 903 } 904 } 905 } 906 } 907 } 908 909 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 910 //Note: "COP1X instructions are legal only if 64-bit floating point 911 //operations are enabled." 912 0x3: decode FUNCTION_HI { 913 0x0: decode FUNCTION_LO { 914 format LoadFloatMemory { 915 0x0: lwxc1({{ /*F_t<31:0> = Mem.sf; */}}, {{ EA = Rs + Rt; }}); 916 0x1: ldxc1({{ /*F_t<63:0> = Mem.df;*/ }}, {{ EA = Rs + Rt; }}); 917 0x5: luxc1({{ /*F_t<31:0> = Mem.df; */}}, 918 {{ //Need to make EA<2:0> = 0 919 EA = Rs + Rt; 920 }}); 921 } 922 } 923 924 0x1: decode FUNCTION_LO { 925 format StoreFloatMemory { 926 0x0: swxc1({{ /*Mem.sf = Ft<31:0>; */}},{{ EA = Rs + Rt; }}); 927 0x1: sdxc1({{ /*Mem.df = Ft<63:0> */}}, {{ EA = Rs + Rt; }}); 928 0x5: suxc1({{ /*Mem.df = F_t<63:0>;*/}}, 929 {{ //Need to make sure EA<2:0> = 0 930 EA = Rs + Rt; 931 }}); 932 } 933 934 0x7: WarnUnimpl::prefx(); 935 } 936 937 format FloatOp { 938 0x3: WarnUnimpl::alnv_ps(); 939 940 format BasicOp { 941 0x4: decode FUNCTION_LO { 942 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 943 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 944 0x6: madd_ps({{ 945 //Must Check for Exception Here... Supposed to Operate on Upper and 946 //Lower Halves Independently but we take simulator shortcut 947 Fd.df = (Fs.df * Fs.df) + Fr.df; 948 }}); 949 } 950 951 0x5: decode FUNCTION_LO { 952 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 953 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 954 0x6: msub_ps({{ 955 //Must Check for Exception Here... Supposed to Operate on Upper and 956 //Lower Halves Independently but we take simulator shortcut 957 Fd.df = (Fs.df * Fs.df) - Fr.df; 958 }}); 959 } 960 961 0x6: decode FUNCTION_LO { 962 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 963 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 964 0x6: nmadd_ps({{ 965 //Must Check for Exception Here... Supposed to Operate on Upper and 966 //Lower Halves Independently but we take simulator shortcut 967 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 968 }}); 969 } 970 971 0x7: decode FUNCTION_LO { 972 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 973 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 974 0x6: nmsub_ps({{ 975 //Must Check for Exception Here... Supposed to Operate on Upper and 976 //Lower Halves Independently but we take simulator shortcut 977 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 978 }}); 979 } 980 } 981 } 982 } 983 984 //MIPS obsolete instructions 985 format BranchLikely { 986 0x4: beql({{ cond = (Rs.sw == 0); }}); 987 0x5: bnel({{ cond = (Rs.sw != 0); }}); 988 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 989 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 990 } 991 } 992 993 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 994 995 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 996 0x4: decode FUNCTION_HI { 997 998 0x0: decode FUNCTION_LO { 999 format IntOp { 1000 0x0: madd({{ 1001 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 1002 temp1 = temp1 + (Rs.sw * Rt.sw); 1003 xc->setMiscReg(Hi,temp1<63:32>); 1004 xc->setMiscReg(Lo,temp1<31:0>); 1005 }}); 1006 1007 0x1: maddu({{ 1008 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 1009 temp1 = temp1 + (Rs.uw * Rt.uw); 1010 xc->setMiscReg(Hi,temp1<63:32>); 1011 xc->setMiscReg(Lo,temp1<31:0>); 1012 }}); 1013 1014 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 1015 1016 0x4: msub({{ 1017 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 1018 temp1 = temp1 - (Rs.sw * Rt.sw); 1019 xc->setMiscReg(Hi,temp1<63:32>); 1020 xc->setMiscReg(Lo,temp1<31:0>); 1021 }}); 1022 1023 0x5: msubu({{ 1024 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 1025 temp1 = temp1 - (Rs.uw * Rt.uw); 1026 xc->setMiscReg(Hi,temp1<63:32>); 1027 xc->setMiscReg(Lo,temp1<31:0>); 1028 }}); 1029 } 1030 } 1031 1032 0x4: decode FUNCTION_LO { 1033 format BasicOp { 1034 0x0: clz({{ 1035 /*int cnt = 0; 1036 int idx = 0; 1037 while ( Rs.uw<idx> != 1) { 1038 cnt++; 1039 idx--; 1040 } 1041 1042 Rd.uw = cnt;*/ 1043 }}); 1044 1045 0x1: clo({{ 1046 /*int cnt = 0; 1047 int idx = 0; 1048 while ( Rs.uw<idx> != 0) { 1049 cnt++; 1050 idx--; 1051 } 1052 1053 Rd.uw = cnt;*/ 1054 }}); 1055 } 1056 } 1057 1058 0x7: decode FUNCTION_LO { 1059 0x7: WarnUnimpl::sdbbp(); 1060 } 1061 } 1062 1063 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 1064 0x7: decode FUNCTION_HI { 1065 1066 0x0: decode FUNCTION_LO { 1067 format FailUnimpl { 1068 0x1: ext(); 1069 0x4: ins(); 1070 } 1071 } 1072 1073 0x1: decode FUNCTION_LO { 1074 format FailUnimpl { 1075 0x0: fork(); 1076 0x1: yield(); 1077 } 1078 } 1079 1080 1081 //Table A-10 MIPS32 BSHFL Encoding of sa Field 1082 0x4: decode SA { 1083 1084 0x02: FailUnimpl::wsbh(); 1085 1086 format BasicOp { 1087 0x10: seb({{ Rd.sw = Rt<7:0>}}); 1088 0x18: seh({{ Rd.sw = Rt<15:0>}}); 1089 } 1090 } 1091 1092 0x6: decode FUNCTION_LO { 1093 0x7: FailUnimpl::rdhwr();//{{ /*Rt = xc->hwRegs[RD];*/ }} 1094 } 1095 } 1096 } 1097 1098 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 1099 format LoadMemory { 1100 0x0: lb({{ Rt.sw = Mem.sb; }}); 1101 0x1: lh({{ Rt.sw = Mem.sh; }}); 1102 1103 0x2: lwl({{ 1104 uint32_t mem_word = Mem.uw; 1105 uint32_t unalign_addr = Rs + disp; 1106 uint32_t offset = unalign_addr & 0x00000003; 1107#if BYTE_ORDER == BIG_ENDIAN 1108 switch(offset) 1109 { 1110 case 0: 1111 Rt = mem_word; 1112 break; 1113 1114 case 1: 1115 Rt &= 0x000F; 1116 Rt |= (mem_word << 4); 1117 break; 1118 1119 case 2: 1120 Rt &= 0x00FF; 1121 Rt |= (mem_word << 8); 1122 break; 1123 1124 case 3: 1125 Rt &= 0x0FFF; 1126 Rt |= (mem_word << 12); 1127 break; 1128 1129 default: 1130 panic("lwl: bad offset"); 1131 } 1132#elif BYTE_ORDER == LITTLE_ENDIAN 1133 switch(offset) 1134 { 1135 case 0: 1136 Rt &= 0x0FFF; 1137 Rt |= (mem_word << 12); 1138 break; 1139 1140 case 1: 1141 Rt &= 0x00FF; 1142 Rt |= (mem_word << 8); 1143 break; 1144 1145 case 2: 1146 Rt &= 0x000F; 1147 Rt |= (mem_word << 4); 1148 break; 1149 1150 case 3: 1151 Rt = mem_word; 1152 break; 1153 1154 default: 1155 panic("lwl: bad offset"); 1156 } 1157#endif 1158 }}, {{ EA = (Rs + disp) & ~3; }}); 1159 1160 0x3: lw({{ Rt.sw = Mem.sw; }}); 1161 0x4: lbu({{ Rt.uw = Mem.ub; }}); 1162 0x5: lhu({{ Rt.uw = Mem.uh; }}); 1163 0x6: lwr({{ 1164 uint32_t mem_word = Mem.uw; 1165 uint32_t unalign_addr = Rs + disp; 1166 uint32_t offset = unalign_addr & 0x00000003; 1167 1168#if BYTE_ORDER == BIG_ENDIAN 1169 switch(offset) 1170 { 1171 case 0: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; 1172 case 1: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; 1173 case 2: Rt &= 0xF000; Rt |= (mem_word >> 4); break; 1174 case 3: Rt = mem_word; break; 1175 default: panic("lwr: bad offset"); 1176 } 1177#elif BYTE_ORDER == LITTLE_ENDIAN 1178 switch(offset) 1179 { 1180 case 0: Rt = mem_word; break; 1181 case 1: Rt &= 0xF000; Rt |= (mem_word >> 4); break; 1182 case 2: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; 1183 case 3: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; 1184 default: panic("lwr: bad offset"); 1185 } 1186#endif 1187 }}, 1188 {{ EA = (Rs + disp) & ~3; }}); 1189 } 1190 1191 0x7: FailUnimpl::reserved(); 1192 } 1193 1194 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 1195 format StoreMemory { 1196 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 1197 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 1198 0x2: swl({{ 1199 uint32_t mem_word = 0; 1200 uint32_t aligned_addr = (Rs + disp) & ~3; 1201 uint32_t unalign_addr = Rs + disp; 1202 uint32_t offset = unalign_addr & 0x00000003; 1203 1204 DPRINTF(IEW,"Execute: aligned=0x%x unaligned=0x%x\n offset=0x%x", 1205 aligned_addr,unalign_addr,offset); 1206 1207 fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); 1208 1209#if BYTE_ORDER == BIG_ENDIAN 1210 switch(offset) 1211 { 1212 case 0: 1213 Mem = Rt; 1214 break; 1215 1216 case 1: 1217 mem_word &= 0xF000; 1218 mem_word |= (Rt >> 4); 1219 Mem = mem_word; 1220 break; 1221 1222 case 2: 1223 mem_word &= 0xFF00; 1224 mem_word |= (Rt >> 8); 1225 Mem = mem_word; 1226 break; 1227 1228 case 3: 1229 mem_word &= 0xFFF0; 1230 mem_word |= (Rt >> 12); 1231 Mem = mem_word; 1232 break; 1233 1234 default: 1235 panic("swl: bad offset"); 1236 } 1237#elif BYTE_ORDER == LITTLE_ENDIAN 1238 switch(offset) 1239 { 1240 case 0: 1241 mem_word &= 0xFFF0; 1242 mem_word |= (Rt >> 12); 1243 Mem = mem_word; 1244 break; 1245 1246 case 1: 1247 mem_word &= 0xFF00; 1248 mem_word |= (Rt >> 8); 1249 Mem = mem_word; 1250 break; 1251 1252 case 2: 1253 mem_word &= 0xF000; 1254 mem_word |= (Rt >> 4); 1255 Mem = mem_word; 1256 break; 1257 1258 case 3: 1259 Mem = Rt; 1260 break; 1261 1262 default: 1263 panic("swl: bad offset"); 1264 } 1265#endif 1266 }},{{ EA = (Rs + disp) & ~3; }},mem_flags = NO_ALIGN_FAULT); 1267 1268 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 1269 1270 0x6: swr({{ 1271 uint32_t mem_word = 0; 1272 uint32_t aligned_addr = (Rs + disp) & ~3; 1273 uint32_t unalign_addr = Rs + disp; 1274 uint32_t offset = unalign_addr & 0x00000003; 1275 1276 fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); 1277 1278#if BYTE_ORDER == BIG_ENDIAN 1279 switch(offset) 1280 { 1281 case 0: 1282 mem_word &= 0x0FFF; 1283 mem_word |= (Rt << 12); 1284 Mem = mem_word; 1285 break; 1286 1287 case 1: 1288 mem_word &= 0x00FF; 1289 mem_word |= (Rt << 8); 1290 Mem = mem_word; 1291 break; 1292 1293 case 2: 1294 mem_word &= 0x000F; 1295 mem_word |= (Rt << 4); 1296 Mem = mem_word; 1297 break; 1298 1299 case 3: 1300 Mem = Rt; 1301 break; 1302 1303 default: 1304 panic("swr: bad offset"); 1305 } 1306#elif BYTE_ORDER == LITTLE_ENDIAN 1307 switch(offset) 1308 { 1309 case 0: 1310 Mem = Rt; 1311 break; 1312 1313 case 1: 1314 mem_word &= 0x000F; 1315 mem_word |= (Rt << 4); 1316 Mem = mem_word; 1317 break; 1318 1319 case 2: 1320 mem_word &= 0x00FF; 1321 mem_word |= (Rt << 8); 1322 Mem = mem_word; 1323 break; 1324 1325 case 3: 1326 mem_word &= 0x0FFF; 1327 mem_word |= (Rt << 12); 1328 Mem = mem_word; 1329 break; 1330 1331 default: 1332 panic("swr: bad offset"); 1333 } 1334#endif 1335 }},{{ EA = (Rs + disp) & ~3;}},mem_flags = NO_ALIGN_FAULT); 1336 } 1337 1338 format WarnUnimpl { 1339 0x7: cache(); 1340 } 1341 1342 } 1343 1344 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 1345 0x0: LoadMemory::ll({{Rt.uw = Mem.uw}},mem_flags=LOCKED); 1346 1347 format LoadFloatMemory { 1348 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 1349 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 1350 } 1351 } 1352 1353 1354 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 1355 0x0: StoreMemory::sc({{ Mem.uw = Rt.uw; Rt.uw = 1; }}); 1356 1357 format StoreFloatMemory { 1358 0x1: swc1({{ Mem.uw = Ft.uw; }}); 1359 0x5: sdc1({{ Mem.ud = Ft.ud; }}); 1360 } 1361 } 1362} 1363 1364 1365