decoder.isa revision 2601
1// -*- mode:c++ -*- 2 3//////////////////////////////////////////////////////////////////// 4// 5// The actual MIPS32 ISA decoder 6// ----------------------------- 7// The following instructions are specified in the MIPS32 ISA 8// Specification. Decoding closely follows the style specified 9// in the MIPS32 ISAthe specification document starting with Table 10// A-2 (document available @ www.mips.com) 11// 12//@todo: Distinguish "unknown/future" use insts from "reserved" 13// ones 14decode OPCODE_HI default Unknown::unknown() { 15 16 // Derived From ... Table A-2 MIPS32 ISA Manual 17 0x0: decode OPCODE_LO { 18 19 0x0: decode FUNCTION_HI { 20 0x0: decode FUNCTION_LO { 21 0x1: decode MOVCI { 22 format BasicOp { 23 0: movf({{ if (xc->readMiscReg(FPCR) != CC) Rd = Rs}}); 24 1: movt({{ if (xc->readMiscReg(FPCR) == CC) Rd = Rs}}); 25 } 26 } 27 28 format BasicOp { 29 30 //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 31 //are used to distinguish among the SLL, NOP, SSNOP and EHB functions. 32 0x0: decode RS { 33 0x0: decode RT { //fix Nop traditional vs. Nop converted disassembly later 34 0x0: decode RD default Nop::nop(){ 35 0x0: decode SA { 36 0x1: ssnop({{ ; }}); //really sll r0,r0,1 37 0x3: ehb({{ ; }}); //really sll r0,r0,3 38 } 39 } 40 41 default: sll({{ Rd = Rt.uw << SA; }}); 42 } 43 44 } 45 46 0x2: decode RS_SRL { 47 0x0:decode SRL { 48 0: srl({{ Rd = Rt.uw >> SA; }}); 49 50 //Hardcoded assuming 32-bit ISA, probably need parameter here 51 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 52 } 53 } 54 55 0x3: decode RS { 56 0x0: sra({{ 57 uint32_t temp = Rt >> SA; 58 59 if ( (Rt & 0x80000000) > 0 ) { 60 uint32_t mask = 0x80000000; 61 for(int i=0; i < SA; i++) { 62 temp |= mask; 63 mask = mask >> 1; 64 } 65 } 66 67 Rd = temp; 68 }}); 69 } 70 71 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 72 73 0x6: decode SRLV { 74 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 75 76 //Hardcoded assuming 32-bit ISA, probably need parameter here 77 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 78 } 79 80 0x7: srav({{ 81 int shift_amt = Rs<4:0>; 82 83 uint32_t temp = Rt >> shift_amt; 84 85 if ( (Rt & 0x80000000) > 0 ) { 86 uint32_t mask = 0x80000000; 87 for(int i=0; i < shift_amt; i++) { 88 temp |= mask; 89 mask = mask >> 1; 90 } 91 } 92 93 Rd = temp; 94 }}); 95 } 96 } 97 98 0x1: decode FUNCTION_LO { 99 100 //Table A-3 Note: "Specific encodings of the hint field are used 101 //to distinguish JR from JR.HB and JALR from JALR.HB" 102 format Jump { 103 0x0: decode HINT { 104 0:jr({{ NNPC = Rs & ~1; }},IsReturn); 105 106 1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn); 107 } 108 109 0x1: decode HINT { 110 0: jalr({{ Rd = NNPC; NNPC = Rs; }},IsCall,IsReturn); 111 112 1: jalr_hb({{ Rd = NNPC; NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn); 113 } 114 } 115 116 format BasicOp { 117 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 118 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 119 } 120 121 format BasicOp { 122 0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative); 123 0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative); 124 0x7: sync({{ panic("Not implemented sync yet"); }},IsNonSpeculative); 125 } 126 } 127 128 0x2: decode FUNCTION_LO { 129 format BasicOp { 130 0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }}); 131 0x1: mthi({{ xc->setMiscReg(Hi,Rs); }}); 132 0x2: mflo({{ Rd = xc->readMiscReg(Lo); }}); 133 0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }}); 134 } 135 } 136 137 0x3: decode FUNCTION_LO { 138 format IntOp { 139 0x0: mult({{ 140 int64_t temp1 = Rs.sd * Rt.sd; 141 xc->setMiscReg(Hi,temp1<63:32>); 142 xc->setMiscReg(Lo,temp1<31:0>); 143 }}); 144 145 0x1: multu({{ 146 uint64_t temp1 = Rs.ud * Rt.ud; 147 xc->setMiscReg(Hi,temp1<63:32>); 148 xc->setMiscReg(Lo,temp1<31:0>); 149 }}); 150 151 0x2: div({{ 152 xc->setMiscReg(Hi,Rs.sd % Rt.sd); 153 xc->setMiscReg(Lo,Rs.sd / Rt.sd); 154 }}); 155 156 0x3: divu({{ 157 xc->setMiscReg(Hi,Rs.ud % Rt.ud); 158 xc->setMiscReg(Lo,Rs.ud / Rt.ud); 159 }}); 160 } 161 } 162 163 0x4: decode HINT { 164 0x0: decode FUNCTION_LO { 165 format IntOp { 166 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}}); 167 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 168 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}}); 169 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 170 0x4: and({{ Rd = Rs & Rt;}}); 171 0x5: or({{ Rd = Rs | Rt;}}); 172 0x6: xor({{ Rd = Rs ^ Rt;}}); 173 0x7: nor({{ Rd = ~(Rs | Rt);}}); 174 } 175 } 176 } 177 178 0x5: decode HINT { 179 0x0: decode FUNCTION_LO { 180 format IntOp{ 181 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 182 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 183 } 184 } 185 } 186 187 0x6: decode FUNCTION_LO { 188 format Trap { 189 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 190 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 191 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 192 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 193 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 194 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 195 } 196 } 197 } 198 199 0x1: decode REGIMM_HI { 200 0x0: decode REGIMM_LO { 201 format Branch { 202 0x0: bltz({{ cond = (Rs.sw < 0); }}); 203 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 204 } 205 206 format BranchLikely { 207 //MIPS obsolete instructions 208 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 209 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 210 } 211 } 212 213 0x1: decode REGIMM_LO { 214 format Trap { 215 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 216 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 217 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 218 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 219 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 220 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 221 } 222 } 223 224 0x2: decode REGIMM_LO { 225 format Branch { 226 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn); 227 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn); 228 } 229 230 format BranchLikely { 231 //Will be removed in future MIPS releases 232 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn); 233 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn); 234 } 235 } 236 237 0x3: decode REGIMM_LO { 238 format WarnUnimpl { 239 0x7: synci(); 240 } 241 } 242 } 243 244 format Jump { 245 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 246 247 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn); 248 } 249 250 format Branch { 251 0x4: beq({{ cond = (Rs.sw == Rt.sw); }}); 252 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 253 0x6: decode RT { 254 0x0: blez({{ cond = (Rs.sw <= 0); }}); 255 } 256 257 0x7: decode RT { 258 0x0: bgtz({{ cond = (Rs.sw > 0); }}); 259 } 260 } 261 } 262 263 0x1: decode OPCODE_LO { 264 format IntOp { 265 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}}); 266 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 267 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 268 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); 269 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 270 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 271 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); 272 273 0x7: decode RS { 274 0x0: lui({{ Rt = imm << 16}}); 275 } 276 } 277 } 278 279 0x2: decode OPCODE_LO { 280 281 //Table A-11 MIPS32 COP0 Encoding of rs Field 282 0x0: decode RS_MSB { 283 0x0: decode RS { 284 format System { 285 0x0: mfc0({{ 286 //uint64_t reg_num = Rd.uw; 287 288 Rt = xc->readMiscReg(RD << 5 | SEL); 289 }}); 290 291 0x4: mtc0({{ 292 //uint64_t reg_num = Rd.uw; 293 294 xc->setMiscReg(RD << 5 | SEL,Rt); 295 }}); 296 297 0x8: mftr({{ 298 //The contents of the coprocessor 0 register specified by the 299 //combination of rd and sel are loaded into general register 300 //rt. Note that not all coprocessor 0 registers support the 301 //sel field. In those instances, the sel field must be zero. 302 303 //MT Code Needed Here 304 }}); 305 306 0xC: mttr({{ 307 //The contents of the coprocessor 0 register specified by the 308 //combination of rd and sel are loaded into general register 309 //rt. Note that not all coprocessor 0 registers support the 310 //sel field. In those instances, the sel field must be zero. 311 312 //MT Code Needed Here 313 }}); 314 315 316 0xA: rdpgpr({{ 317 //Accessing Previous Shadow Set Register Number 318 //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/; 319 //uint64_t reg_num = Rt.uw; 320 321 //Rd = xc->regs.IntRegFile[prev]; 322 //Rd = xc->shadowIntRegFile[prev][reg_num]; 323 }}); 324 325 0xB: decode RD { 326 327 0x0: decode SC { 328 0x0: dvpe({{ 329 Rt.sw = xc->readMiscReg(MVPControl); 330 xc->setMiscReg(MVPControl,0); 331 }}); 332 333 0x1: evpe({{ 334 Rt.sw = xc->readMiscReg(MVPControl); 335 xc->setMiscReg(MVPControl,1); 336 }}); 337 } 338 339 0x1: decode SC { 340 0x0: dmt({{ 341 Rt.sw = xc->readMiscReg(VPEControl); 342 xc->setMiscReg(VPEControl,0); 343 }}); 344 345 0x1: emt({{ 346 Rt.sw = xc->readMiscReg(VPEControl); 347 xc->setMiscReg(VPEControl,1); 348 }}); 349 } 350 351 0xC: decode SC { 352 0x0: di({{ 353 Rt.sw = xc->readMiscReg(Status); 354 xc->setMiscReg(Status,0); 355 }}); 356 357 0x1: ei({{ 358 Rt.sw = xc->readMiscReg(Status); 359 xc->setMiscReg(Status,1); 360 }}); 361 } 362 } 363 364 0xE: wrpgpr({{ 365 //Accessing Previous Shadow Set Register Number 366 //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/); 367 //uint64_t reg_num = Rd.uw; 368 369 //xc->regs.IntRegFile[prev]; 370 //xc->shadowIntRegFile[prev][reg_num] = Rt; 371 }}); 372 } 373 } 374 375 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 376 0x1: decode FUNCTION { 377 format System { 378 0x01: tlbr({{ }}); 379 0x02: tlbwi({{ }}); 380 0x06: tlbwr({{ }}); 381 0x08: tlbp({{ }}); 382 } 383 384 format WarnUnimpl { 385 0x18: eret(); 386 0x1F: deret(); 387 0x20: wait(); 388 } 389 } 390 } 391 392 //Table A-13 MIPS32 COP1 Encoding of rs Field 393 0x1: decode RS_MSB { 394 395 0x0: decode RS_HI { 396 0x0: decode RS_LO { 397 format FloatOp { 398 0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }}); 399 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); 400 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); 401 0x7: mthc1({{ 402 uint64_t fs_hi = Rt.ud << 32; 403 uint64_t fs_lo = Fs.ud & 0x0000FFFF; 404 Fs.ud = fs_hi & fs_lo; 405 }}); 406 } 407 408 format System { 409 0x2: cfc1({{ 410 uint32_t fcsr_reg = xc->readMiscReg(FCSR); 411 412 switch (FS) 413 { 414 case 0: 415 Rt = xc->readMiscReg(FIR); 416 break; 417 case 25: 418 Rt = 0 | (fcsr_reg & 0xFE000000) >> 24 | (fcsr_reg & 0x00800000) >> 23; 419 break; 420 case 26: 421 Rt = 0 | (fcsr_reg & 0x0003F07C); 422 break; 423 case 28: 424 Rt = 0 | (fcsr_reg); 425 break; 426 case 31: 427 Rt = fcsr_reg; 428 break; 429 default: 430 panic("FP Control Value (%d) Not Available. Ignoring Access to" 431 "Floating Control Status Register",fcsr_reg); 432 } 433 }}); 434 435 0x6: ctc1({{ 436 uint32_t fcsr_reg = xc->readMiscReg(FCSR); 437 uint32_t temp; 438 439 switch (FS) 440 { 441 case 25: 442 temp = 0 | (Rt.uw<7:1> << 25) // move 31...25 443 | (fcsr_reg & 0x01000000) // bit 24 444 | (fcsr_reg & 0x004FFFFF);// bit 22...0 445 break; 446 447 case 26: 448 temp = 0 | (fcsr_reg & 0xFFFC0000) // move 31...18 449 | Rt.uw<17:12> << 12 // bit 17...12 450 | (fcsr_reg & 0x00000F80) << 7// bit 11...7 451 | Rt.uw<6:2> << 2 // bit 6...2 452 | (fcsr_reg & 0x00000002); // bit 1...0 453 break; 454 455 case 28: 456 temp = 0 | (fcsr_reg & 0xFE000000) // move 31...25 457 | Rt.uw<2:2> << 24 // bit 24 458 | (fcsr_reg & 0x00FFF000) << 23// bit 23...12 459 | Rt.uw<11:7> << 7 // bit 24 460 | (fcsr_reg & 0x000007E) 461 | Rt.uw<1:0>;// bit 22...0 462 break; 463 464 case 31: 465 temp = Rt.uw; 466 break; 467 468 default: 469 panic("FP Control Value (%d) Not Available. Ignoring Access to" 470 "Floating Control Status Register",fcsr_reg); 471 } 472 473 xc->setMiscReg(FCSR,temp); 474 }}); 475 } 476 } 477 478 0x1: decode ND { 479 0x0: decode TF { 480 format Branch { 481 0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 482 0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 483 } 484 } 485 486 0x1: decode TF { 487 format BranchLikely { 488 0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 489 0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 490 } 491 } 492 } 493 } 494 495 0x1: decode RS_HI { 496 0x2: decode RS_LO { 497 498 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 499 //(( single-word )) 500 0x0: decode FUNCTION_HI { 501 0x0: decode FUNCTION_LO { 502 format FloatOp { 503 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); 504 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); 505 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); 506 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); 507 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); 508 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); 509 0x6: mov_s({{ Fd.sf = Fs.sf;}}); 510 0x7: neg_s({{ Fd.sf = -1 * Fs.sf;}}); 511 } 512 } 513 514 0x1: decode FUNCTION_LO { 515 format Float64Op { 516 0x0: round_l_s({{ 517 Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_LONG, RND_NEAREST); 518 }}); 519 520 0x1: trunc_l_s({{ 521 Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_LONG, RND_ZERO); 522 }}); 523 524 0x2: ceil_l_s({{ 525 Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_LONG, RND_UP); 526 }}); 527 528 0x3: floor_l_s({{ 529 Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_LONG, RND_DOWN); 530 }}); 531 } 532 533 format FloatOp { 534 0x4: round_w_s({{ 535 Fd.uw = convert_and_round(Fs.sf, SINGLE_TO_WORD, RND_NEAREST); 536 }}); 537 538 0x5: trunc_w_s({{ 539 Fd.uw = convert_and_round(Fs.sf, SINGLE_TO_WORD, RND_ZERO); 540 }}); 541 542 0x6: ceil_w_s({{ 543 Fd.uw = convert_and_round(Fs.sf, SINGLE_TO_WORD, RND_UP); 544 }}); 545 546 0x7: floor_w_s({{ 547 Fd.uw = convert_and_round(Fs.sf, SINGLE_TO_WORD, RND_DOWN); 548 }}); 549 } 550 } 551 552 0x2: decode FUNCTION_LO { 553 0x1: decode MOVCF { 554 format FloatOp { 555 0x0: movfs({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); 556 0x1: movts({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); 557 } 558 } 559 560 format BasicOp { 561 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 562 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); 563 } 564 565 format Float64Op { 566 0x5: recips({{ Fd = 1 / Fs; }}); 567 0x6: rsqrts({{ Fd = 1 / sqrt((double)Fs.ud);}}); 568 } 569 } 570 571 0x4: decode FUNCTION_LO { 572 573 format FloatOp { 574 0x1: cvt_d_s({{ 575 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 576 Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_DOUBLE, rnd_mode); 577 }}); 578 579 0x4: cvt_w_s({{ 580 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 581 Fd.uw = convert_and_round(Fs.sf, SINGLE_TO_WORD, rnd_mode); 582 }}); 583 } 584 585 //only legal for 64 bit 586 format Float64Op { 587 0x5: cvt_l_s({{ 588 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 589 Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_LONG, rnd_mode); 590 }}); 591 592 0x6: cvt_ps_st({{ 593 Fd.ud = (uint64_t)Fs.uw << 32 | (uint64_t)Ft.uw; 594 }}); 595 } 596 } 597 } 598 599 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 600 0x1: decode FUNCTION_HI { 601 0x0: decode FUNCTION_LO { 602 format FloatOp { 603 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 604 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 605 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 606 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 607 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 608 0x5: absd({{ Fd.df = fabs(Fs.df);}}); 609 0x6: movd({{ Fd.ud = Fs.ud;}}); 610 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 611 } 612 } 613 614 0x1: decode FUNCTION_LO { 615 format Float64Op { 616 0x0: round_l_d({{ 617 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_NEAREST); 618 }}); 619 620 0x1: trunc_l_d({{ 621 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_ZERO); 622 }}); 623 624 0x2: ceil_l_d({{ 625 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_UP); 626 }}); 627 628 0x3: floor_l_d({{ 629 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_DOWN); 630 }}); 631 } 632 633 format FloatOp { 634 0x4: round_w_d({{ 635 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_NEAREST); 636 }}); 637 638 0x5: trunc_w_d({{ 639 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_ZERO); 640 }}); 641 642 0x6: ceil_w_d({{ 643 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_UP); 644 }}); 645 646 0x7: floor_w_d({{ 647 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_DOWN); 648 }}); 649 } 650 } 651 652 0x2: decode FUNCTION_LO { 653 0x1: decode MOVCF { 654 format FloatOp { 655 0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }}); 656 0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }}); 657 } 658 } 659 660 format BasicOp { 661 0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }}); 662 0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }}); 663 } 664 665 format Float64Op { 666 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 667 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 668 } 669 } 670 671 0x4: decode FUNCTION_LO { 672 format FloatOp { 673 0x0: cvt_s_d({{ 674 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 675 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_SINGLE, rnd_mode); 676 }}); 677 678 0x4: cvt_w_d({{ 679 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 680 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, rnd_mode); 681 }}); 682 } 683 684 //only legal for 64 bit 685 format Float64Op { 686 0x5: cvt_l_d({{ 687 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 688 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, rnd_mode); 689 }}); 690 } 691 } 692 } 693 694 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 695 0x4: decode FUNCTION { 696 format FloatOp { 697 0x20: cvt_s_w({{ 698 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 699 Fd.uw = convert_and_round(Fs.sf, WORD_TO_SINGLE, rnd_mode); 700 }}); 701 702 0x21: cvt_d_w({{ 703 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 704 Fd.ud = convert_and_round(Fs.sf, WORD_TO_DOUBLE, rnd_mode); 705 }}); 706 } 707 } 708 709 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 710 //Note: "1. Format type L is legal only if 64-bit floating point operations 711 //are enabled." 712 0x5: decode FUNCTION_HI { 713 format Float64Op { 714 0x10: cvt_s_l({{ 715 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 716 Fd.uw = convert_and_round(Fs.ud, LONG_TO_SINGLE, rnd_mode); 717 }}); 718 719 0x11: cvt_d_l({{ 720 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 721 Fd.ud = convert_and_round(Fs.ud, LONG_TO_DOUBLE, rnd_mode); 722 }}); 723 } 724 } 725 726 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 727 //Note: "1. Format type PS is legal only if 64-bit floating point operations 728 //are enabled. " 729 0x6: decode FUNCTION_HI { 730 0x0: decode FUNCTION_LO { 731 format Float64Op { 732 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 733 //Lower Halves Independently but we take simulator shortcut 734 Fd.df = Fs.df + Ft.df; 735 }}); 736 737 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 738 //Lower Halves Independently but we take simulator shortcut 739 Fd.df = Fs.df - Ft.df; 740 }}); 741 742 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 743 //Lower Halves Independently but we take simulator shortcut 744 Fd.df = Fs.df * Ft.df; 745 }}); 746 747 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 748 //Lower Halves Independently but we take simulator shortcut 749 Fd.df = fabs(Fs.df); 750 }}); 751 752 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 753 //Lower Halves Independently but we take simulator shortcut 754 //Fd.df = Fs<31:0> | Ft<31:0>; 755 }}); 756 757 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 758 //Lower Halves Independently but we take simulator shortcut 759 Fd.df = -1 * Fs.df; 760 }}); 761 } 762 } 763 764 0x2: decode FUNCTION_LO { 765 0x1: decode MOVCF { 766 format Float64Op { 767 0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}}); 768 0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); 769 } 770 } 771 772 format BasicOp { 773 0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); 774 0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }}); 775 } 776 777 } 778 779 0x4: decode FUNCTION_LO { 780 0x0: Float64Op::cvt_s_pu({{ 781 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 782 Fd.uw = convert_and_round(Fs.ud, PUPPER_TO_SINGLE, rnd_mode); 783 }}); 784 } 785 786 0x5: decode FUNCTION_LO { 787 format Float64Op { 788 0x0: cvt_s_pl({{ 789 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 790 Fd.uw = convert_and_round(Fs.ud, PLOWER_TO_SINGLE, 791 rnd_mode); 792 }}); 793 794 0x4: pll({{ Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<31:0>; }}); 795 0x5: plu({{ Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>;}}); 796 0x6: pul({{ Fd.ud = Fs.ud<63:32> << 32 | Ft.ud<31:0>; }}); 797 0x7: puu({{ Fd.ud = Fs.ud<63:32> << 32 | Ft.ud<63:32>;}}); 798 } 799 } 800 } 801 } 802 } 803 } 804 805 //Table A-19 MIPS32 COP2 Encoding of rs Field 806 0x2: decode RS_MSB { 807 0x0: decode RS_HI { 808 0x0: decode RS_LO { 809 format WarnUnimpl { 810 0x0: mfc2(); 811 0x2: cfc2(); 812 0x3: mfhc2(); 813 0x4: mtc2(); 814 0x6: ctc2(); 815 0x7: mftc2(); 816 } 817 } 818 819 0x1: decode ND { 820 0x0: decode TF { 821 format WarnUnimpl { 822 0x0: bc2f(); 823 0x1: bc2t(); 824 } 825 } 826 827 0x1: decode TF { 828 format WarnUnimpl { 829 0x0: bc2fl(); 830 0x1: bc2tl(); 831 } 832 } 833 } 834 } 835 } 836 837 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 838 //Note: "COP1X instructions are legal only if 64-bit floating point 839 //operations are enabled." 840 0x3: decode FUNCTION_HI { 841 0x0: decode FUNCTION_LO { 842 format LoadFloatMemory { 843 0x0: lwxc1({{ /*F_t<31:0> = Mem.sf; */}}, {{ EA = Rs + Rt; }}); 844 0x1: ldxc1({{ /*F_t<63:0> = Mem.df;*/ }}, {{ EA = Rs + Rt; }}); 845 0x5: luxc1({{ /*F_t<31:0> = Mem.df; */}}, 846 {{ //Need to make EA<2:0> = 0 847 EA = Rs + Rt; 848 }}); 849 } 850 } 851 852 0x1: decode FUNCTION_LO { 853 format StoreFloatMemory { 854 0x0: swxc1({{ /*Mem.sf = Ft<31:0>; */}},{{ EA = Rs + Rt; }}); 855 0x1: sdxc1({{ /*Mem.df = Ft<63:0> */}}, {{ EA = Rs + Rt; }}); 856 0x5: suxc1({{ /*Mem.df = F_t<63:0>;*/}}, 857 {{ //Need to make sure EA<2:0> = 0 858 EA = Rs + Rt; 859 }}); 860 } 861 862 0x7: WarnUnimpl::prefx(); 863 } 864 865 format FloatOp { 866 0x3: WarnUnimpl::alnv_ps(); 867 868 format BasicOp { 869 0x4: decode FUNCTION_LO { 870 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 871 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 872 0x6: madd_ps({{ 873 //Must Check for Exception Here... Supposed to Operate on Upper and 874 //Lower Halves Independently but we take simulator shortcut 875 Fd.df = (Fs.df * Fs.df) + Fr.df; 876 }}); 877 } 878 879 0x5: decode FUNCTION_LO { 880 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 881 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 882 0x6: msub_ps({{ 883 //Must Check for Exception Here... Supposed to Operate on Upper and 884 //Lower Halves Independently but we take simulator shortcut 885 Fd.df = (Fs.df * Fs.df) - Fr.df; 886 }}); 887 } 888 889 0x6: decode FUNCTION_LO { 890 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 891 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 892 0x6: nmadd_ps({{ 893 //Must Check for Exception Here... Supposed to Operate on Upper and 894 //Lower Halves Independently but we take simulator shortcut 895 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 896 }}); 897 } 898 899 0x7: decode FUNCTION_LO { 900 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 901 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 902 0x6: nmsub_ps({{ 903 //Must Check for Exception Here... Supposed to Operate on Upper and 904 //Lower Halves Independently but we take simulator shortcut 905 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 906 }}); 907 } 908 } 909 } 910 } 911 912 //MIPS obsolete instructions 913 format BranchLikely { 914 0x4: beql({{ cond = (Rs.sw == 0); }}); 915 0x5: bnel({{ cond = (Rs.sw != 0); }}); 916 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 917 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 918 } 919 } 920 921 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 922 923 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 924 0x4: decode FUNCTION_HI { 925 926 0x0: decode FUNCTION_LO { 927 format IntOp { 928 0x0: madd({{ 929 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 930 temp1 = temp1 + (Rs.sw * Rt.sw); 931 xc->setMiscReg(Hi,temp1<63:32>); 932 xc->setMiscReg(Lo,temp1<31:0>); 933 }}); 934 935 0x1: maddu({{ 936 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 937 temp1 = temp1 + (Rs.uw * Rt.uw); 938 xc->setMiscReg(Hi,temp1<63:32>); 939 xc->setMiscReg(Lo,temp1<31:0>); 940 }}); 941 942 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 943 944 0x4: msub({{ 945 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 946 temp1 = temp1 - (Rs.sw * Rt.sw); 947 xc->setMiscReg(Hi,temp1<63:32>); 948 xc->setMiscReg(Lo,temp1<31:0>); 949 }}); 950 951 0x5: msubu({{ 952 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 953 temp1 = temp1 - (Rs.uw * Rt.uw); 954 xc->setMiscReg(Hi,temp1<63:32>); 955 xc->setMiscReg(Lo,temp1<31:0>); 956 }}); 957 } 958 } 959 960 0x4: decode FUNCTION_LO { 961 format BasicOp { 962 0x0: clz({{ 963 /*int cnt = 0; 964 int idx = 0; 965 while ( Rs.uw<idx> != 1) { 966 cnt++; 967 idx--; 968 } 969 970 Rd.uw = cnt;*/ 971 }}); 972 973 0x1: clo({{ 974 /*int cnt = 0; 975 int idx = 0; 976 while ( Rs.uw<idx> != 0) { 977 cnt++; 978 idx--; 979 } 980 981 Rd.uw = cnt;*/ 982 }}); 983 } 984 } 985 986 0x7: decode FUNCTION_LO { 987 0x7: WarnUnimpl::sdbbp(); 988 } 989 } 990 991 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 992 0x7: decode FUNCTION_HI { 993 994 0x0: decode FUNCTION_LO { 995 format FailUnimpl { 996 0x1: ext(); 997 0x4: ins(); 998 } 999 } 1000 1001 0x1: decode FUNCTION_LO { 1002 format FailUnimpl { 1003 0x0: fork(); 1004 0x1: yield(); 1005 } 1006 } 1007 1008 1009 //Table A-10 MIPS32 BSHFL Encoding of sa Field 1010 0x4: decode SA { 1011 1012 0x02: FailUnimpl::wsbh(); 1013 1014 format BasicOp { 1015 0x10: seb({{ Rd.sw = Rt<7:0>}}); 1016 0x18: seh({{ Rd.sw = Rt<15:0>}}); 1017 } 1018 } 1019 1020 0x6: decode FUNCTION_LO { 1021 0x7: FailUnimpl::rdhwr();//{{ /*Rt = xc->hwRegs[RD];*/ }} 1022 } 1023 } 1024 } 1025 1026 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 1027 format LoadMemory { 1028 0x0: lb({{ Rt.sw = Mem.sb; }}); 1029 0x1: lh({{ Rt.sw = Mem.sh; }}); 1030 1031 0x2: lwl({{ 1032 uint32_t mem_word = Mem.uw; 1033 uint32_t unalign_addr = Rs + disp; 1034 uint32_t offset = unalign_addr & 0x00000003; 1035#if BYTE_ORDER == BIG_ENDIAN 1036 switch(offset) 1037 { 1038 case 0: 1039 Rt = mem_word; 1040 break; 1041 1042 case 1: 1043 Rt &= 0x000F; 1044 Rt |= (mem_word << 4); 1045 break; 1046 1047 case 2: 1048 Rt &= 0x00FF; 1049 Rt |= (mem_word << 8); 1050 break; 1051 1052 case 3: 1053 Rt &= 0x0FFF; 1054 Rt |= (mem_word << 12); 1055 break; 1056 1057 default: 1058 panic("lwl: bad offset"); 1059 } 1060#elif BYTE_ORDER == LITTLE_ENDIAN 1061 switch(offset) 1062 { 1063 case 0: 1064 Rt &= 0x0FFF; 1065 Rt |= (mem_word << 12); 1066 break; 1067 1068 case 1: 1069 Rt &= 0x00FF; 1070 Rt |= (mem_word << 8); 1071 break; 1072 1073 case 2: 1074 Rt &= 0x000F; 1075 Rt |= (mem_word << 4); 1076 break; 1077 1078 case 3: 1079 Rt = mem_word; 1080 break; 1081 1082 default: 1083 panic("lwl: bad offset"); 1084 } 1085#endif 1086 }}, {{ EA = (Rs + disp) & ~3; }}); 1087 1088 0x3: lw({{ Rt.sw = Mem.sw; }}); 1089 0x4: lbu({{ Rt.uw = Mem.ub; }}); 1090 0x5: lhu({{ Rt.uw = Mem.uh; }}); 1091 0x6: lwr({{ 1092 uint32_t mem_word = Mem.uw; 1093 uint32_t unalign_addr = Rs + disp; 1094 uint32_t offset = unalign_addr & 0x00000003; 1095 1096#if BYTE_ORDER == BIG_ENDIAN 1097 switch(offset) 1098 { 1099 case 0: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; 1100 case 1: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; 1101 case 2: Rt &= 0xF000; Rt |= (mem_word >> 4); break; 1102 case 3: Rt = mem_word; break; 1103 default: panic("lwr: bad offset"); 1104 } 1105#elif BYTE_ORDER == LITTLE_ENDIAN 1106 switch(offset) 1107 { 1108 case 0: Rt = mem_word; break; 1109 case 1: Rt &= 0xF000; Rt |= (mem_word >> 4); break; 1110 case 2: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; 1111 case 3: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; 1112 default: panic("lwr: bad offset"); 1113 } 1114#endif 1115 }}, 1116 {{ EA = (Rs + disp) & ~3; }}); 1117 } 1118 1119 0x7: FailUnimpl::reserved(); 1120 } 1121 1122 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 1123 format StoreMemory { 1124 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 1125 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 1126 0x2: swl({{ 1127 uint32_t mem_word = 0; 1128 uint32_t aligned_addr = (Rs + disp) & ~3; 1129 uint32_t unalign_addr = Rs + disp; 1130 uint32_t offset = unalign_addr & 0x00000003; 1131 1132 DPRINTF(IEW,"Execute: aligned=0x%x unaligned=0x%x\n offset=0x%x", 1133 aligned_addr,unalign_addr,offset); 1134 1135 fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); 1136 1137#if BYTE_ORDER == BIG_ENDIAN 1138 switch(offset) 1139 { 1140 case 0: 1141 Mem = Rt; 1142 break; 1143 1144 case 1: 1145 mem_word &= 0xF000; 1146 mem_word |= (Rt >> 4); 1147 Mem = mem_word; 1148 break; 1149 1150 case 2: 1151 mem_word &= 0xFF00; 1152 mem_word |= (Rt >> 8); 1153 Mem = mem_word; 1154 break; 1155 1156 case 3: 1157 mem_word &= 0xFFF0; 1158 mem_word |= (Rt >> 12); 1159 Mem = mem_word; 1160 break; 1161 1162 default: 1163 panic("swl: bad offset"); 1164 } 1165#elif BYTE_ORDER == LITTLE_ENDIAN 1166 switch(offset) 1167 { 1168 case 0: 1169 mem_word &= 0xFFF0; 1170 mem_word |= (Rt >> 12); 1171 Mem = mem_word; 1172 break; 1173 1174 case 1: 1175 mem_word &= 0xFF00; 1176 mem_word |= (Rt >> 8); 1177 Mem = mem_word; 1178 break; 1179 1180 case 2: 1181 mem_word &= 0xF000; 1182 mem_word |= (Rt >> 4); 1183 Mem = mem_word; 1184 break; 1185 1186 case 3: 1187 Mem = Rt; 1188 break; 1189 1190 default: 1191 panic("swl: bad offset"); 1192 } 1193#endif 1194 }},{{ EA = (Rs + disp) & ~3; }},mem_flags = NO_ALIGN_FAULT); 1195 1196 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 1197 1198 0x6: swr({{ 1199 uint32_t mem_word = 0; 1200 uint32_t aligned_addr = (Rs + disp) & ~3; 1201 uint32_t unalign_addr = Rs + disp; 1202 uint32_t offset = unalign_addr & 0x00000003; 1203 1204 fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); 1205 1206#if BYTE_ORDER == BIG_ENDIAN 1207 switch(offset) 1208 { 1209 case 0: 1210 mem_word &= 0x0FFF; 1211 mem_word |= (Rt << 12); 1212 Mem = mem_word; 1213 break; 1214 1215 case 1: 1216 mem_word &= 0x00FF; 1217 mem_word |= (Rt << 8); 1218 Mem = mem_word; 1219 break; 1220 1221 case 2: 1222 mem_word &= 0x000F; 1223 mem_word |= (Rt << 4); 1224 Mem = mem_word; 1225 break; 1226 1227 case 3: 1228 Mem = Rt; 1229 break; 1230 1231 default: 1232 panic("swr: bad offset"); 1233 } 1234#elif BYTE_ORDER == LITTLE_ENDIAN 1235 switch(offset) 1236 { 1237 case 0: 1238 Mem = Rt; 1239 break; 1240 1241 case 1: 1242 mem_word &= 0x000F; 1243 mem_word |= (Rt << 4); 1244 Mem = mem_word; 1245 break; 1246 1247 case 2: 1248 mem_word &= 0x00FF; 1249 mem_word |= (Rt << 8); 1250 Mem = mem_word; 1251 break; 1252 1253 case 3: 1254 mem_word &= 0x0FFF; 1255 mem_word |= (Rt << 12); 1256 Mem = mem_word; 1257 break; 1258 1259 default: 1260 panic("swr: bad offset"); 1261 } 1262#endif 1263 }},{{ EA = (Rs + disp) & ~3;}},mem_flags = NO_ALIGN_FAULT); 1264 } 1265 1266 format WarnUnimpl { 1267 0x7: cache(); 1268 } 1269 1270 } 1271 1272 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 1273 0x0: LoadMemory::ll({{Rt.uw = Mem.uw}},mem_flags=LOCKED); 1274 1275 format LoadFloatMemory { 1276 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 1277 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 1278 } 1279 } 1280 1281 1282 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 1283 0x0: StoreMemory::sc({{ Mem.uw = Rt.uw; Rt.uw = 1; }}); 1284 1285 format StoreFloatMemory { 1286 0x1: swc1({{ Mem.uw = Ft.uw; }}); 1287 0x5: sdc1({{ Mem.ud = Ft.ud; }}); 1288 } 1289 } 1290} 1291 1292 1293