decoder.isa revision 2573
1// -*- mode:c++ -*- 2 3//////////////////////////////////////////////////////////////////// 4// 5// The actual MIPS32 ISA decoder 6// ----------------------------- 7// The following instructions are specified in the MIPS32 ISA 8// Specification. Decoding closely follows the style specified 9// in the MIPS32 ISAthe specification document starting with Table 10// A-2 (document available @ www.mips.com) 11// 12//@todo: Distinguish "unknown/future" use insts from "reserved" 13// ones 14decode OPCODE_HI default Unknown::unknown() { 15 16 // Derived From ... Table A-2 MIPS32 ISA Manual 17 0x0: decode OPCODE_LO { 18 19 0x0: decode FUNCTION_HI { 20 0x0: decode FUNCTION_LO { 21 0x1: decode MOVCI { 22 format BasicOp { 23 0: movf({{ if (xc->readMiscReg(FPCR) != CC) Rd = Rs}}); 24 1: movt({{ if (xc->readMiscReg(FPCR) == CC) Rd = Rs}}); 25 } 26 } 27 28 format BasicOp { 29 30 //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 31 //are used to distinguish among the SLL, NOP, SSNOP and EHB functions. 32 0x0: decode RS { 33 0x0: decode RT { //fix Nop traditional vs. Nop converted disassembly later 34 0x0: decode RD default Nop::nop(){ 35 0x0: decode SA { 36 0x1: ssnop({{ ; }}); //really sll r0,r0,1 37 0x3: ehb({{ ; }}); //really sll r0,r0,3 38 } 39 } 40 41 default: sll({{ Rd = Rt.uw << SA; }}); 42 } 43 44 } 45 46 0x2: decode RS_SRL { 47 0x0:decode SRL { 48 0: srl({{ Rd = Rt.uw >> SA; }}); 49 50 //Hardcoded assuming 32-bit ISA, probably need parameter here 51 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 52 } 53 } 54 55 0x3: decode RS { 56 0x0: sra({{ 57 uint32_t temp = Rt >> SA; 58 59 if ( (Rt & 0x80000000) > 0 ) { 60 uint32_t mask = 0x80000000; 61 for(int i=0; i < SA; i++) { 62 temp |= mask; 63 mask = mask >> 1; 64 } 65 } 66 67 Rd = temp; 68 }}); 69 } 70 71 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 72 73 0x6: decode SRLV { 74 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 75 76 //Hardcoded assuming 32-bit ISA, probably need parameter here 77 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 78 } 79 80 0x7: srav({{ 81 int shift_amt = Rs<4:0>; 82 83 uint32_t temp = Rt >> shift_amt; 84 85 if ( (Rt & 0x80000000) > 0 ) { 86 uint32_t mask = 0x80000000; 87 for(int i=0; i < shift_amt; i++) { 88 temp |= mask; 89 mask = mask >> 1; 90 } 91 } 92 93 Rd = temp; 94 }}); 95 } 96 } 97 98 0x1: decode FUNCTION_LO { 99 100 //Table A-3 Note: "Specific encodings of the hint field are used 101 //to distinguish JR from JR.HB and JALR from JALR.HB" 102 format Jump { 103 0x0: decode HINT { 104 0:jr({{ NNPC = Rs & ~1; }},IsReturn); 105 106 1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn); 107 } 108 109 0x1: decode HINT { 110 0: jalr({{ Rd = NNPC; NNPC = Rs; }},IsCall,IsReturn); 111 112 1: jalr_hb({{ Rd = NNPC; NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn); 113 } 114 } 115 116 format BasicOp { 117 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 118 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 119 } 120 121 format BasicOp { 122 0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative); 123 0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative); 124 0x7: sync({{ panic("Not implemented sync yet"); }},IsNonSpeculative); 125 } 126 } 127 128 0x2: decode FUNCTION_LO { 129 format BasicOp { 130 0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }}); 131 0x1: mthi({{ xc->setMiscReg(Hi,Rs); }}); 132 0x2: mflo({{ Rd = xc->readMiscReg(Lo); }}); 133 0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }}); 134 } 135 } 136 137 0x3: decode FUNCTION_LO { 138 format IntOp { 139 0x0: mult({{ 140 int64_t temp1 = Rs.sd * Rt.sd; 141 xc->setMiscReg(Hi,temp1<63:32>); 142 xc->setMiscReg(Lo,temp1<31:0>); 143 }}); 144 145 0x1: multu({{ 146 uint64_t temp1 = Rs.ud * Rt.ud; 147 xc->setMiscReg(Hi,temp1<63:32>); 148 xc->setMiscReg(Lo,temp1<31:0>); 149 }}); 150 151 0x2: div({{ 152 xc->setMiscReg(Hi,Rs.sw % Rt.sw); 153 xc->setMiscReg(Lo,Rs.sw / Rt.sw); 154 }}); 155 156 0x3: divu({{ 157 xc->setMiscReg(Hi,Rs.uw % Rt.uw); 158 xc->setMiscReg(Lo,Rs.uw / Rt.uw); 159 }}); 160 } 161 } 162 163 0x4: decode HINT { 164 0x0: decode FUNCTION_LO { 165 format IntOp { 166 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}}); 167 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 168 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}}); 169 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 170 0x4: and({{ Rd = Rs & Rt;}}); 171 0x5: or({{ Rd = Rs | Rt;}}); 172 0x6: xor({{ Rd = Rs ^ Rt;}}); 173 0x7: nor({{ Rd = ~(Rs | Rt);}}); 174 } 175 } 176 } 177 178 0x5: decode HINT { 179 0x0: decode FUNCTION_LO { 180 format IntOp{ 181 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 182 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 183 } 184 } 185 } 186 187 0x6: decode FUNCTION_LO { 188 format Trap { 189 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 190 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 191 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 192 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 193 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 194 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 195 } 196 } 197 } 198 199 0x1: decode REGIMM_HI { 200 0x0: decode REGIMM_LO { 201 format Branch { 202 0x0: bltz({{ cond = (Rs.sw < 0); }}); 203 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 204 } 205 206 format BranchLikely { 207 //MIPS obsolete instructions 208 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 209 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 210 } 211 } 212 213 0x1: decode REGIMM_LO { 214 format Trap { 215 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 216 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 217 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 218 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 219 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 220 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 221 } 222 } 223 224 0x2: decode REGIMM_LO { 225 format Branch { 226 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn); 227 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn); 228 } 229 230 format BranchLikely { 231 //Will be removed in future MIPS releases 232 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn); 233 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn); 234 } 235 } 236 237 0x3: decode REGIMM_LO { 238 format WarnUnimpl { 239 0x7: synci(); 240 } 241 } 242 } 243 244 format Jump { 245 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 246 247 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn); 248 } 249 250 format Branch { 251 0x4: beq({{ cond = (Rs.sw == Rt.sw); }}); 252 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 253 0x6: decode RT { 254 0x0: blez({{ cond = (Rs.sw <= 0); }}); 255 } 256 257 0x7: decode RT { 258 0x0: bgtz({{ cond = (Rs.sw > 0); }}); 259 } 260 } 261 } 262 263 0x1: decode OPCODE_LO { 264 format IntOp { 265 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}}); 266 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 267 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 268 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); 269 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 270 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 271 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); 272 273 0x7: decode RS { 274 0x0: lui({{ Rt = imm << 16}}); 275 } 276 } 277 } 278 279 0x2: decode OPCODE_LO { 280 281 //Table A-11 MIPS32 COP0 Encoding of rs Field 282 0x0: decode RS_MSB { 283 0x0: decode RS { 284 format System { 285 0x0: mfc0({{ 286 //uint64_t reg_num = Rd.uw; 287 288 Rt = xc->readMiscReg(RD << 5 | SEL); 289 }}); 290 291 0x4: mtc0({{ 292 //uint64_t reg_num = Rd.uw; 293 294 xc->setMiscReg(RD << 5 | SEL,Rt); 295 }}); 296 297 0x8: mftr({{ 298 //The contents of the coprocessor 0 register specified by the 299 //combination of rd and sel are loaded into general register 300 //rt. Note that not all coprocessor 0 registers support the 301 //sel field. In those instances, the sel field must be zero. 302 303 //MT Code Needed Here 304 }}); 305 306 0xC: mttr({{ 307 //The contents of the coprocessor 0 register specified by the 308 //combination of rd and sel are loaded into general register 309 //rt. Note that not all coprocessor 0 registers support the 310 //sel field. In those instances, the sel field must be zero. 311 312 //MT Code Needed Here 313 }}); 314 315 316 0xA: rdpgpr({{ 317 //Accessing Previous Shadow Set Register Number 318 //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/; 319 //uint64_t reg_num = Rt.uw; 320 321 //Rd = xc->regs.IntRegFile[prev]; 322 //Rd = xc->shadowIntRegFile[prev][reg_num]; 323 }}); 324 325 0xB: decode RD { 326 327 0x0: decode SC { 328 0x0: dvpe({{ 329 Rt.sw = xc->readMiscReg(MVPControl); 330 xc->setMiscReg(MVPControl,0); 331 }}); 332 333 0x1: evpe({{ 334 Rt.sw = xc->readMiscReg(MVPControl); 335 xc->setMiscReg(MVPControl,1); 336 }}); 337 } 338 339 0x1: decode SC { 340 0x0: dmt({{ 341 Rt.sw = xc->readMiscReg(VPEControl); 342 xc->setMiscReg(VPEControl,0); 343 }}); 344 345 0x1: emt({{ 346 Rt.sw = xc->readMiscReg(VPEControl); 347 xc->setMiscReg(VPEControl,1); 348 }}); 349 } 350 351 0xC: decode SC { 352 0x0: di({{ 353 Rt.sw = xc->readMiscReg(Status); 354 xc->setMiscReg(Status,0); 355 }}); 356 357 0x1: ei({{ 358 Rt.sw = xc->readMiscReg(Status); 359 xc->setMiscReg(Status,1); 360 }}); 361 } 362 } 363 364 0xE: wrpgpr({{ 365 //Accessing Previous Shadow Set Register Number 366 //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/); 367 //uint64_t reg_num = Rd.uw; 368 369 //xc->regs.IntRegFile[prev]; 370 //xc->shadowIntRegFile[prev][reg_num] = Rt; 371 }}); 372 } 373 } 374 375 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 376 0x1: decode FUNCTION { 377 format System { 378 0x01: tlbr({{ }}); 379 0x02: tlbwi({{ }}); 380 0x06: tlbwr({{ }}); 381 0x08: tlbp({{ }}); 382 } 383 384 format WarnUnimpl { 385 0x18: eret(); 386 0x1F: deret(); 387 0x20: wait(); 388 } 389 } 390 } 391 392 //Table A-13 MIPS32 COP1 Encoding of rs Field 393 0x1: decode RS_MSB { 394 395 0x0: decode RS_HI { 396 0x0: decode RS_LO { 397 format FloatOp { 398 0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }}); 399 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); 400 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); 401 0x7: mthc1({{ 402 uint64_t fs_hi = Rt.ud << 32; 403 uint64_t fs_lo = Fs.ud & 0x0000FFFF; 404 Fs.ud = fs_hi & fs_lo; 405 }}); 406 } 407 408 format System { 409 0x2: cfc1({{ 410 std::cout << "FP Control Reg " << FS << "accessed." << std::endl; 411 uint32_t fcsr_reg = xc->readMiscReg(FCSR); 412 413 switch (FS) 414 { 415 case 0: 416 Rt = xc->readMiscReg(FIR); 417 break; 418 case 25: 419 Rt = 0 | (fcsr_reg & 0xFE000000) >> 24 | (fcsr_reg & 0x00800000) >> 23; 420 break; 421 case 26: 422 Rt = 0 | (fcsr_reg & 0x0003F07C); 423 break; 424 case 28: 425 Rt = 0 | (fcsr_reg); 426 break; 427 case 31: 428 Rt = fcsr_reg; 429 break; 430 default: 431 panic("FP Control Value (%d) Not Available. Ignoring Access to" 432 "Floating Control Status Register",fcsr_reg); 433 } 434 }}); 435 436 0x6: ctc1({{ 437 std::cout << "FP Control Reg " << FS << "accessed." << std::endl; 438 439 uint32_t fcsr_reg = xc->readMiscReg(FCSR); 440 uint32_t temp; 441 switch (FS) 442 { 443 case 25: 444 temp = 0 | (Rt.uw<7:1> << 25) // move 31...25 445 | (fcsr_reg & 0x01000000) // bit 24 446 | (fcsr_reg & 0x004FFFFF);// bit 22...0 447 break; 448 449 case 26: 450 temp = 0 | (fcsr_reg & 0xFFFC0000) // move 31...18 451 | Rt.uw<17:12> << 12 // bit 17...12 452 | (fcsr_reg & 0x00000F80) << 7// bit 11...7 453 | Rt.uw<6:2> << 2 // bit 6...2 454 | (fcsr_reg & 0x00000002); // bit 1...0 455 break; 456 457 case 28: 458 temp = 0 | (fcsr_reg & 0xFE000000) // move 31...25 459 | Rt.uw<2:2> << 24 // bit 24 460 | (fcsr_reg & 0x00FFF000) << 23// bit 23...12 461 | Rt.uw<11:7> << 7 // bit 24 462 | (fcsr_reg & 0x000007E) 463 | Rt.uw<1:0>;// bit 22...0 464 break; 465 466 case 31: 467 temp = Rt.uw; 468 break; 469 470 default: 471 panic("FP Control Value (%d) Not Available. Ignoring Access to" 472 "Floating Control Status Register",fcsr_reg); 473 } 474 475 xc->setMiscReg(FCSR,temp); 476 }}); 477 } 478 } 479 480 0x1: decode ND { 481 0x0: decode TF { 482 format Branch { 483 0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 484 0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 485 } 486 } 487 488 0x1: decode TF { 489 format BranchLikely { 490 0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 491 0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 492 } 493 } 494 } 495 } 496 497 0x1: decode RS_HI { 498 0x2: decode RS_LO { 499 500 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 501 //(( single-word )) 502 0x0: decode FUNCTION_HI { 503 0x0: decode FUNCTION_LO { 504 format FloatOp { 505 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); 506 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); 507 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); 508 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); 509 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); 510 0x5: abss({{ Fd.sf = fabs(Fs.sf);}}); 511 0x6: movs({{ Fd.sf = Fs.sf;}}); 512 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); 513 } 514 } 515 516 0x1: decode FUNCTION_LO { 517 //only legal for 64 bit-FP 518 format Float64Op { 519 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}}); 520 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}}); 521 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}}); 522 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}}); 523 } 524 525 format FloatOp { 526 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}}); 527 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}}); 528 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}}); 529 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}}); 530 } 531 } 532 533 0x2: decode FUNCTION_LO { 534 0x1: decode MOVCF { 535 format FloatOp { 536 0x0: movfs({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); 537 0x1: movts({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); 538 } 539 } 540 541 format BasicOp { 542 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 543 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); 544 } 545 546 format Float64Op { 547 0x5: recips({{ Fd = 1 / Fs; }}); 548 0x6: rsqrts({{ Fd = 1 / sqrt((double)Fs.ud);}}); 549 } 550 } 551 552 0x4: decode FUNCTION_LO { 553 554 format FloatOp { 555 0x1: cvt_d_s({{ 556 int rnd_mode = xc->readMiscReg(FCSR); 557 Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE); 558 }}); 559 560 0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR); 561 Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE); 562 }}); 563 } 564 565 //only legal for 64 bit 566 format Float64Op { 567 0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR); 568 Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE); 569 }}); 570 571 0x6: cvt_ps_s({{ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/ }}); 572 } 573 } 574 } 575 576 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 577 0x1: decode FUNCTION_HI { 578 0x0: decode FUNCTION_LO { 579 format FloatOp { 580 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 581 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 582 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 583 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 584 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 585 0x5: absd({{ Fd.df = fabs(Fs.df);}}); 586 0x6: movd({{ Fd.df = Fs.df;}}); 587 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 588 } 589 } 590 591 0x1: decode FUNCTION_LO { 592 //only legal for 64 bit 593 format Float64Op { 594 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 595 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}}); 596 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}}); 597 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}}); 598 } 599 600 format FloatOp { 601 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 602 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }}); 603 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }}); 604 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }}); 605 } 606 } 607 608 0x2: decode FUNCTION_LO { 609 0x1: decode MOVCF { 610 format FloatOp { 611 0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }}); 612 0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }}); 613 } 614 } 615 616 format BasicOp { 617 0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }}); 618 0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }}); 619 } 620 621 format Float64Op { 622 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 623 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 624 } 625 } 626 627 0x4: decode FUNCTION_LO { 628 format FloatOp { 629 0x0: cvt_s_d({{ 630 int rnd_mode = xc->readMiscReg(FCSR); 631 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE); 632 }}); 633 634 0x4: cvt_w_d({{ 635 int rnd_mode = xc->readMiscReg(FCSR); 636 Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE); 637 }}); 638 } 639 640 //only legal for 64 bit 641 format Float64Op { 642 0x5: cvt_l_d({{ 643 int rnd_mode = xc->readMiscReg(FCSR); 644 Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE); 645 }}); 646 } 647 } 648 } 649 650 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 651 0x4: decode FUNCTION { 652 format FloatOp { 653 0x20: cvt_s({{ 654 int rnd_mode = xc->readMiscReg(FCSR); 655 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); 656 }}); 657 658 0x21: cvt_d({{ 659 int rnd_mode = xc->readMiscReg(FCSR); 660 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); 661 }}); 662 } 663 } 664 665 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 666 //Note: "1. Format type L is legal only if 64-bit floating point operations 667 //are enabled." 668 0x5: decode FUNCTION_HI { 669 format FloatOp { 670 0x10: cvt_s_l({{ 671 int rnd_mode = xc->readMiscReg(FCSR); 672 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG); 673 }}); 674 675 0x11: cvt_d_l({{ 676 int rnd_mode = xc->readMiscReg(FCSR); 677 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG); 678 }}); 679 } 680 } 681 682 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 683 //Note: "1. Format type PS is legal only if 64-bit floating point operations 684 //are enabled. " 685 0x6: decode FUNCTION_HI { 686 0x0: decode FUNCTION_LO { 687 format Float64Op { 688 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 689 //Lower Halves Independently but we take simulator shortcut 690 Fd.df = Fs.df + Ft.df; 691 }}); 692 693 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 694 //Lower Halves Independently but we take simulator shortcut 695 Fd.df = Fs.df - Ft.df; 696 }}); 697 698 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 699 //Lower Halves Independently but we take simulator shortcut 700 Fd.df = Fs.df * Ft.df; 701 }}); 702 703 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 704 //Lower Halves Independently but we take simulator shortcut 705 Fd.df = fabs(Fs.df); 706 }}); 707 708 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 709 //Lower Halves Independently but we take simulator shortcut 710 //Fd.df = Fs<31:0> | Ft<31:0>; 711 }}); 712 713 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 714 //Lower Halves Independently but we take simulator shortcut 715 Fd.df = -1 * Fs.df; 716 }}); 717 } 718 } 719 720 0x2: decode FUNCTION_LO { 721 0x1: decode MOVCF { 722 format Float64Op { 723 0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}}); 724 0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); 725 } 726 } 727 728 format BasicOp { 729 0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); 730 0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }}); 731 } 732 733 } 734 735 0x4: decode FUNCTION_LO { 736 0x0: Float64Op::cvt_s_pu({{ 737 int rnd_mode = xc->readMiscReg(FCSR); 738 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI); 739 }}); 740 } 741 742 0x5: decode FUNCTION_LO { 743 format Float64Op { 744 0x0: cvt_s_pl({{ 745 int rnd_mode = xc->readMiscReg(FCSR); 746 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO); 747 }}); 748 0x4: pll({{ /*Fd.df = Fs<31:0> | Ft<31:0>*/}}); 749 0x5: plu({{ /*Fd.df = Fs<31:0> | Ft<63:32>*/}}); 750 0x6: pul({{ /*Fd.df = Fs<63:32> | Ft<31:0>*/}}); 751 0x7: puu({{ /*Fd.df = Fs<63:32 | Ft<63:32>*/}}); 752 } 753 } 754 } 755 } 756 } 757 } 758 759 //Table A-19 MIPS32 COP2 Encoding of rs Field 760 0x2: decode RS_MSB { 761 0x0: decode RS_HI { 762 0x0: decode RS_LO { 763 format WarnUnimpl { 764 0x0: mfc2(); 765 0x2: cfc2(); 766 0x3: mfhc2(); 767 0x4: mtc2(); 768 0x6: ctc2(); 769 0x7: mftc2(); 770 } 771 } 772 773 0x1: decode ND { 774 0x0: decode TF { 775 format WarnUnimpl { 776 0x0: bc2f(); 777 0x1: bc2t(); 778 } 779 } 780 781 0x1: decode TF { 782 format WarnUnimpl { 783 0x0: bc2fl(); 784 0x1: bc2tl(); 785 } 786 } 787 } 788 } 789 } 790 791 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 792 //Note: "COP1X instructions are legal only if 64-bit floating point 793 //operations are enabled." 794 0x3: decode FUNCTION_HI { 795 0x0: decode FUNCTION_LO { 796 format LoadFloatMemory { 797 0x0: lwxc1({{ /*F_t<31:0> = Mem.sf; */}}, {{ EA = Rs + Rt; }}); 798 0x1: ldxc1({{ /*F_t<63:0> = Mem.df;*/ }}, {{ EA = Rs + Rt; }}); 799 0x5: luxc1({{ /*F_t<31:0> = Mem.df; */}}, 800 {{ //Need to make EA<2:0> = 0 801 EA = Rs + Rt; 802 }}); 803 } 804 } 805 806 0x1: decode FUNCTION_LO { 807 format StoreFloatMemory { 808 0x0: swxc1({{ /*Mem.sf = Ft<31:0>; */}},{{ EA = Rs + Rt; }}); 809 0x1: sdxc1({{ /*Mem.df = Ft<63:0> */}}, {{ EA = Rs + Rt; }}); 810 0x5: suxc1({{ /*Mem.df = F_t<63:0>;*/}}, 811 {{ //Need to make sure EA<2:0> = 0 812 EA = Rs + Rt; 813 }}); 814 } 815 816 0x7: WarnUnimpl::prefx(); 817 } 818 819 format FloatOp { 820 0x3: WarnUnimpl::alnv_ps(); 821 822 format BasicOp { 823 0x4: decode FUNCTION_LO { 824 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 825 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 826 0x6: madd_ps({{ 827 //Must Check for Exception Here... Supposed to Operate on Upper and 828 //Lower Halves Independently but we take simulator shortcut 829 Fd.df = (Fs.df * Fs.df) + Fr.df; 830 }}); 831 } 832 833 0x5: decode FUNCTION_LO { 834 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 835 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 836 0x6: msub_ps({{ 837 //Must Check for Exception Here... Supposed to Operate on Upper and 838 //Lower Halves Independently but we take simulator shortcut 839 Fd.df = (Fs.df * Fs.df) - Fr.df; 840 }}); 841 } 842 843 0x6: decode FUNCTION_LO { 844 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 845 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 846 0x6: nmadd_ps({{ 847 //Must Check for Exception Here... Supposed to Operate on Upper and 848 //Lower Halves Independently but we take simulator shortcut 849 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 850 }}); 851 } 852 853 0x7: decode FUNCTION_LO { 854 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 855 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 856 0x6: nmsub_ps({{ 857 //Must Check for Exception Here... Supposed to Operate on Upper and 858 //Lower Halves Independently but we take simulator shortcut 859 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 860 }}); 861 } 862 } 863 } 864 } 865 866 //MIPS obsolete instructions 867 format BranchLikely { 868 0x4: beql({{ cond = (Rs.sw == 0); }}); 869 0x5: bnel({{ cond = (Rs.sw != 0); }}); 870 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 871 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 872 } 873 } 874 875 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 876 877 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 878 0x4: decode FUNCTION_HI { 879 880 0x0: decode FUNCTION_LO { 881 format IntOp { 882 0x0: madd({{ 883 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 884 temp1 = temp1 + (Rs.sw * Rt.sw); 885 xc->setMiscReg(Hi,temp1<63:32>); 886 xc->setMiscReg(Lo,temp1<31:0>); 887 }}); 888 889 0x1: maddu({{ 890 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 891 temp1 = temp1 + (Rs.uw * Rt.uw); 892 xc->setMiscReg(Hi,temp1<63:32>); 893 xc->setMiscReg(Lo,temp1<31:0>); 894 }}); 895 896 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 897 898 0x4: msub({{ 899 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 900 temp1 = temp1 - (Rs.sw * Rt.sw); 901 xc->setMiscReg(Hi,temp1<63:32>); 902 xc->setMiscReg(Lo,temp1<31:0>); 903 }}); 904 905 0x5: msubu({{ 906 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 907 temp1 = temp1 - (Rs.uw * Rt.uw); 908 xc->setMiscReg(Hi,temp1<63:32>); 909 xc->setMiscReg(Lo,temp1<31:0>); 910 }}); 911 } 912 } 913 914 0x4: decode FUNCTION_LO { 915 format BasicOp { 916 0x0: clz({{ 917 /*int cnt = 0; 918 int idx = 0; 919 while ( Rs.uw<idx> != 1) { 920 cnt++; 921 idx--; 922 } 923 924 Rd.uw = cnt;*/ 925 }}); 926 927 0x1: clo({{ 928 /*int cnt = 0; 929 int idx = 0; 930 while ( Rs.uw<idx> != 0) { 931 cnt++; 932 idx--; 933 } 934 935 Rd.uw = cnt;*/ 936 }}); 937 } 938 } 939 940 0x7: decode FUNCTION_LO { 941 0x7: WarnUnimpl::sdbbp(); 942 } 943 } 944 945 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 946 0x7: decode FUNCTION_HI { 947 948 0x0: decode FUNCTION_LO { 949 format FailUnimpl { 950 0x1: ext(); 951 0x4: ins(); 952 } 953 } 954 955 0x1: decode FUNCTION_LO { 956 format FailUnimpl { 957 0x0: fork(); 958 0x1: yield(); 959 } 960 } 961 962 963 //Table A-10 MIPS32 BSHFL Encoding of sa Field 964 0x4: decode SA { 965 966 0x02: FailUnimpl::wsbh(); 967 968 format BasicOp { 969 0x10: seb({{ Rd.sw = Rt<7:0>}}); 970 0x18: seh({{ Rd.sw = Rt<15:0>}}); 971 } 972 } 973 974 0x6: decode FUNCTION_LO { 975 0x7: FailUnimpl::rdhwr();//{{ /*Rt = xc->hwRegs[RD];*/ }} 976 } 977 } 978 } 979 980 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 981 format LoadMemory { 982 0x0: lb({{ Rt.sw = Mem.sb; }}); 983 0x1: lh({{ Rt.sw = Mem.sh; }}); 984 985 0x2: lwl({{ 986 uint32_t mem_word = Mem.uw; 987 uint32_t unalign_addr = Rs + disp; 988 uint32_t offset = unalign_addr & 0x00000003; 989#if BYTE_ORDER == BIG_ENDIAN 990 std::cout << "Big Endian Byte Order\n"; 991 992 switch(offset) 993 { 994 case 0: 995 Rt = mem_word; 996 break; 997 998 case 1: 999 Rt &= 0x000F; 1000 Rt |= (mem_word << 4); 1001 break; 1002 1003 case 2: 1004 Rt &= 0x00FF; 1005 Rt |= (mem_word << 8); 1006 break; 1007 1008 case 3: 1009 Rt &= 0x0FFF; 1010 Rt |= (mem_word << 12); 1011 break; 1012 1013 default: 1014 panic("lwl: bad offset"); 1015 } 1016#elif BYTE_ORDER == LITTLE_ENDIAN 1017 std::cout << "Little Endian Byte Order\n"; 1018 1019 switch(offset) 1020 { 1021 case 0: 1022 Rt &= 0x0FFF; 1023 Rt |= (mem_word << 12); 1024 break; 1025 1026 case 1: 1027 Rt &= 0x00FF; 1028 Rt |= (mem_word << 8); 1029 break; 1030 1031 case 2: 1032 Rt &= 0x000F; 1033 Rt |= (mem_word << 4); 1034 break; 1035 1036 case 3: 1037 Rt = mem_word; 1038 break; 1039 1040 default: 1041 panic("lwl: bad offset"); 1042 } 1043#endif 1044 }}, {{ EA = (Rs + disp) & ~3; }}); 1045 1046 0x3: lw({{ Rt.sw = Mem.sw; }}); 1047 0x4: lbu({{ Rt.uw = Mem.ub; }}); 1048 0x5: lhu({{ Rt.uw = Mem.uh; }}); 1049 0x6: lwr({{ 1050 uint32_t mem_word = Mem.uw; 1051 uint32_t unalign_addr = Rs + disp; 1052 uint32_t offset = unalign_addr & 0x00000003; 1053 1054#if BYTE_ORDER == BIG_ENDIAN 1055 switch(offset) 1056 { 1057 case 0: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; 1058 case 1: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; 1059 case 2: Rt &= 0xF000; Rt |= (mem_word >> 4); break; 1060 case 3: Rt = mem_word; break; 1061 default: panic("lwr: bad offset"); 1062 } 1063#elif BYTE_ORDER == LITTLE_ENDIAN 1064 switch(offset) 1065 { 1066 case 0: Rt = mem_word; break; 1067 case 1: Rt &= 0xF000; Rt |= (mem_word >> 4); break; 1068 case 2: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; 1069 case 3: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; 1070 default: panic("lwr: bad offset"); 1071 } 1072#endif 1073 }}, 1074 {{ EA = (Rs + disp) & ~3; }}); 1075 } 1076 1077 0x7: FailUnimpl::reserved(); 1078 } 1079 1080 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 1081 format StoreMemory { 1082 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 1083 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 1084 0x2: swl({{ 1085 uint32_t mem_word = 0; 1086 uint32_t aligned_addr = (Rs + disp) & ~3; 1087 uint32_t unalign_addr = Rs + disp; 1088 uint32_t offset = unalign_addr & 0x00000003; 1089 1090 DPRINTF(IEW,"Execute: aligned=0x%x unaligned=0x%x\n offset=0x%x", 1091 aligned_addr,unalign_addr,offset); 1092 1093 fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); 1094 1095#if BYTE_ORDER == BIG_ENDIAN 1096 switch(offset) 1097 { 1098 case 0: 1099 Mem = Rt; 1100 break; 1101 1102 case 1: 1103 mem_word &= 0xF000; 1104 mem_word |= (Rt >> 4); 1105 Mem = mem_word; 1106 break; 1107 1108 case 2: 1109 mem_word &= 0xFF00; 1110 mem_word |= (Rt >> 8); 1111 Mem = mem_word; 1112 break; 1113 1114 case 3: 1115 mem_word &= 0xFFF0; 1116 mem_word |= (Rt >> 12); 1117 Mem = mem_word; 1118 break; 1119 1120 default: 1121 panic("swl: bad offset"); 1122 } 1123#elif BYTE_ORDER == LITTLE_ENDIAN 1124 switch(offset) 1125 { 1126 case 0: 1127 mem_word &= 0xFFF0; 1128 mem_word |= (Rt >> 12); 1129 Mem = mem_word; 1130 break; 1131 1132 case 1: 1133 mem_word &= 0xFF00; 1134 mem_word |= (Rt >> 8); 1135 Mem = mem_word; 1136 break; 1137 1138 case 2: 1139 mem_word &= 0xF000; 1140 mem_word |= (Rt >> 4); 1141 Mem = mem_word; 1142 break; 1143 1144 case 3: 1145 Mem = Rt; 1146 break; 1147 1148 default: 1149 panic("swl: bad offset"); 1150 } 1151#endif 1152 }},{{ EA = (Rs + disp) & ~3; }},mem_flags = NO_ALIGN_FAULT); 1153 1154 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 1155 1156 0x6: swr({{ 1157 uint32_t mem_word = 0; 1158 uint32_t aligned_addr = (Rs + disp) & ~3; 1159 uint32_t unalign_addr = Rs + disp; 1160 uint32_t offset = unalign_addr & 0x00000003; 1161 1162 fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); 1163 1164#if BYTE_ORDER == BIG_ENDIAN 1165 switch(offset) 1166 { 1167 case 0: 1168 mem_word &= 0x0FFF; 1169 mem_word |= (Rt << 12); 1170 Mem = mem_word; 1171 break; 1172 1173 case 1: 1174 mem_word &= 0x00FF; 1175 mem_word |= (Rt << 8); 1176 Mem = mem_word; 1177 break; 1178 1179 case 2: 1180 mem_word &= 0x000F; 1181 mem_word |= (Rt << 4); 1182 Mem = mem_word; 1183 break; 1184 1185 case 3: 1186 Mem = Rt; 1187 break; 1188 1189 default: 1190 panic("swr: bad offset"); 1191 } 1192#elif BYTE_ORDER == LITTLE_ENDIAN 1193 switch(offset) 1194 { 1195 case 0: 1196 Mem = Rt; 1197 break; 1198 1199 case 1: 1200 mem_word &= 0x000F; 1201 mem_word |= (Rt << 4); 1202 Mem = mem_word; 1203 break; 1204 1205 case 2: 1206 mem_word &= 0x00FF; 1207 mem_word |= (Rt << 8); 1208 Mem = mem_word; 1209 break; 1210 1211 case 3: 1212 mem_word &= 0x0FFF; 1213 mem_word |= (Rt << 12); 1214 Mem = mem_word; 1215 break; 1216 1217 default: 1218 panic("swr: bad offset"); 1219 } 1220#endif 1221 }},{{ EA = (Rs + disp) & ~3;}},mem_flags = NO_ALIGN_FAULT); 1222 } 1223 1224 format WarnUnimpl { 1225 0x7: cache(); 1226 } 1227 1228 } 1229 1230 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 1231 0x0: FailUnimpl::ll(); 1232 1233 format LoadFloatMemory { 1234 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 1235 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 1236 } 1237 } 1238 1239 1240 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 1241 0x0: FailUnimpl::sc(); 1242 1243 format StoreFloatMemory { 1244 0x1: swc1({{ Mem.uw = Ft.uw; }}); 1245 0x5: sdc1({{ Mem.ud = Ft.ud; }}); 1246 } 1247 } 1248} 1249 1250 1251