decoder.isa revision 2572
12SN/A// -*- mode:c++ -*-
21762SN/A
32SN/A////////////////////////////////////////////////////////////////////
42SN/A//
52SN/A// The actual MIPS32 ISA decoder
62SN/A// -----------------------------
72SN/A// The following instructions are specified in the MIPS32 ISA
82SN/A// Specification. Decoding closely follows the style specified
92SN/A// in the MIPS32 ISAthe specification document starting with Table
102SN/A// A-2 (document available @ www.mips.com)
112SN/A//
122SN/A//@todo: Distinguish "unknown/future" use insts from "reserved"
132SN/A// ones
142SN/Adecode OPCODE_HI default Unknown::unknown() {
152SN/A
162SN/A    // Derived From ... Table A-2 MIPS32 ISA Manual
172SN/A    0x0: decode OPCODE_LO {
182SN/A
192SN/A        0x0: decode FUNCTION_HI {
202SN/A            0x0: decode FUNCTION_LO {
212SN/A                0x1: decode MOVCI {
222SN/A                    format BasicOp {
232SN/A                        0: movf({{ if (xc->readMiscReg(FPCR) != CC) Rd = Rs}});
242SN/A                        1: movt({{ if (xc->readMiscReg(FPCR) == CC) Rd = Rs}});
252SN/A                    }
262SN/A                }
272665Ssaidi@eecs.umich.edu
282665Ssaidi@eecs.umich.edu                format BasicOp {
292665Ssaidi@eecs.umich.edu
302SN/A                    //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
312SN/A                    //are used to distinguish among the SLL, NOP, SSNOP and EHB functions.
321112SN/A                    0x0: decode RS  {
331112SN/A                        0x0: decode RT {     //fix Nop traditional vs. Nop converted disassembly later
342SN/A                             0x0: decode RD  default Nop::nop(){
353386Sgblack@eecs.umich.edu                                  0x0: decode SA {
362SN/A                                      0x1: ssnop({{ ; }}); //really sll r0,r0,1
372SN/A                                      0x3: ehb({{ ; }});   //really sll r0,r0,3
382SN/A                                  }
392SN/A                             }
402SN/A
412SN/A                             default: sll({{ Rd = Rt.uw << SA; }});
422SN/A                        }
432SN/A
442SN/A                    }
452SN/A
462SN/A                    0x2: decode RS_SRL {
474070Ssaidi@eecs.umich.edu                        0x0:decode SRL {
482SN/A                            0: srl({{ Rd = Rt.uw >> SA; }});
492SN/A
502SN/A                            //Hardcoded assuming 32-bit ISA, probably need parameter here
512SN/A                            1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
522SN/A                        }
532SN/A                    }
542SN/A
552SN/A                    0x3: decode RS {
562SN/A                        0x0: sra({{
572SN/A                            uint32_t temp = Rt >> SA;
582SN/A
592SN/A                            if ( (Rt & 0x80000000) > 0 ) {
602SN/A                                uint32_t mask = 0x80000000;
612SN/A                                for(int i=0; i < SA; i++) {
623814Ssaidi@eecs.umich.edu                                    temp |= mask;
633814Ssaidi@eecs.umich.edu                                    mask = mask >> 1;
643814Ssaidi@eecs.umich.edu                                }
653814Ssaidi@eecs.umich.edu                            }
663814Ssaidi@eecs.umich.edu
673814Ssaidi@eecs.umich.edu                            Rd = temp;
683814Ssaidi@eecs.umich.edu                        }});
693814Ssaidi@eecs.umich.edu                    }
703814Ssaidi@eecs.umich.edu
713814Ssaidi@eecs.umich.edu                    0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
723814Ssaidi@eecs.umich.edu
734070Ssaidi@eecs.umich.edu                    0x6: decode SRLV {
744070Ssaidi@eecs.umich.edu                        0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
754070Ssaidi@eecs.umich.edu
764070Ssaidi@eecs.umich.edu                        //Hardcoded assuming 32-bit ISA, probably need parameter here
774070Ssaidi@eecs.umich.edu                        1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
784070Ssaidi@eecs.umich.edu                    }
793814Ssaidi@eecs.umich.edu
802SN/A                    0x7: srav({{
812SN/A                        int shift_amt = Rs<4:0>;
822SN/A
832SN/A                        uint32_t temp = Rt >> shift_amt;
842SN/A
852SN/A                        if ( (Rt & 0x80000000) > 0 ) {
862SN/A                                uint32_t mask = 0x80000000;
872SN/A                                for(int i=0; i < shift_amt; i++) {
882SN/A                                    temp |= mask;
892SN/A                                    mask = mask >> 1;
902SN/A                                }
913422Sgblack@eecs.umich.edu                            }
923422Sgblack@eecs.umich.edu
933422Sgblack@eecs.umich.edu                        Rd = temp;
943422Sgblack@eecs.umich.edu                    }});
953422Sgblack@eecs.umich.edu                }
963422Sgblack@eecs.umich.edu            }
973422Sgblack@eecs.umich.edu
983422Sgblack@eecs.umich.edu            0x1: decode FUNCTION_LO {
993422Sgblack@eecs.umich.edu
1003422Sgblack@eecs.umich.edu                //Table A-3 Note: "Specific encodings of the hint field are used
1013422Sgblack@eecs.umich.edu                //to distinguish JR from JR.HB and JALR from JALR.HB"
1023422Sgblack@eecs.umich.edu                format Jump {
1033422Sgblack@eecs.umich.edu                    0x0: decode HINT {
1043422Sgblack@eecs.umich.edu                        0:jr({{ NNPC = Rs & ~1; }},IsReturn);
1053422Sgblack@eecs.umich.edu
1063422Sgblack@eecs.umich.edu                        1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn);
1073422Sgblack@eecs.umich.edu                    }
1083422Sgblack@eecs.umich.edu
1093422Sgblack@eecs.umich.edu                    0x1: decode HINT {
1103422Sgblack@eecs.umich.edu                        0: jalr({{ Rd = NNPC; NNPC = Rs; }},IsCall,IsReturn);
1113422Sgblack@eecs.umich.edu
1123422Sgblack@eecs.umich.edu                        1: jalr_hb({{ Rd = NNPC; NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn);
1133422Sgblack@eecs.umich.edu                    }
1143422Sgblack@eecs.umich.edu                }
1154103Ssaidi@eecs.umich.edu
1164103Ssaidi@eecs.umich.edu                format BasicOp {
1174103Ssaidi@eecs.umich.edu                    0x2: movz({{ if (Rt == 0) Rd = Rs; }});
1184103Ssaidi@eecs.umich.edu                    0x3: movn({{ if (Rt != 0) Rd = Rs; }});
1194103Ssaidi@eecs.umich.edu                }
1204103Ssaidi@eecs.umich.edu
1214103Ssaidi@eecs.umich.edu                format BasicOp {
1224103Ssaidi@eecs.umich.edu                    0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative);
1234103Ssaidi@eecs.umich.edu                    0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative);
1244244Ssaidi@eecs.umich.edu                    0x7: sync({{  panic("Not implemented sync yet"); }},IsNonSpeculative);
1254244Ssaidi@eecs.umich.edu                }
1264244Ssaidi@eecs.umich.edu            }
1274244Ssaidi@eecs.umich.edu
1284244Ssaidi@eecs.umich.edu            0x2: decode FUNCTION_LO {
1294244Ssaidi@eecs.umich.edu                format BasicOp {
1304103Ssaidi@eecs.umich.edu                    0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }});
1314103Ssaidi@eecs.umich.edu                    0x1: mthi({{ xc->setMiscReg(Hi,Rs); }});
1324103Ssaidi@eecs.umich.edu                    0x2: mflo({{ Rd = xc->readMiscReg(Lo); }});
1334259Sgblack@eecs.umich.edu                    0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }});
1344259Sgblack@eecs.umich.edu                }
1354259Sgblack@eecs.umich.edu            }
1364259Sgblack@eecs.umich.edu
1374259Sgblack@eecs.umich.edu            0x3: decode FUNCTION_LO {
1384259Sgblack@eecs.umich.edu                format IntOp {
1394259Sgblack@eecs.umich.edu                    0x0: mult({{
1404259Sgblack@eecs.umich.edu                        int64_t temp1 = Rs.sd * Rt.sd;
1414259Sgblack@eecs.umich.edu                        xc->setMiscReg(Hi,temp1<63:32>);
1424259Sgblack@eecs.umich.edu                        xc->setMiscReg(Lo,temp1<31:0>);
1434258Sgblack@eecs.umich.edu                    }});
1444257Sgblack@eecs.umich.edu
1454259Sgblack@eecs.umich.edu                    0x1: multu({{
1464259Sgblack@eecs.umich.edu                        uint64_t temp1 = Rs.ud * Rt.ud;
1474259Sgblack@eecs.umich.edu                        xc->setMiscReg(Hi,temp1<63:32>);
1484258Sgblack@eecs.umich.edu                        xc->setMiscReg(Lo,temp1<31:0>);
1494258Sgblack@eecs.umich.edu                    }});
1504258Sgblack@eecs.umich.edu
1514258Sgblack@eecs.umich.edu                    0x2: div({{
1524258Sgblack@eecs.umich.edu                        xc->setMiscReg(Hi,Rs.sw % Rt.sw);
1534103Ssaidi@eecs.umich.edu                        xc->setMiscReg(Lo,Rs.sw / Rt.sw);
1544259Sgblack@eecs.umich.edu                    }});
1554259Sgblack@eecs.umich.edu
1564259Sgblack@eecs.umich.edu                    0x3: divu({{
1574259Sgblack@eecs.umich.edu                        xc->setMiscReg(Hi,Rs.uw % Rt.uw);
1584258Sgblack@eecs.umich.edu                        xc->setMiscReg(Lo,Rs.uw / Rt.uw);
1594258Sgblack@eecs.umich.edu                    }});
1604258Sgblack@eecs.umich.edu                }
1614258Sgblack@eecs.umich.edu            }
1624258Sgblack@eecs.umich.edu
1634258Sgblack@eecs.umich.edu            0x4: decode HINT {
1644259Sgblack@eecs.umich.edu                0x0: decode FUNCTION_LO {
1654258Sgblack@eecs.umich.edu                    format IntOp {
1664258Sgblack@eecs.umich.edu                        0x0: add({{  Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}});
1674258Sgblack@eecs.umich.edu                        0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
1684258Sgblack@eecs.umich.edu                        0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
1694258Sgblack@eecs.umich.edu                        0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
1704258Sgblack@eecs.umich.edu                        0x4: and({{ Rd = Rs & Rt;}});
1714258Sgblack@eecs.umich.edu                        0x5: or({{ Rd = Rs | Rt;}});
1724259Sgblack@eecs.umich.edu                        0x6: xor({{ Rd = Rs ^ Rt;}});
1734259Sgblack@eecs.umich.edu                        0x7: nor({{ Rd = ~(Rs | Rt);}});
1744261Sgblack@eecs.umich.edu                    }
1754258Sgblack@eecs.umich.edu                }
1764258Sgblack@eecs.umich.edu            }
1774257Sgblack@eecs.umich.edu
1784261Sgblack@eecs.umich.edu            0x5: decode HINT {
1794261Sgblack@eecs.umich.edu                0x0: decode FUNCTION_LO {
1804261Sgblack@eecs.umich.edu                    format IntOp{
1814261Sgblack@eecs.umich.edu                        0x2: slt({{  Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
1824258Sgblack@eecs.umich.edu                        0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
1834258Sgblack@eecs.umich.edu                    }
1844258Sgblack@eecs.umich.edu                }
1854258Sgblack@eecs.umich.edu            }
1864258Sgblack@eecs.umich.edu
1874258Sgblack@eecs.umich.edu            0x6: decode FUNCTION_LO {
1884257Sgblack@eecs.umich.edu                format Trap {
1894259Sgblack@eecs.umich.edu                    0x0: tge({{  cond = (Rs.sw >= Rt.sw); }});
1904258Sgblack@eecs.umich.edu                    0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
1914258Sgblack@eecs.umich.edu                    0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
1924257Sgblack@eecs.umich.edu                    0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
1934261Sgblack@eecs.umich.edu                    0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
1944261Sgblack@eecs.umich.edu                    0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
1954261Sgblack@eecs.umich.edu                }
1964258Sgblack@eecs.umich.edu            }
1974260Sgblack@eecs.umich.edu        }
1984258Sgblack@eecs.umich.edu
1994258Sgblack@eecs.umich.edu        0x1: decode REGIMM_HI {
2004258Sgblack@eecs.umich.edu            0x0: decode REGIMM_LO {
2014258Sgblack@eecs.umich.edu                format Branch {
2024258Sgblack@eecs.umich.edu                    0x0: bltz({{ cond = (Rs.sw < 0); }});
2034257Sgblack@eecs.umich.edu                    0x1: bgez({{ cond = (Rs.sw >= 0); }});
2044259Sgblack@eecs.umich.edu                }
2054259Sgblack@eecs.umich.edu
2064258Sgblack@eecs.umich.edu                format BranchLikely {
2074258Sgblack@eecs.umich.edu                    //MIPS obsolete instructions
2084258Sgblack@eecs.umich.edu                    0x2: bltzl({{ cond = (Rs.sw < 0); }});
2094258Sgblack@eecs.umich.edu                    0x3: bgezl({{ cond = (Rs.sw >= 0); }});
2104258Sgblack@eecs.umich.edu                }
2114258Sgblack@eecs.umich.edu            }
2124258Sgblack@eecs.umich.edu
2134258Sgblack@eecs.umich.edu            0x1: decode REGIMM_LO {
2144257Sgblack@eecs.umich.edu                format Trap {
2154258Sgblack@eecs.umich.edu                    0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
2164260Sgblack@eecs.umich.edu                    0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
2174258Sgblack@eecs.umich.edu                    0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
2184258Sgblack@eecs.umich.edu                    0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
2194258Sgblack@eecs.umich.edu                    0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
2204258Sgblack@eecs.umich.edu                    0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
2214258Sgblack@eecs.umich.edu                }
2224258Sgblack@eecs.umich.edu            }
2234259Sgblack@eecs.umich.edu
2244259Sgblack@eecs.umich.edu            0x2: decode REGIMM_LO {
2254259Sgblack@eecs.umich.edu                format Branch {
2264259Sgblack@eecs.umich.edu                    0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn);
2274259Sgblack@eecs.umich.edu                    0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn);
2284259Sgblack@eecs.umich.edu                }
2294258Sgblack@eecs.umich.edu
2304258Sgblack@eecs.umich.edu                format BranchLikely {
2314257Sgblack@eecs.umich.edu                    //Will be removed in future MIPS releases
2324258Sgblack@eecs.umich.edu                    0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn);
2334258Sgblack@eecs.umich.edu                    0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn);
2344258Sgblack@eecs.umich.edu                }
2354258Sgblack@eecs.umich.edu            }
2364258Sgblack@eecs.umich.edu
2374257Sgblack@eecs.umich.edu            0x3: decode REGIMM_LO {
2384258Sgblack@eecs.umich.edu                format WarnUnimpl {
2394260Sgblack@eecs.umich.edu                    0x7: synci();
2404258Sgblack@eecs.umich.edu                }
2414258Sgblack@eecs.umich.edu            }
2424258Sgblack@eecs.umich.edu        }
2434257Sgblack@eecs.umich.edu
2444258Sgblack@eecs.umich.edu        format Jump {
2454260Sgblack@eecs.umich.edu            0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
2464258Sgblack@eecs.umich.edu
2474258Sgblack@eecs.umich.edu            0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn);
2484258Sgblack@eecs.umich.edu        }
2494257Sgblack@eecs.umich.edu
2504258Sgblack@eecs.umich.edu        format Branch {
2514260Sgblack@eecs.umich.edu            0x4: beq({{ cond = (Rs.sw == Rt.sw); }});
2524258Sgblack@eecs.umich.edu            0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
2534258Sgblack@eecs.umich.edu            0x6: decode RT {
2544258Sgblack@eecs.umich.edu                0x0: blez({{ cond = (Rs.sw <= 0); }});
2554258Sgblack@eecs.umich.edu            }
2564258Sgblack@eecs.umich.edu
2574257Sgblack@eecs.umich.edu            0x7: decode RT {
2584259Sgblack@eecs.umich.edu                0x0: bgtz({{ cond = (Rs.sw > 0); }});
2594259Sgblack@eecs.umich.edu            }
2604259Sgblack@eecs.umich.edu        }
2614259Sgblack@eecs.umich.edu    }
2624259Sgblack@eecs.umich.edu
2634259Sgblack@eecs.umich.edu    0x1: decode OPCODE_LO {
2644259Sgblack@eecs.umich.edu        format IntOp {
2654259Sgblack@eecs.umich.edu            0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
2664259Sgblack@eecs.umich.edu            0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
2674259Sgblack@eecs.umich.edu            0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
2684259Sgblack@eecs.umich.edu            0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }});
2694259Sgblack@eecs.umich.edu            0x4: andi({{ Rt.sw = Rs.sw & zextImm;}});
2704259Sgblack@eecs.umich.edu            0x5: ori({{ Rt.sw = Rs.sw | zextImm;}});
2714259Sgblack@eecs.umich.edu            0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}});
2724259Sgblack@eecs.umich.edu
2734257Sgblack@eecs.umich.edu            0x7: decode RS {
2744258Sgblack@eecs.umich.edu                0x0: lui({{ Rt = imm << 16}});
2754258Sgblack@eecs.umich.edu            }
2764258Sgblack@eecs.umich.edu        }
2774258Sgblack@eecs.umich.edu    }
2784258Sgblack@eecs.umich.edu
2794257Sgblack@eecs.umich.edu    0x2: decode OPCODE_LO {
2804257Sgblack@eecs.umich.edu
2814257Sgblack@eecs.umich.edu        //Table A-11 MIPS32 COP0 Encoding of rs Field
2824257Sgblack@eecs.umich.edu        0x0: decode RS_MSB {
2834257Sgblack@eecs.umich.edu            0x0: decode RS {
2844259Sgblack@eecs.umich.edu                format System {
2854259Sgblack@eecs.umich.edu                    0x0: mfc0({{
2864259Sgblack@eecs.umich.edu                        //uint64_t reg_num = Rd.uw;
2874259Sgblack@eecs.umich.edu
2884257Sgblack@eecs.umich.edu                        Rt = xc->readMiscReg(RD << 5 | SEL);
2894257Sgblack@eecs.umich.edu                    }});
2904257Sgblack@eecs.umich.edu
2914258Sgblack@eecs.umich.edu                    0x4: mtc0({{
2924258Sgblack@eecs.umich.edu                        //uint64_t reg_num = Rd.uw;
2934258Sgblack@eecs.umich.edu
2944257Sgblack@eecs.umich.edu                        xc->setMiscReg(RD << 5 | SEL,Rt);
2954259Sgblack@eecs.umich.edu                    }});
2964259Sgblack@eecs.umich.edu
2974259Sgblack@eecs.umich.edu                    0x8: mftr({{
2984259Sgblack@eecs.umich.edu                        //The contents of the coprocessor 0 register specified by the
2994259Sgblack@eecs.umich.edu                        //combination of rd and sel are loaded into general register
3004259Sgblack@eecs.umich.edu                        //rt. Note that not all coprocessor 0 registers support the
3014259Sgblack@eecs.umich.edu                        //sel field. In those instances, the sel field must be zero.
3024257Sgblack@eecs.umich.edu
3034257Sgblack@eecs.umich.edu                        //MT Code Needed Here
3044257Sgblack@eecs.umich.edu                    }});
3054257Sgblack@eecs.umich.edu
3064257Sgblack@eecs.umich.edu                    0xC: mttr({{
3074257Sgblack@eecs.umich.edu                        //The contents of the coprocessor 0 register specified by the
3084257Sgblack@eecs.umich.edu                        //combination of rd and sel are loaded into general register
3094257Sgblack@eecs.umich.edu                        //rt. Note that not all coprocessor 0 registers support the
3104257Sgblack@eecs.umich.edu                        //sel field. In those instances, the sel field must be zero.
3114259Sgblack@eecs.umich.edu
3124259Sgblack@eecs.umich.edu                        //MT Code Needed Here
3134257Sgblack@eecs.umich.edu                    }});
3144257Sgblack@eecs.umich.edu
3154259Sgblack@eecs.umich.edu
3164259Sgblack@eecs.umich.edu                    0xA: rdpgpr({{
3174259Sgblack@eecs.umich.edu                        //Accessing Previous Shadow Set Register Number
3184258Sgblack@eecs.umich.edu                        //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/;
3194257Sgblack@eecs.umich.edu                        //uint64_t reg_num = Rt.uw;
3204257Sgblack@eecs.umich.edu
3214259Sgblack@eecs.umich.edu                        //Rd = xc->regs.IntRegFile[prev];
3224259Sgblack@eecs.umich.edu                       //Rd = xc->shadowIntRegFile[prev][reg_num];
3234259Sgblack@eecs.umich.edu                    }});
3244259Sgblack@eecs.umich.edu
3254258Sgblack@eecs.umich.edu                    0xB: decode RD {
3264258Sgblack@eecs.umich.edu
3274258Sgblack@eecs.umich.edu                        0x0: decode SC {
3284258Sgblack@eecs.umich.edu                            0x0: dvpe({{
3294257Sgblack@eecs.umich.edu                                Rt.sw = xc->readMiscReg(MVPControl);
3304257Sgblack@eecs.umich.edu                                xc->setMiscReg(MVPControl,0);
3314259Sgblack@eecs.umich.edu                            }});
3324259Sgblack@eecs.umich.edu
3334258Sgblack@eecs.umich.edu                            0x1: evpe({{
3344258Sgblack@eecs.umich.edu                                Rt.sw = xc->readMiscReg(MVPControl);
3354258Sgblack@eecs.umich.edu                                xc->setMiscReg(MVPControl,1);
3364258Sgblack@eecs.umich.edu                            }});
3374258Sgblack@eecs.umich.edu                        }
3384258Sgblack@eecs.umich.edu
3394259Sgblack@eecs.umich.edu                        0x1: decode SC {
3404259Sgblack@eecs.umich.edu                            0x0: dmt({{
3414258Sgblack@eecs.umich.edu                                Rt.sw = xc->readMiscReg(VPEControl);
3424258Sgblack@eecs.umich.edu                                xc->setMiscReg(VPEControl,0);
3434258Sgblack@eecs.umich.edu                            }});
3444258Sgblack@eecs.umich.edu
3454258Sgblack@eecs.umich.edu                            0x1: emt({{
3464258Sgblack@eecs.umich.edu                                Rt.sw = xc->readMiscReg(VPEControl);
3474258Sgblack@eecs.umich.edu                                xc->setMiscReg(VPEControl,1);
3484258Sgblack@eecs.umich.edu                            }});
3494257Sgblack@eecs.umich.edu                        }
3504258Sgblack@eecs.umich.edu
3514257Sgblack@eecs.umich.edu                        0xC: decode SC {
3524259Sgblack@eecs.umich.edu                            0x0: di({{
3534257Sgblack@eecs.umich.edu                                Rt.sw = xc->readMiscReg(Status);
3544257Sgblack@eecs.umich.edu                                xc->setMiscReg(Status,0);
3554259Sgblack@eecs.umich.edu                            }});
3564257Sgblack@eecs.umich.edu
3574257Sgblack@eecs.umich.edu                            0x1: ei({{
3584257Sgblack@eecs.umich.edu                                Rt.sw = xc->readMiscReg(Status);
3594257Sgblack@eecs.umich.edu                                xc->setMiscReg(Status,1);
3604103Ssaidi@eecs.umich.edu                            }});
3611112SN/A                        }
362                    }
363
364                    0xE: wrpgpr({{
365                        //Accessing Previous Shadow Set Register Number
366                        //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/);
367                        //uint64_t reg_num = Rd.uw;
368
369                        //xc->regs.IntRegFile[prev];
370                        //xc->shadowIntRegFile[prev][reg_num] = Rt;
371                    }});
372                }
373            }
374
375            //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
376            0x1: decode FUNCTION {
377                format System {
378                    0x01: tlbr({{ }});
379                    0x02: tlbwi({{ }});
380                    0x06: tlbwr({{ }});
381                    0x08: tlbp({{ }});
382                }
383
384                format WarnUnimpl {
385                    0x18: eret();
386                    0x1F: deret();
387                    0x20: wait();
388                }
389            }
390        }
391
392        //Table A-13 MIPS32 COP1 Encoding of rs Field
393        0x1: decode RS_MSB {
394
395            0x0: decode RS_HI {
396                0x0: decode RS_LO {
397                    format WarnUnimpl {
398                        0x0: mfc1();//{{ /*Rt.uw = Fs.ud<31:0>;*/ }}
399                        0x3: mfhc1();// /*Rt.uw = Fs.ud<63:32>*/;
400                        0x4: mtc1();// /*Fs = Rt.uw*/
401                        0x7: mthc1();//{{/*Fs<63:32> = Rt.uw*/}}
402                    }
403
404                    format System {
405                        0x2: cfc1({{
406                            uint32_t fcsr_reg = xc->readMiscReg(FCSR);
407
408                            if (Fs == 0){
409                                Rt = xc->readMiscReg(FIR);
410                            } else if (Fs == 25) {
411                                Rt = 0 | (fcsr_reg & 0xFE000000) >> 24 | (fcsr_reg & 0x00800000) >> 23;
412                            } else if (Fs == 26) {
413                                Rt = 0 | (fcsr_reg & 0x0003F07C);
414                            } else if (Fs == 28) {
415                                Rt = 0 | (fcsr_reg);
416                            } else if (Fs == 31) {
417                                Rt = fcsr_reg;
418                            } else {
419                                panic("FP Control Value (%d) Not Available. Ignoring Access to"
420                                      "Floating Control Status Register",fcsr_reg);
421                            }
422
423                        }});
424
425                        0x6: ctc1({{
426                            /*xc->setMiscReg(FPCR[Fs],Rt);*/
427                        }});
428                    }
429                }
430
431                0x1: decode ND {
432                    0x0: decode TF {
433                        format Branch {
434                            0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }});
435                            0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }});
436                        }
437                    }
438
439                    0x1: decode TF {
440                        format BranchLikely {
441                            0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }});
442                            0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }});
443                        }
444                    }
445                }
446            }
447
448            0x1: decode RS_HI {
449                0x2: decode RS_LO {
450
451                    //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
452                    //(( single-word ))
453                    0x0: decode FUNCTION_HI {
454                        0x0: decode FUNCTION_LO {
455                            format FloatOp {
456                                0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}});
457                                0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}});
458                                0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}});
459                                0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}});
460                                0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}});
461                                0x5: abss({{ Fd.sf = fabs(Fs.sf);}});
462                                0x6: movs({{ Fd.sf = Fs.sf;}});
463                                0x7: negs({{ Fd.sf = -1 * Fs.sf;}});
464                            }
465                        }
466
467                        0x1: decode FUNCTION_LO {
468                            //only legal for 64 bit-FP
469                            format Float64Op {
470                                0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}});
471                                0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}});
472                                0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}});
473                                0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}});
474                            }
475
476                            format FloatOp {
477                                0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}});
478                                0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}});
479                                0x6: ceil_w_s({{  Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}});
480                                0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}});
481                            }
482                        }
483
484                        0x2: decode FUNCTION_LO {
485                            0x1: decode MOVCF {
486                                format FloatOp {
487                                    0x0: movfs({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }});
488                                    0x1: movts({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}});
489                                }
490                            }
491
492                            format BasicOp {
493                                0x2: movzs({{ if (Rt == 0) Fd = Fs; }});
494                                0x3: movns({{ if (Rt != 0) Fd = Fs; }});
495                            }
496
497                            format Float64Op {
498                                0x5: recips({{ Fd = 1 / Fs; }});
499                                0x6: rsqrts({{ Fd = 1 / sqrt((double)Fs.ud);}});
500                            }
501                        }
502
503                        0x4: decode FUNCTION_LO {
504
505                            format FloatOp {
506                                0x1: cvt_d_s({{ int rnd_mode = xc->readMiscReg(FCSR);
507                                Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
508                                }});
509
510                                0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR);
511                                Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
512                                }});
513                            }
514
515                            //only legal for 64 bit
516                            format Float64Op {
517                                0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR);
518                                Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
519                                }});
520
521                                0x6: cvt_ps_s({{ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/ }});
522                            }
523                        }
524                    }
525
526                    //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
527                    0x1: decode FUNCTION_HI {
528                        0x0: decode FUNCTION_LO {
529                            format FloatOp {
530                                0x0: addd({{ Fd.df = Fs.df + Ft.df;}});
531                                0x1: subd({{ Fd.df = Fs.df - Ft.df;}});
532                                0x2: muld({{ Fd.df = Fs.df * Ft.df;}});
533                                0x3: divd({{ Fd.df = Fs.df / Ft.df;}});
534                                0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}});
535                                0x5: absd({{ Fd.df = fabs(Fs.df);}});
536                                0x6: movd({{ Fd.df = Fs.df;}});
537                                0x7: negd({{ Fd.df = -1 * Fs.df;}});
538                            }
539                        }
540
541                        0x1: decode FUNCTION_LO {
542                            //only legal for 64 bit
543                            format Float64Op {
544                                0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
545                                0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}});
546                                0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}});
547                                0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}});
548                            }
549
550                            format FloatOp {
551                                0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
552                                0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }});
553                                0x6: ceil_w_d({{  Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }});
554                                0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }});
555                            }
556                        }
557
558                        0x2: decode FUNCTION_LO {
559                            0x1: decode MOVCF {
560                                format FloatOp {
561                                    0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }});
562                                    0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }});
563                                }
564                            }
565
566                            format BasicOp {
567                                0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }});
568                                0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }});
569                            }
570
571                            format Float64Op {
572                                0x5: recipd({{ Fd.df = 1 / Fs.df}});
573                                0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }});
574                            }
575                        }
576
577                        0x4: decode FUNCTION_LO {
578                            format FloatOp {
579                                0x0: cvt_s_d({{
580                                    int rnd_mode = xc->readMiscReg(FCSR);
581                                    Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE);
582                                }});
583
584                                0x4: cvt_w_d({{
585                                    int rnd_mode = xc->readMiscReg(FCSR);
586                                    Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE);
587                                }});
588                            }
589
590                            //only legal for 64 bit
591                            format Float64Op {
592                                0x5: cvt_l_d({{
593                                    int rnd_mode = xc->readMiscReg(FCSR);
594                                    Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE);
595                                }});
596                            }
597                        }
598                    }
599
600                    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
601                    0x4: decode FUNCTION {
602                        format FloatOp {
603                            0x20: cvt_s({{
604                                int rnd_mode = xc->readMiscReg(FCSR);
605                                Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD);
606                            }});
607
608                            0x21: cvt_d({{
609                                int rnd_mode = xc->readMiscReg(FCSR);
610                                Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD);
611                            }});
612                        }
613                    }
614
615                    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
616                    //Note: "1. Format type L is legal only if 64-bit floating point operations
617                    //are enabled."
618                    0x5: decode FUNCTION_HI {
619                        format FloatOp {
620                            0x10: cvt_s_l({{
621                                int rnd_mode = xc->readMiscReg(FCSR);
622                                Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG);
623                            }});
624
625                            0x11: cvt_d_l({{
626                                int rnd_mode = xc->readMiscReg(FCSR);
627                                Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG);
628                            }});
629                        }
630                    }
631
632                    //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
633                    //Note: "1. Format type PS is legal only if 64-bit floating point operations
634                    //are enabled. "
635                    0x6: decode FUNCTION_HI {
636                        0x0: decode FUNCTION_LO {
637                            format Float64Op {
638                                0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
639                                    //Lower Halves Independently but we take simulator shortcut
640                                    Fd.df = Fs.df + Ft.df;
641                                }});
642
643                                0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
644                                    //Lower Halves Independently but we take simulator shortcut
645                                    Fd.df = Fs.df - Ft.df;
646                                }});
647
648                                0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
649                                    //Lower Halves Independently but we take simulator shortcut
650                                    Fd.df = Fs.df * Ft.df;
651                                }});
652
653                                0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
654                                    //Lower Halves Independently but we take simulator shortcut
655                                    Fd.df = fabs(Fs.df);
656                                }});
657
658                                0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
659                                    //Lower Halves Independently but we take simulator shortcut
660                                    //Fd.df = Fs<31:0> |  Ft<31:0>;
661                                }});
662
663                                0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
664                                    //Lower Halves Independently but we take simulator shortcut
665                                    Fd.df = -1 * Fs.df;
666                                }});
667                            }
668                        }
669
670                        0x2: decode FUNCTION_LO {
671                            0x1: decode MOVCF {
672                                format Float64Op {
673                                    0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}});
674                                    0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}});
675                                }
676                            }
677
678                            format BasicOp {
679                                0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }});
680                                0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }});
681                            }
682
683                        }
684
685                        0x4: decode FUNCTION_LO {
686                            0x0: Float64Op::cvt_s_pu({{
687                                int rnd_mode = xc->readMiscReg(FCSR);
688                                Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI);
689                            }});
690                        }
691
692                        0x5: decode FUNCTION_LO {
693                            format Float64Op {
694                                0x0: cvt_s_pl({{
695                                    int rnd_mode = xc->readMiscReg(FCSR);
696                                    Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO);
697                                }});
698                                0x4: pll({{ /*Fd.df = Fs<31:0> | Ft<31:0>*/}});
699                                0x5: plu({{ /*Fd.df = Fs<31:0> | Ft<63:32>*/}});
700                                0x6: pul({{ /*Fd.df = Fs<63:32> | Ft<31:0>*/}});
701                                0x7: puu({{ /*Fd.df = Fs<63:32 | Ft<63:32>*/}});
702                            }
703                        }
704                    }
705                }
706            }
707        }
708
709        //Table A-19 MIPS32 COP2 Encoding of rs Field
710        0x2: decode RS_MSB {
711            0x0: decode RS_HI {
712                0x0: decode RS_LO {
713                    format WarnUnimpl {
714                        0x0: mfc2();
715                        0x2: cfc2();
716                        0x3: mfhc2();
717                        0x4: mtc2();
718                        0x6: ctc2();
719                        0x7: mftc2();
720                    }
721                }
722
723                0x1: decode ND {
724                    0x0: decode TF {
725                        format WarnUnimpl {
726                            0x0: bc2f();
727                            0x1: bc2t();
728                        }
729                    }
730
731                    0x1: decode TF {
732                        format WarnUnimpl {
733                            0x0: bc2fl();
734                            0x1: bc2tl();
735                        }
736                    }
737                }
738            }
739        }
740
741        //Table A-20 MIPS64 COP1X Encoding of Function Field 1
742        //Note: "COP1X instructions are legal only if 64-bit floating point
743        //operations are enabled."
744        0x3: decode FUNCTION_HI {
745            0x0: decode FUNCTION_LO {
746                format LoadMemory2 {
747                    0x0: lwxc1({{ EA = Rs + Rt; }},{{ /*F_t<31:0> = Mem.sf; */}});
748                    0x1: ldxc1({{ EA = Rs + Rt; }},{{ /*F_t<63:0> = Mem.df;*/ }});
749                    0x5: luxc1({{ //Need to make EA<2:0> = 0
750                        EA = Rs + Rt;
751                    }},
752                {{ /*F_t<31:0> = Mem.df; */}});
753                }
754            }
755
756            0x1: decode FUNCTION_LO {
757                format StoreMemory2 {
758                    0x0: swxc1({{ EA = Rs + Rt; }},{{ /*Mem.sf = Ft<31:0>; */}});
759                    0x1: sdxc1({{ EA = Rs + Rt; }},{{ /*Mem.df = Ft<63:0> */}});
760                    0x5: suxc1({{ //Need to make EA<2:0> = 0
761                        EA = Rs + Rt;
762                    }},
763                {{ /*Mem.df = F_t<63:0>;*/}});
764                }
765
766                0x7: WarnUnimpl::prefx();
767            }
768
769            format FloatOp {
770                0x3: WarnUnimpl::alnv_ps();
771
772                format BasicOp {
773                    0x4: decode FUNCTION_LO {
774                        0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }});
775                        0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }});
776                        0x6: madd_ps({{
777                            //Must Check for Exception Here... Supposed to Operate on Upper and
778                            //Lower Halves Independently but we take simulator shortcut
779                            Fd.df = (Fs.df * Fs.df) + Fr.df;
780                        }});
781                    }
782
783                    0x5: decode FUNCTION_LO {
784                        0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }});
785                        0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }});
786                        0x6: msub_ps({{
787                            //Must Check for Exception Here... Supposed to Operate on Upper and
788                            //Lower Halves Independently but we take simulator shortcut
789                            Fd.df = (Fs.df * Fs.df) - Fr.df;
790                        }});
791                    }
792
793                    0x6: decode FUNCTION_LO {
794                        0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
795                        0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }});
796                        0x6: nmadd_ps({{
797                            //Must Check for Exception Here... Supposed to Operate on Upper and
798                            //Lower Halves Independently but we take simulator shortcut
799                            Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
800                        }});
801                    }
802
803                    0x7: decode FUNCTION_LO {
804                        0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
805                        0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }});
806                        0x6: nmsub_ps({{
807                            //Must Check for Exception Here... Supposed to Operate on Upper and
808                            //Lower Halves Independently but we take simulator shortcut
809                            Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
810                        }});
811                    }
812                }
813            }
814        }
815
816        //MIPS obsolete instructions
817        format BranchLikely {
818            0x4: beql({{ cond = (Rs.sw == 0); }});
819            0x5: bnel({{ cond = (Rs.sw != 0); }});
820            0x6: blezl({{ cond = (Rs.sw <= 0); }});
821            0x7: bgtzl({{ cond = (Rs.sw > 0); }});
822        }
823    }
824
825    0x3: decode OPCODE_LO default FailUnimpl::reserved() {
826
827        //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
828        0x4: decode FUNCTION_HI {
829
830            0x0: decode FUNCTION_LO {
831                format IntOp {
832                    0x0: madd({{
833                        int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
834                        temp1 = temp1 + (Rs.sw * Rt.sw);
835                        xc->setMiscReg(Hi,temp1<63:32>);
836                        xc->setMiscReg(Lo,temp1<31:0>);
837                            }});
838
839                    0x1: maddu({{
840                        int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
841                        temp1 = temp1 + (Rs.uw * Rt.uw);
842                        xc->setMiscReg(Hi,temp1<63:32>);
843                        xc->setMiscReg(Lo,temp1<31:0>);
844                            }});
845
846                    0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; 	}});
847
848                    0x4: msub({{
849                        int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
850                        temp1 = temp1 - (Rs.sw * Rt.sw);
851                        xc->setMiscReg(Hi,temp1<63:32>);
852                        xc->setMiscReg(Lo,temp1<31:0>);
853                            }});
854
855                    0x5: msubu({{
856                        int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
857                        temp1 = temp1 - (Rs.uw * Rt.uw);
858                        xc->setMiscReg(Hi,temp1<63:32>);
859                        xc->setMiscReg(Lo,temp1<31:0>);
860                            }});
861                }
862            }
863
864            0x4: decode FUNCTION_LO {
865                format BasicOp {
866                    0x0: clz({{
867                        /*int cnt = 0;
868                        int idx = 0;
869                        while ( Rs.uw<idx> != 1) {
870                            cnt++;
871                            idx--;
872                        }
873
874                        Rd.uw = cnt;*/
875                    }});
876
877                    0x1: clo({{
878                        /*int cnt = 0;
879                        int idx = 0;
880                        while ( Rs.uw<idx> != 0) {
881                            cnt++;
882                            idx--;
883                        }
884
885                        Rd.uw = cnt;*/
886                    }});
887                }
888            }
889
890            0x7: decode FUNCTION_LO {
891                0x7: WarnUnimpl::sdbbp();
892            }
893        }
894
895        //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture
896        0x7: decode FUNCTION_HI {
897
898            0x0: decode FUNCTION_LO {
899                format FailUnimpl {
900                    0x1: ext();
901                    0x4: ins();
902                }
903            }
904
905            0x1: decode FUNCTION_LO {
906                format FailUnimpl {
907                    0x0: fork();
908                    0x1: yield();
909                }
910            }
911
912
913            //Table A-10 MIPS32 BSHFL Encoding of sa Field
914            0x4: decode SA {
915
916                0x02: FailUnimpl::wsbh();
917
918                format BasicOp {
919                    0x10: seb({{ Rd.sw = Rt<7:0>}});
920                    0x18: seh({{ Rd.sw = Rt<15:0>}});
921                }
922            }
923
924            0x6: decode FUNCTION_LO {
925                0x7: FailUnimpl::rdhwr();//{{ /*Rt = xc->hwRegs[RD];*/ }}
926            }
927        }
928    }
929
930    0x4: decode OPCODE_LO default FailUnimpl::reserved() {
931        format LoadMemory {
932            0x0: lb({{ Rt.sw = Mem.sb; }});
933            0x1: lh({{ Rt.sw = Mem.sh; }});
934
935            0x2: lwl({{
936                uint32_t mem_word = Mem.uw;
937                uint32_t unalign_addr = Rs + disp;
938                uint32_t offset = unalign_addr & 0x00000003;
939#if BYTE_ORDER == BIG_ENDIAN
940                std::cout << "Big Endian Byte Order\n";
941
942                switch(offset)
943                {
944                  case 0:
945                    Rt = mem_word;
946                    break;
947
948                  case 1:
949                    Rt &= 0x000F;
950                    Rt |= (mem_word << 4);
951                    break;
952
953                  case 2:
954                    Rt &= 0x00FF;
955                    Rt |= (mem_word << 8);
956                    break;
957
958                  case 3:
959                    Rt &= 0x0FFF;
960                    Rt |= (mem_word << 12);
961                    break;
962
963                  default:
964                    panic("lwl: bad offset");
965                }
966#elif BYTE_ORDER == LITTLE_ENDIAN
967                std::cout << "Little Endian Byte Order\n";
968
969                switch(offset)
970                {
971                  case 0:
972                    Rt &= 0x0FFF;
973                    Rt |= (mem_word << 12);
974                    break;
975
976                  case 1:
977                    Rt &= 0x00FF;
978                    Rt |= (mem_word << 8);
979                    break;
980
981                  case 2:
982                    Rt &= 0x000F;
983                    Rt |= (mem_word << 4);
984                    break;
985
986                  case 3:
987                    Rt = mem_word;
988                    break;
989
990                  default:
991                    panic("lwl: bad offset");
992                }
993#endif
994            }}, {{ EA = (Rs + disp) & ~3; }});
995
996            0x3: lw({{ Rt.sw = Mem.sw; }});
997            0x4: lbu({{ Rt.uw = Mem.ub; }});
998            0x5: lhu({{ Rt.uw = Mem.uh; }});
999            0x6: lwr({{
1000                uint32_t mem_word = Mem.uw;
1001                uint32_t unalign_addr = Rs + disp;
1002                uint32_t offset = unalign_addr & 0x00000003;
1003
1004#if BYTE_ORDER == BIG_ENDIAN
1005                switch(offset)
1006                {
1007                  case 0: Rt &= 0xFFF0;  Rt |= (mem_word >> 12); break;
1008                  case 1: Rt &= 0xFF00;  Rt |= (mem_word >> 8);  break;
1009                  case 2: Rt &= 0xF000;  Rt |= (mem_word >> 4);  break;
1010                  case 3: Rt = mem_word; break;
1011                  default: panic("lwr: bad offset");
1012                }
1013#elif BYTE_ORDER == LITTLE_ENDIAN
1014                switch(offset)
1015                {
1016                  case 0: Rt = mem_word; break;
1017                  case 1: Rt &= 0xF000;  Rt |= (mem_word >> 4);  break;
1018                  case 2: Rt &= 0xFF00;  Rt |= (mem_word >> 8);  break;
1019                  case 3: Rt &= 0xFFF0;  Rt |= (mem_word >> 12); break;
1020                  default: panic("lwr: bad offset");
1021                }
1022#endif
1023            }},
1024            {{ EA = (Rs + disp) & ~3; }});
1025        }
1026
1027        0x7: FailUnimpl::reserved();
1028    }
1029
1030    0x5: decode OPCODE_LO default FailUnimpl::reserved() {
1031        format StoreMemory {
1032            0x0: sb({{ Mem.ub = Rt<7:0>; }});
1033            0x1: sh({{ Mem.uh = Rt<15:0>; }});
1034            0x2: swl({{
1035                uint32_t mem_word = 0;
1036                uint32_t aligned_addr = (Rs + disp) & ~3;
1037                uint32_t unalign_addr = Rs + disp;
1038                uint32_t offset = unalign_addr & 0x00000003;
1039
1040                DPRINTF(IEW,"Execute: aligned=0x%x unaligned=0x%x\n offset=0x%x",
1041                        aligned_addr,unalign_addr,offset);
1042
1043                fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags);
1044
1045#if BYTE_ORDER == BIG_ENDIAN
1046                switch(offset)
1047                {
1048                  case 0:
1049                    Mem = Rt;
1050                    break;
1051
1052                  case 1:
1053                    mem_word &= 0xF000;
1054                    mem_word |= (Rt >> 4);
1055                    Mem = mem_word;
1056                    break;
1057
1058                  case 2:
1059                    mem_word &= 0xFF00;
1060                    mem_word |= (Rt >> 8);
1061                    Mem = mem_word;
1062                    break;
1063
1064                  case 3:
1065                    mem_word &= 0xFFF0;
1066                    mem_word |= (Rt >> 12);
1067                    Mem = mem_word;
1068                   break;
1069
1070                  default:
1071                    panic("swl: bad offset");
1072                }
1073#elif BYTE_ORDER == LITTLE_ENDIAN
1074                switch(offset)
1075                {
1076                  case 0:
1077                    mem_word &= 0xFFF0;
1078                    mem_word |= (Rt >> 12);
1079                    Mem = mem_word;
1080                    break;
1081
1082                  case 1:
1083                    mem_word &= 0xFF00;
1084                    mem_word |= (Rt >> 8);
1085                    Mem = mem_word;
1086                    break;
1087
1088                  case 2:
1089                    mem_word &= 0xF000;
1090                    mem_word |= (Rt >> 4);
1091                    Mem = mem_word;
1092                    break;
1093
1094                  case 3:
1095                    Mem = Rt;
1096                   break;
1097
1098                  default:
1099                    panic("swl: bad offset");
1100                }
1101#endif
1102            }},{{ EA = (Rs + disp) & ~3; }},mem_flags = NO_ALIGN_FAULT);
1103
1104            0x3: sw({{ Mem.uw = Rt<31:0>; }});
1105
1106            0x6: swr({{
1107                uint32_t mem_word = 0;
1108                uint32_t aligned_addr = (Rs + disp) & ~3;
1109                uint32_t unalign_addr = Rs + disp;
1110                uint32_t offset = unalign_addr & 0x00000003;
1111
1112                fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags);
1113
1114#if BYTE_ORDER == BIG_ENDIAN
1115                switch(offset)
1116                {
1117                  case 0:
1118                    mem_word &= 0x0FFF;
1119                    mem_word |= (Rt << 12);
1120                    Mem = mem_word;
1121                    break;
1122
1123                  case 1:
1124                    mem_word &= 0x00FF;
1125                    mem_word |= (Rt << 8);
1126                    Mem = mem_word;
1127                    break;
1128
1129                  case 2:
1130                    mem_word &= 0x000F;
1131                    mem_word |= (Rt << 4);
1132                    Mem = mem_word;
1133                    break;
1134
1135                  case 3:
1136                    Mem = Rt;
1137                    break;
1138
1139                  default:
1140                    panic("swr: bad offset");
1141                }
1142#elif BYTE_ORDER == LITTLE_ENDIAN
1143                switch(offset)
1144                {
1145                  case 0:
1146                    Mem = Rt;
1147                    break;
1148
1149                  case 1:
1150                    mem_word &= 0x000F;
1151                    mem_word |= (Rt << 4);
1152                    Mem = mem_word;
1153                    break;
1154
1155                  case 2:
1156                    mem_word &= 0x00FF;
1157                    mem_word |= (Rt << 8);
1158                    Mem = mem_word;
1159                    break;
1160
1161                  case 3:
1162                    mem_word &= 0x0FFF;
1163                    mem_word |= (Rt << 12);
1164                    Mem = mem_word;
1165                    break;
1166
1167                  default:
1168                    panic("swr: bad offset");
1169                }
1170#endif
1171            }},{{ EA = (Rs + disp) & ~3;}},mem_flags = NO_ALIGN_FAULT);
1172        }
1173
1174        format WarnUnimpl {
1175            0x7: cache();
1176        }
1177
1178    }
1179
1180    0x6: decode OPCODE_LO default FailUnimpl::reserved() {
1181        0x0: FailUnimpl::ll();
1182
1183        format LoadMemory {
1184            0x1: lwc1({{ /*F_t<31:0> = Mem.sf; */}});
1185            0x5: ldc1({{ /*F_t<63:0> = Mem.df; */}});
1186        }
1187    }
1188
1189
1190    0x7: decode OPCODE_LO default FailUnimpl::reserved() {
1191        0x0: FailUnimpl::sc();
1192
1193        format StoreMemory {
1194            0x1: swc1({{ //Mem.sf = Ft<31:0>; }});
1195            0x5: sdc1({{ //Mem.df = Ft<63:0>; }});
1196        }
1197    }
1198}
1199
1200
1201