decoder.isa revision 2241
11689SN/A// -*- mode:c++ -*- 28733Sgeoffrey.blake@arm.com 37598Sminkyu.jeong@arm.com//////////////////////////////////////////////////////////////////// 47598Sminkyu.jeong@arm.com// 57598Sminkyu.jeong@arm.com// The actual MIPS32 ISA decoder 67598Sminkyu.jeong@arm.com// ----------------------------- 77598Sminkyu.jeong@arm.com// The following instructions are specified in the MIPS32 ISA 87598Sminkyu.jeong@arm.com// Specification. Decoding closely follows the style specified 97598Sminkyu.jeong@arm.com// in the MIPS32 ISAthe specification document starting with Table 107598Sminkyu.jeong@arm.com// A-2 (document available @ www.mips.com) 117598Sminkyu.jeong@arm.com// 127598Sminkyu.jeong@arm.com//@todo: Distinguish "unknown/future" use insts from "reserved" 137598Sminkyu.jeong@arm.com// ones 142326SN/Adecode OPCODE_HI default Unknown::unknown() { 151689SN/A 161689SN/A // Derived From ... Table A-2 MIPS32 ISA Manual 171689SN/A 0x0: decode OPCODE_LO { 181689SN/A 191689SN/A 0x0: decode FUNCTION_HI { 201689SN/A 0x0: decode FUNCTION_LO { 211689SN/A 0x1: decode MOVCI { 221689SN/A format BasicOp { 231689SN/A 0: movf({{ if (xc->readMiscReg(FPCR,0) != CC) Rd = Rs}}); 241689SN/A 1: movt({{ if (xc->readMiscReg(FPCR,0) == CC) Rd = Rs}}); 251689SN/A } 261689SN/A } 271689SN/A 281689SN/A format BasicOp { 291689SN/A 301689SN/A //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 311689SN/A //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." 321689SN/A 331689SN/A 0x0: decode RS { 341689SN/A 0x0: decode RT default BasicOp::sll({{ Rd = Rt.uw << SA; }}) { 351689SN/A 0x0: decode RD{ 361689SN/A 0x0: decode HINT { 371689SN/A 0x0:nop({{}}); 381689SN/A 0x1:ssnop({{}}); 392665Ssaidi@eecs.umich.edu 0x3:ehb({{}}); 402665Ssaidi@eecs.umich.edu } 411689SN/A } 421689SN/A } 431060SN/A } 441060SN/A 451689SN/A 0x2: decode SRL { 461060SN/A 0: srl({{ Rd = Rt.uw >> SA; }}); 471060SN/A 481060SN/A //Hardcoded assuming 32-bit ISA, probably need parameter here 498230Snate@binkert.org 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 506658Snate@binkert.org } 518887Sgeoffrey.blake@arm.com 522292SN/A 0x3: sra({{ Rd = Rt.sw >> SA; }}); 531717SN/A 548229Snate@binkert.org 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 558232Snate@binkert.org 568232Snate@binkert.org 0x6: decode SRLV { 578232Snate@binkert.org 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 585529Snate@binkert.org 591060SN/A //Hardcoded assuming 32-bit ISA, probably need parameter here 606221Snate@binkert.org 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 616221Snate@binkert.org } 621681SN/A 635529Snate@binkert.org 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); 642873Sktlim@umich.edu } 654329Sktlim@umich.edu } 664329Sktlim@umich.edu 674329Sktlim@umich.edu 0x1: decode FUNCTION_LO { 682292SN/A 692292SN/A //Table A-3 Note: "Specific encodings of the hint field are used 702292SN/A //to distinguish JR from JR.HB and JALR from JALR.HB" 712292SN/A format Jump { 722820Sktlim@umich.edu 0x0: decode HINT { 732292SN/A 0:jr({{ NNPC = Rs & ~1; }},IsReturn); 742820Sktlim@umich.edu 752820Sktlim@umich.edu 1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn); 765529Snate@binkert.org } 772307SN/A 781060SN/A 0x1: decode HINT { 792292SN/A 0: jalr({{ NNPC = Rs; }},IsCall,IsReturn); 802292SN/A 812292SN/A 1: jalr_hb({{ NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn); 821060SN/A } 831060SN/A } 841060SN/A 851060SN/A format BasicOp { 861060SN/A 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 871060SN/A 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 881681SN/A } 896221Snate@binkert.org 906221Snate@binkert.org format WarnUnimpl { 916221Snate@binkert.org 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative 926221Snate@binkert.org 0x5: break(); 932292SN/A 0x7: sync(); 942292SN/A } 952820Sktlim@umich.edu } 962820Sktlim@umich.edu 972292SN/A 0x2: decode FUNCTION_LO { 982292SN/A format BasicOp { 992820Sktlim@umich.edu 0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }}); 1002820Sktlim@umich.edu 0x1: mthi({{ xc->setMiscReg(Hi,Rs); }}); 1012292SN/A 0x2: mflo({{ Rd = xc->readMiscReg(Lo); }}); 1022292SN/A 0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }}); 1032292SN/A } 1042292SN/A } 1052292SN/A 1062292SN/A 0x3: decode FUNCTION_LO { 1072292SN/A format IntOp { 1082292SN/A 0x0: mult({{ 1091060SN/A int64_t temp1 = Rs.sw * Rt.sw; 1101060SN/A xc->setMiscReg(Hi,temp1<63:32>); 1111681SN/A xc->setMiscReg(Lo,temp1<31:0>); 1121062SN/A }}); 1132292SN/A 1141062SN/A 0x1: multu({{ 1152301SN/A int64_t temp1 = Rs.uw * Rt.uw; 1162301SN/A xc->setMiscReg(Hi,temp1<63:32>); 1171062SN/A xc->setMiscReg(Lo,temp1<31:0>); 1182727Sktlim@umich.edu }}); 1191062SN/A 1201062SN/A 0x2: div({{ 1211062SN/A xc->setMiscReg(Hi,Rs.sw % Rt.sw); 1221062SN/A xc->setMiscReg(Lo,Rs.sw / Rt.sw); 1231062SN/A }}); 1241062SN/A 1251062SN/A 0x3: divu({{ 1261062SN/A xc->setMiscReg(Hi,Rs.uw % Rt.uw); 1271062SN/A xc->setMiscReg(Lo,Rs.uw / Rt.uw); 1281062SN/A }}); 1291062SN/A } 1301062SN/A } 1311062SN/A 1321062SN/A 0x4: decode FUNCTION_LO { 1331062SN/A format IntOp { 1341062SN/A 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}}); 1351062SN/A 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 1361062SN/A 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}}); 1371062SN/A 0x3: subu({{ Rd.sw = Rs.sw - Rt.uw;}}); 1381062SN/A 0x4: and({{ Rd = Rs & Rt;}}); 1391062SN/A 0x5: or({{ Rd = Rs | Rt;}}); 1401062SN/A 0x6: xor({{ Rd = Rs ^ Rt;}}); 1411062SN/A 0x7: nor({{ Rd = ~(Rs | Rt);}}); 1421062SN/A } 1431062SN/A } 1441062SN/A 1451062SN/A 0x5: decode FUNCTION_LO { 1461062SN/A format IntOp{ 1471062SN/A 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 1481062SN/A 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 1491062SN/A } 1501062SN/A } 1511062SN/A 1521062SN/A 0x6: decode FUNCTION_LO { 1531062SN/A format Trap { 1541062SN/A 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 1551062SN/A 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 1561062SN/A 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 1571062SN/A 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 1581062SN/A 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 1591062SN/A 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 1602292SN/A } 1612292SN/A } 1622292SN/A } 1632292SN/A 1641062SN/A 0x1: decode REGIMM_HI { 1651062SN/A 0x0: decode REGIMM_LO { 1661062SN/A format Branch { 1671062SN/A 0x0: bltz({{ cond = (Rs.sw < 0); }}); 1681062SN/A 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 1691062SN/A } 1701062SN/A 1712292SN/A format BranchLikely { 1722292SN/A //MIPS obsolete instructions 1732292SN/A 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 1742292SN/A 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 1752292SN/A } 1762292SN/A } 1772292SN/A 1782292SN/A 0x1: decode REGIMM_LO { 1792292SN/A format Trap { 1802292SN/A 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 1812301SN/A 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 1822727Sktlim@umich.edu 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 1832353SN/A 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 1842727Sktlim@umich.edu 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 1852727Sktlim@umich.edu 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 1862727Sktlim@umich.edu } 1876221Snate@binkert.org } 1882353SN/A 1892727Sktlim@umich.edu 0x2: decode REGIMM_LO { 1902727Sktlim@umich.edu format Branch { 1912727Sktlim@umich.edu 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn); 1922727Sktlim@umich.edu 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn); 1932353SN/A } 1942727Sktlim@umich.edu 1952727Sktlim@umich.edu format BranchLikely { 1962727Sktlim@umich.edu //Will be removed in future MIPS releases 1976221Snate@binkert.org 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn); 1988240Snate@binkert.org 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn); 1992301SN/A } 2002727Sktlim@umich.edu } 2012301SN/A 2022727Sktlim@umich.edu 0x3: decode REGIMM_LO { 2036221Snate@binkert.org format WarnUnimpl { 2048240Snate@binkert.org 0x7: synci(); 2052301SN/A } 2062727Sktlim@umich.edu } 2072301SN/A } 2082727Sktlim@umich.edu 2096221Snate@binkert.org format Jump { 2108240Snate@binkert.org 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 2112301SN/A 2122727Sktlim@umich.edu 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn); 2132301SN/A } 2142727Sktlim@umich.edu 2156221Snate@binkert.org format Branch { 2168240Snate@binkert.org 0x4: beq({{ cond = (Rs.sw == Rt.sw); }}); 2172301SN/A 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 2182727Sktlim@umich.edu 0x6: blez({{ cond = (Rs.sw <= 0); }}); 2192301SN/A 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 2202301SN/A } 2218240Snate@binkert.org } 2222301SN/A 2232727Sktlim@umich.edu 0x1: decode OPCODE_LO { 2242727Sktlim@umich.edu format IntOp { 2252727Sktlim@umich.edu 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}}); 2262727Sktlim@umich.edu 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 2278240Snate@binkert.org 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 2282727Sktlim@umich.edu 0x3: sltiu({{ Rt.sw = ( Rs.sw < imm ) ? 1 : 0 }}); 2292727Sktlim@umich.edu 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); 2302727Sktlim@umich.edu 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); 2312727Sktlim@umich.edu 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); 2322301SN/A 0x7: lui({{ Rt = INTIMM << 16}}); 2332301SN/A } 2346221Snate@binkert.org } 2358240Snate@binkert.org 2362301SN/A 0x2: decode OPCODE_LO { 2372727Sktlim@umich.edu 2382301SN/A //Table A-11 MIPS32 COP0 Encoding of rs Field 2392326SN/A 0x0: decode RS_MSB { 2406221Snate@binkert.org 0x0: decode RS { 2418240Snate@binkert.org format System { 2422301SN/A 0x0: mfc0({{ 2432727Sktlim@umich.edu //uint64_t reg_num = Rd.uw; 2442301SN/A 2452326SN/A Rt = xc->readMiscReg(RD << 5 | SEL); 2466221Snate@binkert.org }}); 2478240Snate@binkert.org 2482301SN/A 0x4: mtc0({{ 2492727Sktlim@umich.edu //uint64_t reg_num = Rd.uw; 2502301SN/A 2512326SN/A xc->setMiscReg(RD << 5 | SEL,Rt); 2526221Snate@binkert.org }}); 2538240Snate@binkert.org 2542301SN/A 0x8: mftr({{ 2552727Sktlim@umich.edu //The contents of the coprocessor 0 register specified by the 2562301SN/A //combination of rd and sel are loaded into general register 2572326SN/A //rt. Note that not all coprocessor 0 registers support the 2586221Snate@binkert.org //sel field. In those instances, the sel field must be zero. 2598240Snate@binkert.org 2602301SN/A //MT Code Needed Here 2612727Sktlim@umich.edu }}); 2622301SN/A 2632326SN/A 0xC: mttr({{ 2648240Snate@binkert.org //The contents of the coprocessor 0 register specified by the 2652301SN/A //combination of rd and sel are loaded into general register 2662727Sktlim@umich.edu //rt. Note that not all coprocessor 0 registers support the 2672301SN/A //sel field. In those instances, the sel field must be zero. 2682326SN/A 2692301SN/A //MT Code Needed Here 2702326SN/A }}); 2718240Snate@binkert.org 2722301SN/A 2732727Sktlim@umich.edu 0xA: rdpgpr({{ 2742301SN/A //Accessing Previous Shadow Set Register Number 2752326SN/A //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/; 2762301SN/A //uint64_t reg_num = Rt.uw; 2772326SN/A 2788240Snate@binkert.org //Rd = xc->regs.IntRegFile[prev]; 2792301SN/A //Rd = xc->shadowIntRegFile[prev][reg_num]; 2802727Sktlim@umich.edu }}); 2812326SN/A 2821062SN/A 0xB: decode RD { 2831062SN/A 2841681SN/A 0x0: decode SC { 2851060SN/A 0x0: dvpe({{ 2869427SAndreas.Sandberg@ARM.com int idx; 2871060SN/A int sel; 2886221Snate@binkert.org getMiscRegIdx(MVPControl,idx,sel); 2892292SN/A Rt.sw = xc->readMiscReg(idx,sel); 2902292SN/A xc->setMiscReg(idx,sel); 2912292SN/A }}); 2922292SN/A 2932292SN/A 0x1: evpe({{ 2942292SN/A int idx; 2952292SN/A int sel; 2962292SN/A getMiscRegIdx(MVPControl,idx,sel); 2972292SN/A Rt.sw = xc->readMiscReg(idx,sel); 2988887Sgeoffrey.blake@arm.com xc->setMiscReg(idx,sel,1); 2998733Sgeoffrey.blake@arm.com }}); 3008850Sandreas.hansson@arm.com } 3018887Sgeoffrey.blake@arm.com 3028733Sgeoffrey.blake@arm.com 0x1: decode SC { 3032733Sktlim@umich.edu 0x0: dmt({{ 3041060SN/A int idx; 3051060SN/A int sel; 3061681SN/A getMiscRegIdx(VPEControl,idx,sel); 3071060SN/A Rt.sw = xc->readMiscReg(idx,sel); 3082292SN/A xc->setMiscReg(idx,sel); 3091060SN/A }}); 3101060SN/A 3111060SN/A 0x1: emt({{ 3121060SN/A int idx; 3131060SN/A int sel; 3141060SN/A getMiscRegIdx(VPEControl,idx,sel); 3151060SN/A Rt.sw = xc->readMiscReg(idx,sel); 3161060SN/A xc->setMiscReg(idx,sel,1); 3171060SN/A }}); 3182292SN/A } 3192292SN/A 3201060SN/A 0xC: decode SC { 3211060SN/A 0x0: di({{ 3221060SN/A int idx; 3231060SN/A int sel; 3241681SN/A getMiscRegIdx(Status,idx,sel); 3251060SN/A Rt.sw = xc->readMiscReg(idx,sel); 3262292SN/A xc->setMiscReg(idx,sel); 3271060SN/A }}); 3281060SN/A 3291060SN/A 0x1: ei({{ 3301060SN/A int idx; 3311060SN/A int sel; 3321060SN/A getMiscRegIdx(Status,idx,sel); 3331060SN/A Rt.sw = xc->readMiscReg(idx,sel); 3341681SN/A xc->setMiscReg(idx,sel,1); 3351060SN/A }}); 3362292SN/A } 3371060SN/A } 3381060SN/A 3391060SN/A 0xE: wrpgpr({{ 3401060SN/A //Accessing Previous Shadow Set Register Number 3411060SN/A //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/); 3421060SN/A //uint64_t reg_num = Rd.uw; 3431060SN/A 3441681SN/A //xc->regs.IntRegFile[prev]; 3451060SN/A //xc->shadowIntRegFile[prev][reg_num] = Rt; 3466221Snate@binkert.org }}); 3471060SN/A } 3482292SN/A } 3492292SN/A 3502292SN/A //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 3512292SN/A 0x1: decode FUNCTION { 3521060SN/A format System { 3531060SN/A 0x01: tlbr({{ }}); 3541681SN/A 0x02: tlbwi({{ }}); 3551060SN/A 0x06: tlbwr({{ }}); 3562292SN/A 0x08: tlbp({{ }}); 3571060SN/A } 3582292SN/A 3591060SN/A format WarnUnimpl { 3601060SN/A 0x18: eret(); 3612307SN/A 0x1F: deret(); 3622863Sktlim@umich.edu 0x20: wait(); 3632843Sktlim@umich.edu } 3642307SN/A } 3652843Sktlim@umich.edu } 3662843Sktlim@umich.edu 3672863Sktlim@umich.edu //Table A-13 MIPS32 COP1 Encoding of rs Field 3681681SN/A 0x1: decode RS_MSB { 3691681SN/A 3702316SN/A 0x0: decode RS_HI { 3711681SN/A 0x0: decode RS_LO { 3722843Sktlim@umich.edu format FloatOp { 3732843Sktlim@umich.edu 0x0: mfc1({{ /*Rt.uw = Fs.ud<31:0>;*/ }}); 3742843Sktlim@umich.edu 0x2: cfc1({{ /*Rt.uw = xc->readMiscReg(FPCR[Fs]);*/}}); 3752843Sktlim@umich.edu 0x3: mfhc1({{ /*Rt.uw = Fs.ud<63:32>*/;}}); 3762843Sktlim@umich.edu 0x4: mtc1({{ /*Fs = Rt.uw*/}}); 3772843Sktlim@umich.edu 0x6: ctc1({{ /*xc->setMiscReg(FPCR[Fs],Rt);*/}}); 3782843Sktlim@umich.edu 0x7: mthc1({{ /*Fs<63:32> = Rt.uw*/}}); 3791681SN/A } 3802348SN/A } 3812307SN/A 3822367SN/A 0x1: decode ND { 3832367SN/A 0x0: decode TF { 3841681SN/A format Branch { 3852307SN/A 0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 3862307SN/A 0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 3872307SN/A } 3882307SN/A } 3896221Snate@binkert.org 3906221Snate@binkert.org 0x1: decode TF { 3916221Snate@binkert.org format BranchLikely { 3926221Snate@binkert.org 0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 3936221Snate@binkert.org 0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 3942307SN/A } 3951681SN/A } 3961681SN/A } 3972307SN/A } 3981681SN/A 3992307SN/A 0x1: decode RS_HI { 4001060SN/A 0x2: decode RS_LO { 4012348SN/A 4022307SN/A //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 4032307SN/A //(( single-word )) 4042307SN/A 0x0: decode RS_HI { 4052307SN/A 0x0: decode RS_LO { 4061060SN/A format FloatOp { 4072307SN/A 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); 4082307SN/A 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); 4098737Skoansin.tan@gmail.com 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); 4101060SN/A 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); 4119427SAndreas.Sandberg@ARM.com 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); 4122307SN/A 0x5: abss({{ Fd.sf = fabs(Fs.sf);}}); 4131060SN/A 0x6: movs({{ Fd.sf = Fs.sf;}}); 4146221Snate@binkert.org 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); 4156221Snate@binkert.org } 4166221Snate@binkert.org } 4176221Snate@binkert.org 4182307SN/A 0x1: decode RS_LO { 4191060SN/A //only legal for 64 bit-FP 4202307SN/A format Float64Op { 4212307SN/A 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}}); 4222873Sktlim@umich.edu 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}}); 4232307SN/A 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}}); 4241060SN/A 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}}); 4251060SN/A } 4261060SN/A 4271681SN/A format FloatOp { 4281060SN/A 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}}); 4296221Snate@binkert.org 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}}); 4302107SN/A 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}}); 4316221Snate@binkert.org 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}}); 4322107SN/A } 4332292SN/A } 4342292SN/A 4352107SN/A 0x2: decode RS_LO { 4362292SN/A 0x1: decode MOVCF { 4372326SN/A format FloatOp { 4382292SN/A 0x0: movfs({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); 4392107SN/A 0x1: movts({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); 4402292SN/A } 4412935Sksewell@umich.edu } 4424632Sgblack@eecs.umich.edu 4432935Sksewell@umich.edu format BasicOp { 4442292SN/A 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 4452292SN/A 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); 4462292SN/A } 4472292SN/A 4482292SN/A format Float64Op { 4492107SN/A 0x5: recips({{ Fd = 1 / Fs; }}); 4502292SN/A 0x6: rsqrts({{ Fd = 1 / sqrt((double)Fs.ud);}}); 4512107SN/A } 4522292SN/A } 4532292SN/A 4542107SN/A 0x4: decode RS_LO { 4552702Sktlim@umich.edu 4562107SN/A format FloatOp { 4572107SN/A 0x1: cvt_d_s({{ int rnd_mode = xc->readMiscReg(FCSR); 4582107SN/A Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE); 4592107SN/A }}); 4606221Snate@binkert.org 4612292SN/A 0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR); 4627720Sgblack@eecs.umich.edu Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE); 4637720Sgblack@eecs.umich.edu }}); 4642292SN/A } 4657852SMatt.Horsnell@arm.com 4667852SMatt.Horsnell@arm.com //only legal for 64 bit 4677852SMatt.Horsnell@arm.com format Float64Op { 4687852SMatt.Horsnell@arm.com 0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR); 4697852SMatt.Horsnell@arm.com Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE); 4702935Sksewell@umich.edu }}); 4717852SMatt.Horsnell@arm.com 4727852SMatt.Horsnell@arm.com 0x6: cvt_ps_s({{ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/ }}); 4732292SN/A } 4747852SMatt.Horsnell@arm.com } 4757852SMatt.Horsnell@arm.com } 4767852SMatt.Horsnell@arm.com 4772292SN/A //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 4787852SMatt.Horsnell@arm.com 0x1: decode RS_HI { 4797852SMatt.Horsnell@arm.com 0x0: decode RS_LO { 4807852SMatt.Horsnell@arm.com format FloatOp { 4812292SN/A 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 4822292SN/A 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 4832292SN/A 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 4842292SN/A 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 4856221Snate@binkert.org 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 4862292SN/A 0x5: absd({{ Fd.df = fabs(Fs.df);}}); 4878513SGiacomo.Gabrielli@arm.com 0x6: movd({{ Fd.df = Fs.df;}}); 4888513SGiacomo.Gabrielli@arm.com 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 4898513SGiacomo.Gabrielli@arm.com } 4908513SGiacomo.Gabrielli@arm.com } 4918513SGiacomo.Gabrielli@arm.com 4928513SGiacomo.Gabrielli@arm.com 0x1: decode RS_LO { 4938513SGiacomo.Gabrielli@arm.com //only legal for 64 bit 4948513SGiacomo.Gabrielli@arm.com format Float64Op { 4958513SGiacomo.Gabrielli@arm.com 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 4968513SGiacomo.Gabrielli@arm.com 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}}); 4978513SGiacomo.Gabrielli@arm.com 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}}); 4982292SN/A 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}}); 4997852SMatt.Horsnell@arm.com } 5008513SGiacomo.Gabrielli@arm.com 5018137SAli.Saidi@ARM.com format FloatOp { 5022292SN/A 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 5038513SGiacomo.Gabrielli@arm.com 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }}); 5048513SGiacomo.Gabrielli@arm.com 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }}); 5052292SN/A 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }}); 5067852SMatt.Horsnell@arm.com } 5077852SMatt.Horsnell@arm.com } 5082292SN/A 5092292SN/A 0x2: decode RS_LO { 5102292SN/A 0x1: decode MOVCF { 5112292SN/A format FloatOp { 5126221Snate@binkert.org 0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }}); 5132292SN/A 0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }}); 5142292SN/A } 5157720Sgblack@eecs.umich.edu } 5167852SMatt.Horsnell@arm.com 5177852SMatt.Horsnell@arm.com format BasicOp { 5187852SMatt.Horsnell@arm.com 0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }}); 5192292SN/A 0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }}); 5207852SMatt.Horsnell@arm.com } 5217852SMatt.Horsnell@arm.com 5228137SAli.Saidi@ARM.com format Float64Op { 5232292SN/A 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 5247852SMatt.Horsnell@arm.com 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 5257852SMatt.Horsnell@arm.com } 5262292SN/A } 5277852SMatt.Horsnell@arm.com 5282292SN/A 0x4: decode RS_LO { 5297852SMatt.Horsnell@arm.com format FloatOp { 5307852SMatt.Horsnell@arm.com 0x0: cvt_s_d({{ 5312292SN/A int rnd_mode = xc->readMiscReg(FCSR); 5322292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE); 5332292SN/A }}); 5342292SN/A 5356221Snate@binkert.org 0x4: cvt_w_d({{ 5362292SN/A int rnd_mode = xc->readMiscReg(FCSR); 5372292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE); 5382292SN/A }}); 5392292SN/A } 5402292SN/A 5412292SN/A //only legal for 64 bit 5422292SN/A format Float64Op { 5432292SN/A 0x5: cvt_l_d({{ 5442292SN/A int rnd_mode = xc->readMiscReg(FCSR); 5452292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE); 5462292SN/A }}); 5472292SN/A } 5482292SN/A } 5492292SN/A } 5502292SN/A 5512292SN/A //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 5522292SN/A 0x4: decode FUNCTION { 5532292SN/A format FloatOp { 5546221Snate@binkert.org 0x20: cvt_s({{ 5552292SN/A int rnd_mode = xc->readMiscReg(FCSR); 5562292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); 5572292SN/A }}); 5582292SN/A 5592292SN/A 0x21: cvt_d({{ 5602292SN/A int rnd_mode = xc->readMiscReg(FCSR); 5612292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); 5622292SN/A }}); 5632292SN/A } 5642292SN/A } 5652292SN/A 5662292SN/A //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 5672292SN/A //Note: "1. Format type L is legal only if 64-bit floating point operations 5682292SN/A //are enabled." 5692292SN/A 0x5: decode FUNCTION_HI { 5702292SN/A format FloatOp { 5712292SN/A 0x10: cvt_s_l({{ 5721060SN/A int rnd_mode = xc->readMiscReg(FCSR); 5731681SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG); 5741060SN/A }}); 5751060SN/A 5762292SN/A 0x11: cvt_d_l({{ 5772292SN/A int rnd_mode = xc->readMiscReg(FCSR); 5782292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG); 5792292SN/A }}); 5802292SN/A } 5812292SN/A } 5821681SN/A 5831681SN/A //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 5841060SN/A //Note: "1. Format type PS is legal only if 64-bit floating point operations 5852292SN/A //are enabled. " 5861060SN/A 0x6: decode RS_HI { 5872292SN/A 0x0: decode RS_LO { 5882292SN/A format Float64Op { 5891060SN/A 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 5902292SN/A //Lower Halves Independently but we take simulator shortcut 5912292SN/A Fd.df = Fs.df + Ft.df; 5922292SN/A }}); 5932292SN/A 5943221Sktlim@umich.edu 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 5953221Sktlim@umich.edu //Lower Halves Independently but we take simulator shortcut 5963221Sktlim@umich.edu Fd.df = Fs.df - Ft.df; 5973221Sktlim@umich.edu }}); 5983221Sktlim@umich.edu 5992292SN/A 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 6002292SN/A //Lower Halves Independently but we take simulator shortcut 6012292SN/A Fd.df = Fs.df * Ft.df; 6022292SN/A }}); 6032326SN/A 6042292SN/A 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 6052292SN/A //Lower Halves Independently but we take simulator shortcut 6062820Sktlim@umich.edu Fd.df = fabs(Fs.df); 6072292SN/A }}); 6082292SN/A 6092292SN/A 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 6102292SN/A //Lower Halves Independently but we take simulator shortcut 6112353SN/A //Fd.df = Fs<31:0> | Ft<31:0>; 6122292SN/A }}); 6132292SN/A 6142353SN/A 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 6152353SN/A //Lower Halves Independently but we take simulator shortcut 6162292SN/A Fd.df = -1 * Fs.df; 6172292SN/A }}); 6182292SN/A } 6192292SN/A } 6202292SN/A 6212292SN/A 0x2: decode RS_LO { 6222292SN/A 0x1: decode MOVCF { 6232292SN/A format Float64Op { 6242292SN/A 0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}}); 6252292SN/A 0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); 6262292SN/A } 6272292SN/A } 6282731Sktlim@umich.edu 6292292SN/A format BasicOp { 6302292SN/A 0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); 6312292SN/A 0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }}); 6322292SN/A } 6332292SN/A 6342292SN/A } 6352292SN/A 6362292SN/A 0x4: decode RS_LO { 6376221Snate@binkert.org 0x0: Float64Op::cvt_s_pu({{ 6382292SN/A int rnd_mode = xc->readMiscReg(FCSR); 6392292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI); 6402292SN/A }}); 6412292SN/A } 6422292SN/A 6432292SN/A 0x5: decode RS_LO { 6442292SN/A format Float64Op { 6452292SN/A 0x0: cvt_s_pl({{ 6467720Sgblack@eecs.umich.edu int rnd_mode = xc->readMiscReg(FCSR); 6472292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO); 6487720Sgblack@eecs.umich.edu }}); 6492292SN/A 0x4: pll({{ /*Fd.df = Fs<31:0> | Ft<31:0>*/}}); 6502292SN/A 0x5: plu({{ /*Fd.df = Fs<31:0> | Ft<63:32>*/}}); 6512292SN/A 0x6: pul({{ /*Fd.df = Fs<63:32> | Ft<31:0>*/}}); 6522292SN/A 0x7: puu({{ /*Fd.df = Fs<63:32 | Ft<63:32>*/}}); 6532292SN/A } 6542292SN/A } 6552292SN/A } 6562292SN/A } 6572292SN/A } 6582292SN/A } 6592292SN/A 6602292SN/A //Table A-19 MIPS32 COP2 Encoding of rs Field 6612292SN/A 0x2: decode RS_MSB { 6622292SN/A 0x0: decode RS_HI { 6636221Snate@binkert.org 0x0: decode RS_LO { 6646221Snate@binkert.org format WarnUnimpl { 6652292SN/A 0x0: mfc2(); 6663867Sbinkertn@umich.edu 0x2: cfc2(); 6676221Snate@binkert.org 0x3: mfhc2(); 6683867Sbinkertn@umich.edu 0x4: mtc2(); 6692292SN/A 0x6: ctc2(); 6702292SN/A 0x7: mftc2(); 6712292SN/A } 6722292SN/A } 6732292SN/A 6742292SN/A 0x1: decode ND { 6752292SN/A 0x0: decode TF { 6762292SN/A format WarnUnimpl { 6772292SN/A 0x0: bc2f(); 6782292SN/A 0x1: bc2t(); 6792292SN/A } 6806221Snate@binkert.org } 6816221Snate@binkert.org 6822292SN/A 0x1: decode TF { 6833867Sbinkertn@umich.edu format WarnUnimpl { 6846221Snate@binkert.org 0x0: bc2fl(); 6853867Sbinkertn@umich.edu 0x1: bc2tl(); 6863867Sbinkertn@umich.edu } 6872292SN/A } 6882292SN/A } 6892292SN/A } 6902292SN/A } 6911062SN/A 6921062SN/A //Table A-20 MIPS64 COP1X Encoding of Function Field 1 6931681SN/A //Note: "COP1X instructions are legal only if 64-bit floating point 6941062SN/A //operations are enabled." 6952292SN/A 0x3: decode FUNCTION_HI { 6961062SN/A 0x0: decode FUNCTION_LO { 6972292SN/A format LoadMemory2 { 6981062SN/A 0x0: lwxc1({{ EA = Rs + Rt; }},{{ /*F_t<31:0> = Mem.sf; */}}); 6996221Snate@binkert.org 0x1: ldxc1({{ EA = Rs + Rt; }},{{ /*F_t<63:0> = Mem.df;*/ }}); 7006221Snate@binkert.org 0x5: luxc1({{ //Need to make EA<2:0> = 0 7011062SN/A EA = Rs + Rt; 7023867Sbinkertn@umich.edu }}, 7036221Snate@binkert.org {{ /*F_t<31:0> = Mem.df; */}}); 7041062SN/A } 7052292SN/A } 7062292SN/A 7072292SN/A 0x1: decode FUNCTION_LO { 7082292SN/A format StoreMemory2 { 7092292SN/A 0x0: swxc1({{ EA = Rs + Rt; }},{{ /*Mem.sf = Ft<31:0>; */}}); 7101062SN/A 0x1: sdxc1({{ EA = Rs + Rt; }},{{ /*Mem.df = Ft<63:0> */}}); 7112292SN/A 0x5: suxc1({{ //Need to make EA<2:0> = 0 7122292SN/A EA = Rs + Rt; 7132292SN/A }}, 7147897Shestness@cs.utexas.edu {{ /*Mem.df = F_t<63:0>;*/}}); 7152292SN/A } 7162292SN/A 7172292SN/A 0x7: WarnUnimpl::prefx(); 7181062SN/A } 7192292SN/A 7201062SN/A format FloatOp { 7212292SN/A 0x3: WarnUnimpl::alnv_ps(); 7222292SN/A 7232292SN/A format BasicOp { 7242292SN/A 0x4: decode FUNCTION_LO { 7252292SN/A 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 7262292SN/A 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 7271062SN/A 0x6: madd_ps({{ 7282292SN/A //Must Check for Exception Here... Supposed to Operate on Upper and 7291062SN/A //Lower Halves Independently but we take simulator shortcut 7302292SN/A Fd.df = (Fs.df * Fs.df) + Fr.df; 7311062SN/A }}); 7321062SN/A } 7331062SN/A 7341681SN/A 0x5: decode FUNCTION_LO { 7351062SN/A 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 7362292SN/A 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 7371062SN/A 0x6: msub_ps({{ 7382292SN/A //Must Check for Exception Here... Supposed to Operate on Upper and 7392292SN/A //Lower Halves Independently but we take simulator shortcut 7402292SN/A Fd.df = (Fs.df * Fs.df) - Fr.df; 7411062SN/A }}); 7422292SN/A } 7432292SN/A 7446221Snate@binkert.org 0x6: decode FUNCTION_LO { 7452292SN/A 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 7462292SN/A 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 7472292SN/A 0x6: nmadd_ps({{ 7482292SN/A //Must Check for Exception Here... Supposed to Operate on Upper and 7491062SN/A //Lower Halves Independently but we take simulator shortcut 7502292SN/A Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 7512292SN/A }}); 7522292SN/A } 7532292SN/A 7542292SN/A 0x7: decode FUNCTION_LO { 7552292SN/A 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 7562292SN/A 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 7572292SN/A 0x6: nmsub_ps({{ 7586221Snate@binkert.org //Must Check for Exception Here... Supposed to Operate on Upper and 7592292SN/A //Lower Halves Independently but we take simulator shortcut 7602292SN/A Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 7612292SN/A }}); 7622292SN/A } 7632292SN/A } 7642292SN/A } 7652292SN/A } 7662292SN/A 7672292SN/A //MIPS obsolete instructions 7682292SN/A format BranchLikely { 7692292SN/A 0x4: beql({{ cond = (Rs.sw == 0); }}); 7702292SN/A 0x5: bnel({{ cond = (Rs.sw != 0); }}); 7712292SN/A 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 7722292SN/A 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 7732292SN/A } 7742292SN/A } 7752292SN/A 7762292SN/A 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 7772292SN/A 7782292SN/A //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 7792292SN/A 0x4: decode FUNCTION_HI { 7802292SN/A 7812292SN/A 0x0: decode FUNCTION_LO { 7822292SN/A format IntOp { 7832292SN/A 0x0: madd({{ 7842292SN/A int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 7852292SN/A temp1 = temp1 + (Rs.sw * Rt.sw); 7862292SN/A xc->setMiscReg(Hi,temp1<63:32>); 7872292SN/A xc->setMiscReg(Lo,temp1<31:0>); 7882292SN/A }}); 7892292SN/A 7902292SN/A 0x1: maddu({{ 7912292SN/A int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 7922292SN/A temp1 = temp1 + (Rs.uw * Rt.uw); 7932292SN/A xc->setMiscReg(Hi,temp1<63:32>); 7946221Snate@binkert.org xc->setMiscReg(Lo,temp1<31:0>); 7952292SN/A }}); 7962292SN/A 7972292SN/A 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 7982292SN/A 7992292SN/A 0x4: msub({{ 8002292SN/A int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 8012292SN/A temp1 = temp1 - (Rs.sw * Rt.sw); 8022292SN/A xc->setMiscReg(Hi,temp1<63:32>); 8032292SN/A xc->setMiscReg(Lo,temp1<31:0>); 8042292SN/A }}); 8052292SN/A 8062292SN/A 0x5: msubu({{ 8072292SN/A int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 8082292SN/A temp1 = temp1 - (Rs.uw * Rt.uw); 8092292SN/A xc->setMiscReg(Hi,temp1<63:32>); 8102292SN/A xc->setMiscReg(Lo,temp1<31:0>); 8112292SN/A }}); 8122292SN/A } 8132292SN/A } 8142292SN/A 8152292SN/A 0x4: decode FUNCTION_LO { 8162292SN/A format BasicOp { 8172292SN/A 0x0: clz({{ 8182292SN/A /*int cnt = 0; 8192292SN/A int idx = 0; 8202702Sktlim@umich.edu while ( Rs.uw<idx> != 1) { 8212292SN/A cnt++; 8222292SN/A idx--; 8232702Sktlim@umich.edu } 8242702Sktlim@umich.edu 8252292SN/A Rd.uw = cnt;*/ 8262292SN/A }}); 8272292SN/A 8282292SN/A 0x1: clo({{ 8292292SN/A /*int cnt = 0; 8302292SN/A int idx = 0; 8312292SN/A while ( Rs.uw<idx> != 0) { 8322292SN/A cnt++; 8332292SN/A idx--; 8342292SN/A } 8352292SN/A 8362292SN/A Rd.uw = cnt;*/ 8372292SN/A }}); 8382292SN/A } 8392292SN/A } 8402292SN/A 8412292SN/A 0x7: decode FUNCTION_LO { 8422292SN/A 0x7: WarnUnimpl::sdbbp(); 8432292SN/A } 8442292SN/A } 8452292SN/A 8462292SN/A //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 8472292SN/A 0x7: decode FUNCTION_HI { 8482292SN/A 8492292SN/A 0x0: decode FUNCTION_LO { 8502292SN/A format WarnUnimpl { 8512292SN/A 0x1: ext(); 8522292SN/A 0x4: ins(); 8532292SN/A } 8542292SN/A } 8552292SN/A 8562292SN/A 0x1: decode FUNCTION_LO { 8572292SN/A format WarnUnimpl { 8582292SN/A 0x0: fork(); 8592292SN/A 0x1: yield(); 8602292SN/A } 8612292SN/A } 8622292SN/A 8632292SN/A 8642326SN/A //Table A-10 MIPS32 BSHFL Encoding of sa Field 8656221Snate@binkert.org 0x4: decode SA { 8666221Snate@binkert.org 8672326SN/A 0x02: WarnUnimpl::wsbh(); 8682292SN/A 8692292SN/A format BasicOp { 8702292SN/A 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}}); 8712292SN/A 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}}); 8722292SN/A } 8732292SN/A } 8742292SN/A 8756221Snate@binkert.org 0x6: decode FUNCTION_LO { 8762702Sktlim@umich.edu 0x7: BasicOp::rdhwr({{ /*Rt = xc->hwRegs[RD];*/ }}); 8774632Sgblack@eecs.umich.edu } 8782935Sksewell@umich.edu } 8792702Sktlim@umich.edu } 8802935Sksewell@umich.edu 8812702Sktlim@umich.edu 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 8822702Sktlim@umich.edu format LoadMemory { 8832702Sktlim@umich.edu 0x0: lb({{ Rt.sw = Mem.sb; }}); 8842702Sktlim@umich.edu 0x1: lh({{ Rt.sw = Mem.sh; }}); 8852702Sktlim@umich.edu 0x2: lwl({{ Rt.sw = Mem.sw; }});//, WordAlign); 8862702Sktlim@umich.edu 0x3: lw({{ Rt.sw = Mem.sb; }}); 8872702Sktlim@umich.edu 0x4: lbu({{ Rt.uw = Mem.ub; }}); 8882702Sktlim@umich.edu 0x5: lhu({{ Rt.uw = Mem.uh; }}); 8892702Sktlim@umich.edu 0x6: lwr({{ Rt.uw = Mem.uw; }});//, WordAlign); 8902702Sktlim@umich.edu } 8912702Sktlim@umich.edu 8922702Sktlim@umich.edu 0x7: FailUnimpl::reserved(); 8932702Sktlim@umich.edu } 8942292SN/A 8952292SN/A 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 8962292SN/A format StoreMemory { 8972292SN/A 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 8982292SN/A 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 8992292SN/A 0x2: swl({{ Mem.ub = Rt<31:0>; }});//,WordAlign); 9002292SN/A 0x3: sw({{ Mem.ub = Rt<31:0>; }}); 9012292SN/A 0x6: swr({{ Mem.ub = Rt<31:0>; }});//,WordAlign); 9022292SN/A } 9032292SN/A 9042292SN/A format WarnUnimpl { 9052292SN/A 0x7: cache(); 9062292SN/A } 9072292SN/A 9082292SN/A } 9092292SN/A 9102292SN/A 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 9112292SN/A 0x0: WarnUnimpl::ll(); 9122733Sktlim@umich.edu 9132292SN/A format LoadMemory { 9142292SN/A 0x1: lwc1({{ /*F_t<31:0> = Mem.sf; */}}); 9152292SN/A 0x5: ldc1({{ /*F_t<63:0> = Mem.df; */}}); 9162292SN/A } 9172292SN/A } 9182292SN/A 9192292SN/A 9202733Sktlim@umich.edu 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 9212292SN/A 0x0: WarnUnimpl::sc(); 9222292SN/A 9232292SN/A format StoreMemory { 9242292SN/A 0x1: swc1({{ //Mem.sf = Ft<31:0>; }}); 9256221Snate@binkert.org 0x5: sdc1({{ //Mem.df = Ft<63:0>; }}); 9262292SN/A } 9272292SN/A } 9282292SN/A} 9292292SN/A 9302292SN/A 9312292SN/A