decoder.isa revision 2124
11049Sbinkertn@umich.edu// -*- mode:c++ -*- 21758Ssaidi@eecs.umich.edu 31758Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 41758Ssaidi@eecs.umich.edu// 51758Ssaidi@eecs.umich.edu// The actual MIPS32 ISA decoder 61758Ssaidi@eecs.umich.edu// ----------------------------- 71758Ssaidi@eecs.umich.edu// The following instructions are specified in the MIPS32 ISA 81758Ssaidi@eecs.umich.edu// Specification. Decoding closely follows the style specified 91758Ssaidi@eecs.umich.edu// in the MIPS32 ISAthe specification document starting with Table 101758Ssaidi@eecs.umich.edu// A-2 (document available @ www.mips.com) 111758Ssaidi@eecs.umich.edu// 121758Ssaidi@eecs.umich.edu//@todo: Distinguish "unknown/future" use insts from "reserved" 131758Ssaidi@eecs.umich.edu// ones 141758Ssaidi@eecs.umich.edudecode OPCODE_HI default Unknown::unknown() { 151758Ssaidi@eecs.umich.edu 161758Ssaidi@eecs.umich.edu // Derived From ... Table A-2 MIPS32 ISA Manual 171758Ssaidi@eecs.umich.edu 0x0: decode OPCODE_LO { 181758Ssaidi@eecs.umich.edu 191758Ssaidi@eecs.umich.edu 0x0: decode FUNCTION_HI { 201758Ssaidi@eecs.umich.edu 0x0: decode FUNCTION_LO { 211758Ssaidi@eecs.umich.edu 0x1: decode MOVCI { 221758Ssaidi@eecs.umich.edu format BasicOp { 231758Ssaidi@eecs.umich.edu 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}}); 241758Ssaidi@eecs.umich.edu 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}}); 251758Ssaidi@eecs.umich.edu } 261758Ssaidi@eecs.umich.edu } 271758Ssaidi@eecs.umich.edu 281758Ssaidi@eecs.umich.edu format BasicOp { 291049Sbinkertn@umich.edu 301318Ssaidi@eecs.umich.edu //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 311049Sbinkertn@umich.edu //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." 321049Sbinkertn@umich.edu 331049Sbinkertn@umich.edu 0x0: sll({{ Rd = Rt.uw << SA; }}); 341881Sbinkertn@umich.edu 351331Ssaidi@eecs.umich.edu 0x2: decode SRL { 361331Ssaidi@eecs.umich.edu 0: srl({{ Rd = Rt.uw >> SA; }}); 371331Ssaidi@eecs.umich.edu 381331Ssaidi@eecs.umich.edu //Hardcoded assuming 32-bit ISA, probably need parameter here 391331Ssaidi@eecs.umich.edu 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 401331Ssaidi@eecs.umich.edu } 411331Ssaidi@eecs.umich.edu 421331Ssaidi@eecs.umich.edu 0x3: sra({{ Rd = Rt.sw >> SA; }}); 431331Ssaidi@eecs.umich.edu 441331Ssaidi@eecs.umich.edu 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 451331Ssaidi@eecs.umich.edu 461331Ssaidi@eecs.umich.edu 0x6: decode SRLV { 471331Ssaidi@eecs.umich.edu 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 481596Ssaidi@eecs.umich.edu 491596Ssaidi@eecs.umich.edu //Hardcoded assuming 32-bit ISA, probably need parameter here 501596Ssaidi@eecs.umich.edu 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 511049Sbinkertn@umich.edu } 521049Sbinkertn@umich.edu 531049Sbinkertn@umich.edu 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); 541049Sbinkertn@umich.edu } 551049Sbinkertn@umich.edu } 561049Sbinkertn@umich.edu 571049Sbinkertn@umich.edu 0x1: decode FUNCTION_LO { 581049Sbinkertn@umich.edu 591049Sbinkertn@umich.edu //Table A-3 Note: "Specific encodings of the hint field are used 601049Sbinkertn@umich.edu //to distinguish JR from JR.HB and JALR from JALR.HB" 611049Sbinkertn@umich.edu format Jump { 621049Sbinkertn@umich.edu 0x0: decode HINT { 631049Sbinkertn@umich.edu 0:jr({{ NNPC = Rs; }},IsReturn); 641049Sbinkertn@umich.edu 651049Sbinkertn@umich.edu 1:jr_hb({{ NNPC = Rs; clear_exe_inst_hazards(); }},IsReturn); 661049Sbinkertn@umich.edu } 671049Sbinkertn@umich.edu 681049Sbinkertn@umich.edu 0x1: decode HINT { 691049Sbinkertn@umich.edu 0: jalr({{ NNPC = Rs; }},IsCall,IsReturn); 701049Sbinkertn@umich.edu 711049Sbinkertn@umich.edu 1: jalr_hb({{ NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn); 721049Sbinkertn@umich.edu } 731049Sbinkertn@umich.edu } 741049Sbinkertn@umich.edu 751049Sbinkertn@umich.edu format BasicOp { 761049Sbinkertn@umich.edu 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 771049Sbinkertn@umich.edu 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 781049Sbinkertn@umich.edu } 791049Sbinkertn@umich.edu 801049Sbinkertn@umich.edu format WarnUnimpl { 811049Sbinkertn@umich.edu 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative 821049Sbinkertn@umich.edu 0x5: break(); 831049Sbinkertn@umich.edu 0x7: sync(); 841049Sbinkertn@umich.edu } 851049Sbinkertn@umich.edu } 861049Sbinkertn@umich.edu 871049Sbinkertn@umich.edu 0x2: decode FUNCTION_LO { 881049Sbinkertn@umich.edu format BasicOp { 891049Sbinkertn@umich.edu 0x0: mfhi({{ Rd = xc->miscRegs.hi; }}); 901049Sbinkertn@umich.edu 0x1: mthi({{ xc->miscRegs.hi = Rs; }}); 911049Sbinkertn@umich.edu 0x2: mflo({{ Rd = xc->miscRegs.lo; }}); 921049Sbinkertn@umich.edu 0x3: mtlo({{ xc->miscRegs.lo = Rs; }}); 931049Sbinkertn@umich.edu } 941049Sbinkertn@umich.edu } 951049Sbinkertn@umich.edu 961049Sbinkertn@umich.edu 0x3: decode FUNCTION_LO { 971049Sbinkertn@umich.edu format IntOp { 981049Sbinkertn@umich.edu 0x0: mult({{ 991049Sbinkertn@umich.edu INT64 temp1 = Rs.sw * Rt.sw; 1001049Sbinkertn@umich.edu xc->miscRegs.hi->temp1<63:32>; 1011929Sbinkertn@umich.edu xc->miscRegs.lo->temp1<31:0>; 1021929Sbinkertn@umich.edu }}); 1031929Sbinkertn@umich.edu 1041929Sbinkertn@umich.edu 0x1: multu({{ 1051929Sbinkertn@umich.edu INT64 temp1 = Rs.uw * Rt.uw; 1061929Sbinkertn@umich.edu xc->miscRegs.hi->temp1<63:32>; 1071929Sbinkertn@umich.edu xc->miscRegs.lo->temp1<31:0> 1081929Sbinkertn@umich.edu Rd.sw = Rs.uw * Rt.uw; 1091049Sbinkertn@umich.edu }}); 1101929Sbinkertn@umich.edu 1111929Sbinkertn@umich.edu 0x2: div({{ 1121049Sbinkertn@umich.edu xc->miscRegs.hi = Rs.sw % Rt.sw; 1131049Sbinkertn@umich.edu xc->miscRegs.lo = Rs.sw / Rt.sw; 1141929Sbinkertn@umich.edu }}); 1151049Sbinkertn@umich.edu 1161049Sbinkertn@umich.edu 0x3: divu({{ 1171049Sbinkertn@umich.edu xc->miscRegs.hi = Rs.uw % Rt.uw; 1181929Sbinkertn@umich.edu xc->miscRegs.lo = Rs.uw / Rt.uw; 1191049Sbinkertn@umich.edu }}); 1201049Sbinkertn@umich.edu } 1211049Sbinkertn@umich.edu } 1221049Sbinkertn@umich.edu 1231049Sbinkertn@umich.edu 0x4: decode FUNCTION_LO { 1241049Sbinkertn@umich.edu format IntOp { 1251049Sbinkertn@umich.edu 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}}); 1261049Sbinkertn@umich.edu 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}}); 1271049Sbinkertn@umich.edu 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}}); 1281049Sbinkertn@umich.edu 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}}); 1291049Sbinkertn@umich.edu 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}}); 1301929Sbinkertn@umich.edu 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}}); 1311049Sbinkertn@umich.edu 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}}); 1321049Sbinkertn@umich.edu 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}}); 1331881Sbinkertn@umich.edu } 1341881Sbinkertn@umich.edu } 1351929Sbinkertn@umich.edu 1361881Sbinkertn@umich.edu 0x5: decode FUNCTION_LO { 1371929Sbinkertn@umich.edu format IntOp{ 1381881Sbinkertn@umich.edu 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 1391881Sbinkertn@umich.edu 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 1401881Sbinkertn@umich.edu } 1411881Sbinkertn@umich.edu } 1421881Sbinkertn@umich.edu 1431881Sbinkertn@umich.edu 0x6: decode FUNCTION_LO { 1441881Sbinkertn@umich.edu format Trap { 1451929Sbinkertn@umich.edu 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 1461881Sbinkertn@umich.edu 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 1471929Sbinkertn@umich.edu 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 1481881Sbinkertn@umich.edu 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 1491881Sbinkertn@umich.edu 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 1501881Sbinkertn@umich.edu 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 1511881Sbinkertn@umich.edu } 1521881Sbinkertn@umich.edu } 1531881Sbinkertn@umich.edu } 1541881Sbinkertn@umich.edu 1551929Sbinkertn@umich.edu 0x1: decode REGIMM_HI { 1561881Sbinkertn@umich.edu 0x0: decode REGIMM_LO { 1571929Sbinkertn@umich.edu format Branch { 1581881Sbinkertn@umich.edu 0x0: bltz({{ cond = (Rs.sw < 0); }}); 1591881Sbinkertn@umich.edu 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 1601881Sbinkertn@umich.edu } 1611881Sbinkertn@umich.edu 1621881Sbinkertn@umich.edu format BranchLikely { 1631881Sbinkertn@umich.edu //MIPS obsolete instructions 1641881Sbinkertn@umich.edu 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 1651881Sbinkertn@umich.edu 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 1661881Sbinkertn@umich.edu } 1671929Sbinkertn@umich.edu } 1681881Sbinkertn@umich.edu 1691881Sbinkertn@umich.edu 0x1: decode REGIMM_LO { 1701309Ssaidi@eecs.umich.edu format Trap { 1711331Ssaidi@eecs.umich.edu 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 1721331Ssaidi@eecs.umich.edu 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 1731331Ssaidi@eecs.umich.edu 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 1741331Ssaidi@eecs.umich.edu 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 1751331Ssaidi@eecs.umich.edu 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 1761331Ssaidi@eecs.umich.edu 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 1771331Ssaidi@eecs.umich.edu } 1781929Sbinkertn@umich.edu } 1791929Sbinkertn@umich.edu 1801331Ssaidi@eecs.umich.edu 0x2: decode REGIMM_LO { 1811881Sbinkertn@umich.edu format Branch { 1821957Ssaidi@eecs.umich.edu 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsLink); 1831881Sbinkertn@umich.edu 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsLink); 1841881Sbinkertn@umich.edu } 1851881Sbinkertn@umich.edu 1861309Ssaidi@eecs.umich.edu format BranchLikely { 1871309Ssaidi@eecs.umich.edu //Will be removed in future MIPS releases 1881309Ssaidi@eecs.umich.edu 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsLink); 1891881Sbinkertn@umich.edu 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsLink); 1901881Sbinkertn@umich.edu } 1911881Sbinkertn@umich.edu } 1921957Ssaidi@eecs.umich.edu 1931309Ssaidi@eecs.umich.edu 0x3: decode REGIMM_LO { 1941309Ssaidi@eecs.umich.edu format WarnUnimpl { 1951309Ssaidi@eecs.umich.edu 0x7: synci(); 1961929Sbinkertn@umich.edu } 1971309Ssaidi@eecs.umich.edu } 1981309Ssaidi@eecs.umich.edu } 1991929Sbinkertn@umich.edu 2001331Ssaidi@eecs.umich.edu format Jump { 2011317Ssaidi@eecs.umich.edu 0x2: j({{ NNPC = (NPC & 0xF0000000) & (0x00000000 & JMPTARG << 2);}}); 2021317Ssaidi@eecs.umich.edu 2031318Ssaidi@eecs.umich.edu 0x3: jal({{ NNPC = (NPC & 0xF0000000) & (0x00000000 & JMPTARG << 2);}},IsCall,IsReturn); 2041318Ssaidi@eecs.umich.edu } 2051331Ssaidi@eecs.umich.edu 2061929Sbinkertn@umich.edu format Branch { 2071331Ssaidi@eecs.umich.edu 0x4: beq({{ cond = (Rs.sw == 0); }}); 2081331Ssaidi@eecs.umich.edu 0x5: bne({{ cond = (Rs.sw != 0); }}); 2091331Ssaidi@eecs.umich.edu 0x6: blez({{ cond = (Rs.sw <= 0); }}); 2101331Ssaidi@eecs.umich.edu 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 2111331Ssaidi@eecs.umich.edu } 2121331Ssaidi@eecs.umich.edu } 2131309Ssaidi@eecs.umich.edu 2141331Ssaidi@eecs.umich.edu 0x1: decode OPCODE_LO { 2151929Sbinkertn@umich.edu format IntOp { 2161929Sbinkertn@umich.edu 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }}); 2171331Ssaidi@eecs.umich.edu 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}}); 2181331Ssaidi@eecs.umich.edu 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }}); 2191929Sbinkertn@umich.edu 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }}); 2201929Sbinkertn@umich.edu 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); 2211331Ssaidi@eecs.umich.edu 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); 2221331Ssaidi@eecs.umich.edu 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); 2231331Ssaidi@eecs.umich.edu 0x7: lui({{ Rt = INTIMM << 16}}); 2241929Sbinkertn@umich.edu } 2251929Sbinkertn@umich.edu } 2261309Ssaidi@eecs.umich.edu 2271317Ssaidi@eecs.umich.edu 0x2: decode OPCODE_LO { 2281317Ssaidi@eecs.umich.edu 2291318Ssaidi@eecs.umich.edu //Table A-11 MIPS32 COP0 Encoding of rs Field 2301318Ssaidi@eecs.umich.edu 0x0: decode RS_MSB { 2311318Ssaidi@eecs.umich.edu 0x0: decode RS { 2321331Ssaidi@eecs.umich.edu format BasicOp { 2331881Sbinkertn@umich.edu 0x0: mfc0({{ 2341881Sbinkertn@umich.edu //The contents of the coprocessor 0 register specified by the 2351881Sbinkertn@umich.edu //combination of rd and sel are loaded into general register 2361881Sbinkertn@umich.edu //rt. Note that not all coprocessor 0 registers support the 2371331Ssaidi@eecs.umich.edu //sel field. In those instances, the sel field must be zero. 2381881Sbinkertn@umich.edu 2391881Sbinkertn@umich.edu if (SEL > 0) 2401881Sbinkertn@umich.edu panic("Can't Handle Cop0 with register select yet\n"); 2411881Sbinkertn@umich.edu 2421331Ssaidi@eecs.umich.edu uint64_t reg_num = Rd.uw; 2431881Sbinkertn@umich.edu 2441881Sbinkertn@umich.edu Rt = xc->miscRegs.cop0[reg_num]; 2451881Sbinkertn@umich.edu }}); 2461881Sbinkertn@umich.edu 2471309Ssaidi@eecs.umich.edu 0x4: mtc0({{ 2481309Ssaidi@eecs.umich.edu //The contents of the coprocessor 0 register specified by the 2491881Sbinkertn@umich.edu //combination of rd and sel are loaded into general register 2501881Sbinkertn@umich.edu //rt. Note that not all coprocessor 0 registers support the 2511049Sbinkertn@umich.edu //sel field. In those instances, the sel field must be zero. 2521049Sbinkertn@umich.edu 2532005Sbinkertn@umich.edu if (SEL > 0) 2541881Sbinkertn@umich.edu panic("Can't Handle Cop0 with register select yet\n"); 2551881Sbinkertn@umich.edu 2561049Sbinkertn@umich.edu uint64_t reg_num = Rd.uw; 2571881Sbinkertn@umich.edu 2581881Sbinkertn@umich.edu xc->miscRegs.cop0[reg_num] = Rt; 2591881Sbinkertn@umich.edu }}); 2601929Sbinkertn@umich.edu 2611881Sbinkertn@umich.edu 0x8: mftr({{ 2622006Sbinkertn@umich.edu //The contents of the coprocessor 0 register specified by the 2632006Sbinkertn@umich.edu //combination of rd and sel are loaded into general register 2642006Sbinkertn@umich.edu //rt. Note that not all coprocessor 0 registers support the 2651881Sbinkertn@umich.edu //sel field. In those instances, the sel field must be zero. 2661881Sbinkertn@umich.edu 2671049Sbinkertn@umich.edu //MT Code Needed Here 2681049Sbinkertn@umich.edu }}); 2691049Sbinkertn@umich.edu 2701881Sbinkertn@umich.edu 0xC: mttr({{ 2711929Sbinkertn@umich.edu //The contents of the coprocessor 0 register specified by the 2721881Sbinkertn@umich.edu //combination of rd and sel are loaded into general register 2731881Sbinkertn@umich.edu //rt. Note that not all coprocessor 0 registers support the 2741881Sbinkertn@umich.edu //sel field. In those instances, the sel field must be zero. 2751049Sbinkertn@umich.edu 2761881Sbinkertn@umich.edu //MT Code Needed Here 2772006Sbinkertn@umich.edu }}); 2782006Sbinkertn@umich.edu 2792006Sbinkertn@umich.edu 2802006Sbinkertn@umich.edu 0xA: rdpgpr({{ 2812006Sbinkertn@umich.edu //Accessing Previous Shadow Set Register Number 2821301Ssaidi@eecs.umich.edu uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 2831049Sbinkertn@umich.edu uint64_t reg_num = Rt.uw; 2841049Sbinkertn@umich.edu 2851049Sbinkertn@umich.edu Rd = xc->shadowIntRegFile[prev][reg_num]; 2861049Sbinkertn@umich.edu }}); 2871049Sbinkertn@umich.edu 2881929Sbinkertn@umich.edu 0xB: decode RD { 2891929Sbinkertn@umich.edu 2901929Sbinkertn@umich.edu 0x0: decode SC { 2911881Sbinkertn@umich.edu 0x0: dvpe({{ 2921881Sbinkertn@umich.edu Rt.sw = xc->miscRegs.cop0.MVPControl; 2931881Sbinkertn@umich.edu xc->miscRegs.cop0.MVPControl[EVP] = 0; 2941881Sbinkertn@umich.edu }}); 2951881Sbinkertn@umich.edu 2961881Sbinkertn@umich.edu 0x1: evpe({{ 2971881Sbinkertn@umich.edu Rt.sw = xc->miscRegs.cop0.MVPControl; 2981881Sbinkertn@umich.edu xc->miscRegs.cop0.MVPControl[EVP] = 1; 2992006Sbinkertn@umich.edu }}); 3002006Sbinkertn@umich.edu } 3012006Sbinkertn@umich.edu 3022006Sbinkertn@umich.edu 0x1: decode SC { 3032006Sbinkertn@umich.edu 0x0: dmt({{ 3041881Sbinkertn@umich.edu Rt.sw = xc->miscRegs.cop0.VPEControl; 3051049Sbinkertn@umich.edu xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0; 3061049Sbinkertn@umich.edu }}); 3072002Sbinkertn@umich.edu 3081049Sbinkertn@umich.edu 0x1: emt({{ 3091049Sbinkertn@umich.edu Rt.sw = xc->miscRegs.cop0.VPEControl; 3102002Sbinkertn@umich.edu xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1; 3112006Sbinkertn@umich.edu }}); 3121881Sbinkertn@umich.edu } 3131881Sbinkertn@umich.edu 3141049Sbinkertn@umich.edu 0xC: decode SC { 3151049Sbinkertn@umich.edu 0x0: di({{ 3161049Sbinkertn@umich.edu Rt.sw = xc->miscRegs.cop0.Status; 3172002Sbinkertn@umich.edu xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0; 3182002Sbinkertn@umich.edu }}); 3191049Sbinkertn@umich.edu 3201881Sbinkertn@umich.edu 0x1: ei({{ 3211881Sbinkertn@umich.edu Rt.sw = xc->miscRegs.cop0.Status; 3221049Sbinkertn@umich.edu xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1; 3231881Sbinkertn@umich.edu }}); 3241881Sbinkertn@umich.edu } 3251881Sbinkertn@umich.edu } 3261049Sbinkertn@umich.edu 3271049Sbinkertn@umich.edu 0xE: wrpgpr({{ 3281049Sbinkertn@umich.edu //Accessing Previous Shadow Set Register Number 3291881Sbinkertn@umich.edu uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 3301881Sbinkertn@umich.edu uint64_t reg_num = Rd.uw; 3311049Sbinkertn@umich.edu 3321049Sbinkertn@umich.edu xc->shadowIntRegFile[prev][reg_num] = Rt; 3331049Sbinkertn@umich.edu }}); 3342002Sbinkertn@umich.edu } 3351881Sbinkertn@umich.edu } 3361881Sbinkertn@umich.edu 3371049Sbinkertn@umich.edu //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 3381049Sbinkertn@umich.edu 0x1: decode FUNCTION { 3391049Sbinkertn@umich.edu format Trap { 3401881Sbinkertn@umich.edu 0x01: tlbr({{ }}); 3412006Sbinkertn@umich.edu 0x02: tlbwi({{ }}); 3421881Sbinkertn@umich.edu 0x06: tlbwr({{ }}); 3431049Sbinkertn@umich.edu 0x08: tlbp({{ }}); 3441049Sbinkertn@umich.edu } 3451049Sbinkertn@umich.edu 3462002Sbinkertn@umich.edu format WarnUnimpl { 3472006Sbinkertn@umich.edu 0x18: eret(); 3481881Sbinkertn@umich.edu 0x1F: deret(); 3491881Sbinkertn@umich.edu 0x20: wait(); 3501049Sbinkertn@umich.edu } 3511049Sbinkertn@umich.edu } 3522002Sbinkertn@umich.edu } 3532002Sbinkertn@umich.edu 3542002Sbinkertn@umich.edu //Table A-13 MIPS32 COP1 Encoding of rs Field 3552002Sbinkertn@umich.edu 0x1: decode RS_MSB { 3562002Sbinkertn@umich.edu 3572002Sbinkertn@umich.edu 0x0: decode RS_HI { 3582002Sbinkertn@umich.edu 0x0: decode RS_LO { 3591049Sbinkertn@umich.edu format FloatOp { 3602006Sbinkertn@umich.edu 0x0: mfc1({{ Rt = Fs<31:0>; }}); 3612006Sbinkertn@umich.edu 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}}); 3621881Sbinkertn@umich.edu 0x3: mfhc1({{ Rt = Fs<63:32>;}}); 3631049Sbinkertn@umich.edu 0x4: mtc1({{ Fs<31:0> = Rt}}); 3641049Sbinkertn@umich.edu 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}}); 3651881Sbinkertn@umich.edu 0x7: mftc1({{ Fs<63:32> = Rt}}); 3661881Sbinkertn@umich.edu } 3672006Sbinkertn@umich.edu } 3681881Sbinkertn@umich.edu 3691881Sbinkertn@umich.edu 0x1: decode ND { 3701881Sbinkertn@umich.edu 0x0: decode TF { 3711881Sbinkertn@umich.edu format Branch { 3721881Sbinkertn@umich.edu 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }}); 3732006Sbinkertn@umich.edu 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }}); 3741881Sbinkertn@umich.edu } 3751881Sbinkertn@umich.edu } 3761881Sbinkertn@umich.edu 3771881Sbinkertn@umich.edu 0x1: decode TF { 3781881Sbinkertn@umich.edu format BranchLikely { 3792006Sbinkertn@umich.edu 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }}); 3801881Sbinkertn@umich.edu 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }}); 3811881Sbinkertn@umich.edu } 3821881Sbinkertn@umich.edu } 3831881Sbinkertn@umich.edu } 3841881Sbinkertn@umich.edu } 3852006Sbinkertn@umich.edu 3861881Sbinkertn@umich.edu 0x1: decode RS_HI { 3871881Sbinkertn@umich.edu 0x2: decode RS_LO { 3881881Sbinkertn@umich.edu 3891881Sbinkertn@umich.edu //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 3901881Sbinkertn@umich.edu //(( single-word )) 3912006Sbinkertn@umich.edu 0x0: decode RS_HI { 3921881Sbinkertn@umich.edu 0x0: decode RS_LO { 3931881Sbinkertn@umich.edu format FloatOp { 3941881Sbinkertn@umich.edu 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); 3951881Sbinkertn@umich.edu 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); 3961881Sbinkertn@umich.edu 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); 3971049Sbinkertn@umich.edu 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); 3981881Sbinkertn@umich.edu 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); 3992006Sbinkertn@umich.edu 0x5: abss({{ Fd.sf = abs(Fs.sf);}}); 4001881Sbinkertn@umich.edu 0x6: movs({{ Fd.sf = Fs.sf;}}); 4011049Sbinkertn@umich.edu 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); 4021049Sbinkertn@umich.edu } 4031049Sbinkertn@umich.edu } 4041881Sbinkertn@umich.edu 4051881Sbinkertn@umich.edu 0x1: decode RS_LO { 4062006Sbinkertn@umich.edu //only legal for 64 bit-FP 4071881Sbinkertn@umich.edu format Float64Op { 4081049Sbinkertn@umich.edu 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}}); 4091049Sbinkertn@umich.edu 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}}); 4101269Sbinkertn@umich.edu 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}}); 4112002Sbinkertn@umich.edu 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}}); 4121881Sbinkertn@umich.edu } 4131881Sbinkertn@umich.edu 4142006Sbinkertn@umich.edu format FloatOp { 4151881Sbinkertn@umich.edu 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}}); 4161269Sbinkertn@umich.edu 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}}); 4171269Sbinkertn@umich.edu 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}}); 4181049Sbinkertn@umich.edu 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}}); 4192002Sbinkertn@umich.edu } 4201881Sbinkertn@umich.edu } 4211049Sbinkertn@umich.edu 4221049Sbinkertn@umich.edu 0x2: decode RS_LO { 4231049Sbinkertn@umich.edu 0x1: decode MOVCF { 4242002Sbinkertn@umich.edu format FloatOp { 4251881Sbinkertn@umich.edu 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }}); 4261049Sbinkertn@umich.edu 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}}); 4271049Sbinkertn@umich.edu } 4281049Sbinkertn@umich.edu } 4292002Sbinkertn@umich.edu 4301881Sbinkertn@umich.edu format BasicOp { 4311049Sbinkertn@umich.edu 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 4321049Sbinkertn@umich.edu 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); 4331049Sbinkertn@umich.edu } 4341049Sbinkertn@umich.edu 4351049Sbinkertn@umich.edu format Float64Op { 4361049Sbinkertn@umich.edu 0x2: recips({{ Fd = 1 / Fs; }}); 4371049Sbinkertn@umich.edu 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}}); 4381049Sbinkertn@umich.edu } 4391049Sbinkertn@umich.edu } 4401881Sbinkertn@umich.edu 4411049Sbinkertn@umich.edu 0x4: decode RS_LO { 4421049Sbinkertn@umich.edu 4431881Sbinkertn@umich.edu format FloatOp { 4441049Sbinkertn@umich.edu 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr; 4451049Sbinkertn@umich.edu Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE); 4461049Sbinkertn@umich.edu }}); 4471049Sbinkertn@umich.edu 4481049Sbinkertn@umich.edu 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr; 4491929Sbinkertn@umich.edu Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE); 4501076Sbinkertn@umich.edu }}); 4511076Sbinkertn@umich.edu } 4521301Ssaidi@eecs.umich.edu 4531881Sbinkertn@umich.edu //only legal for 64 bit 4541918Sbinkertn@umich.edu format Float64Op { 4551881Sbinkertn@umich.edu 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr; 4561881Sbinkertn@umich.edu Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE); 4571049Sbinkertn@umich.edu }}); 4581929Sbinkertn@umich.edu 4591049Sbinkertn@umich.edu 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }}); 4601049Sbinkertn@umich.edu } 4611049Sbinkertn@umich.edu } 4621049Sbinkertn@umich.edu } 4631881Sbinkertn@umich.edu 4641049Sbinkertn@umich.edu //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 4651881Sbinkertn@umich.edu 0x1: decode RS_HI { 4661881Sbinkertn@umich.edu 0x0: decode RS_LO { 4671881Sbinkertn@umich.edu format FloatOp { 4681049Sbinkertn@umich.edu 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 4691049Sbinkertn@umich.edu 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 4701049Sbinkertn@umich.edu 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 4711881Sbinkertn@umich.edu 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 4721881Sbinkertn@umich.edu 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 4731049Sbinkertn@umich.edu 0x5: absd({{ Fd.df = abs(Fs.df);}}); 4741049Sbinkertn@umich.edu 0x6: movd({{ Fd.df = Fs.df;}}); 4751918Sbinkertn@umich.edu 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 4761918Sbinkertn@umich.edu } 4771881Sbinkertn@umich.edu } 4781918Sbinkertn@umich.edu 4791929Sbinkertn@umich.edu 0x1: decode RS_LO { 4801929Sbinkertn@umich.edu //only legal for 64 bit 4811049Sbinkertn@umich.edu format Float64Op { 4821049Sbinkertn@umich.edu 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 4831049Sbinkertn@umich.edu 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}}); 4841049Sbinkertn@umich.edu 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}}); 4851049Sbinkertn@umich.edu 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}}); 4861049Sbinkertn@umich.edu } 4871049Sbinkertn@umich.edu 4881049Sbinkertn@umich.edu format FloatOp { 4891301Ssaidi@eecs.umich.edu 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 4901301Ssaidi@eecs.umich.edu 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }}); 4911049Sbinkertn@umich.edu 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }}); 4921918Sbinkertn@umich.edu 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }}); 4931918Sbinkertn@umich.edu } 4941881Sbinkertn@umich.edu } 4951881Sbinkertn@umich.edu 4961881Sbinkertn@umich.edu 0x2: decode RS_LO { 4971881Sbinkertn@umich.edu 0x1: decode MOVCF { 4981881Sbinkertn@umich.edu format FloatOp { 4991881Sbinkertn@umich.edu 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }}); 5001881Sbinkertn@umich.edu 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }}); 5011881Sbinkertn@umich.edu } 5021881Sbinkertn@umich.edu } 5031881Sbinkertn@umich.edu 5041881Sbinkertn@umich.edu format BasicOp { 5051049Sbinkertn@umich.edu 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }}); 5061049Sbinkertn@umich.edu 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }}); 5071049Sbinkertn@umich.edu } 5081049Sbinkertn@umich.edu 5091049Sbinkertn@umich.edu format Float64Op { 5101049Sbinkertn@umich.edu 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 5111049Sbinkertn@umich.edu 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 5121049Sbinkertn@umich.edu } 5131049Sbinkertn@umich.edu } 5141049Sbinkertn@umich.edu 515 0x4: decode RS_LO { 516 format FloatOp { 517 0x0: cvt_s_d({{ 518 int rnd_mode = xc->miscRegs.fcsr; 519 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE); 520 }}); 521 522 0x4: cvt_w_d({{ 523 int rnd_mode = xc->miscRegs.fcsr; 524 Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE); 525 }}); 526 } 527 528 //only legal for 64 bit 529 format Float64Op { 530 0x5: cvt_l_d({{ 531 int rnd_mode = xc->miscRegs.fcsr; 532 Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE); 533 }}); 534 } 535 } 536 } 537 538 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 539 0x4: decode FUNCTION { 540 format FloatOp { 541 0x10: cvt_s({{ 542 int rnd_mode = xc->miscRegs.fcsr; 543 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); 544 }}); 545 546 0x10: cvt_d({{ 547 int rnd_mode = xc->miscRegs.fcsr; 548 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); 549 }}); 550 } 551 } 552 553 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 554 //Note: "1. Format type L is legal only if 64-bit floating point operations 555 //are enabled." 556 0x5: decode FUNCTION_HI { 557 format FloatOp { 558 0x10: cvt_s_l({{ 559 int rnd_mode = xc->miscRegs.fcsr; 560 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG); 561 }}); 562 563 0x11: cvt_d_l({{ 564 int rnd_mode = xc->miscRegs.fcsr; 565 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG); 566 }}); 567 } 568 } 569 570 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 571 //Note: "1. Format type PS is legal only if 64-bit floating point operations 572 //are enabled. " 573 0x6: decode RS_HI { 574 0x0: decode RS_LO { 575 format Float64Op { 576 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 577 //Lower Halves Independently but we take simulator shortcut 578 Fd.df = Fs.df + Ft.df; 579 }}); 580 581 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 582 //Lower Halves Independently but we take simulator shortcut 583 Fd.df = Fs.df - Ft.df; 584 }}); 585 586 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 587 //Lower Halves Independently but we take simulator shortcut 588 Fd.df = Fs.df * Ft.df; 589 }}); 590 591 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 592 //Lower Halves Independently but we take simulator shortcut 593 Fd.df = abs(Fs.df); 594 }}); 595 596 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 597 //Lower Halves Independently but we take simulator shortcut 598 Fd.df = Fs<31:0> | Ft<31:0>; 599 }}); 600 601 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 602 //Lower Halves Independently but we take simulator shortcut 603 Fd.df = -1 * Fs.df; 604 }}); 605 } 606 } 607 608 0x2: decode RS_LO { 609 0x1: decode MOVCF { 610 format Float64Op { 611 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 612 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 613 } 614 } 615 616 } 617 618 0x4: decode RS_LO { 619 0x0: Float64Op::cvt_s_pu({{ 620 int rnd_mode = xc->miscRegs.fcsr; 621 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI); 622 }}); 623 } 624 625 0x5: decode RS_LO { 626 format Float64Op { 627 0x0: cvt_s_pl({{ 628 int rnd_mode = xc->miscRegs.fcsr; 629 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO); 630 }}); 631 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}}); 632 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}}); 633 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}}); 634 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}}); 635 } 636 } 637 } 638 } 639 } 640 } 641 642 //Table A-19 MIPS32 COP2 Encoding of rs Field 643 0x2: decode RS_MSB { 644 0x0: decode RS_HI { 645 0x0: decode RS_LO { 646 format WarnUnimpl { 647 0x0: mfc2(); 648 0x2: cfc2(); 649 0x3: mfhc2(); 650 0x4: mtc2(); 651 0x6: ctc2(); 652 0x7: mftc2(); 653 } 654 } 655 656 0x1: decode ND { 657 0x0: decode TF { 658 format WarnUnimpl { 659 0x0: bc2f(); 660 0x1: bc2t(); 661 } 662 } 663 664 0x1: decode TF { 665 format WarnUnimpl { 666 0x0: bc2fl(); 667 0x1: bc2tl(); 668 } 669 } 670 } 671 } 672 } 673 674 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 675 //Note: "COP1X instructions are legal only if 64-bit floating point 676 //operations are enabled." 677 0x3: decode FUNCTION_HI { 678 0x0: decode FUNCTION_LO { 679 format LoadMemory2 { 680 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.sf; }}); 681 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }}); 682 0x5: luxc1({{ //Need to make EA<2:0> = 0 683 EA = Rs + Rt; 684 }}, 685 {{ Ft<31:0> = Mem.df; }}); 686 } 687 } 688 689 0x1: decode FUNCTION_LO { 690 format StoreMemory2 { 691 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.sf = Ft<31:0>; }}); 692 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.df = Ft<63:0>}}); 693 0x5: suxc1({{ //Need to make EA<2:0> = 0 694 EA = Rs + Rt; 695 }}, 696 {{ Mem.df = Ft<63:0>;}}); 697 } 698 699 0x7: WarnUnimpl::prefx(); 700 } 701 702 format FloatOp { 703 0x3: WarnUnimpl::alnv_ps(); 704 705 format BasicOp { 706 0x4: decode FUNCTION_LO { 707 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 708 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 709 0x6: madd_ps({{ 710 //Must Check for Exception Here... Supposed to Operate on Upper and 711 //Lower Halves Independently but we take simulator shortcut 712 Fd.df = (Fs.df * Fs.df) + Fr.df; 713 }}); 714 } 715 716 0x5: decode FUNCTION_LO { 717 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 718 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 719 0x6: msub_ps({{ 720 //Must Check for Exception Here... Supposed to Operate on Upper and 721 //Lower Halves Independently but we take simulator shortcut 722 Fd.df = (Fs.df * Fs.df) - Fr.df; 723 }}); 724 } 725 726 0x6: decode FUNCTION_LO { 727 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 728 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 729 0x6: nmadd_ps({{ 730 //Must Check for Exception Here... Supposed to Operate on Upper and 731 //Lower Halves Independently but we take simulator shortcut 732 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 733 }}); 734 } 735 736 0x7: decode FUNCTION_LO { 737 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 738 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 739 0x6: nmsub_ps({{ 740 //Must Check for Exception Here... Supposed to Operate on Upper and 741 //Lower Halves Independently but we take simulator shortcut 742 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 743 }}); 744 } 745 } 746 } 747 } 748 749 //MIPS obsolete instructions 750 format BranchLikely { 751 0x4: beql({{ cond = (Rs.sw == 0); }}); 752 0x5: bnel({{ cond = (Rs.sw != 0); }}); 753 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 754 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 755 } 756 } 757 758 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 759 760 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 761 0x4: decode FUNCTION_HI { 762 763 0x0: decode FUNCTION_LO { 764 format IntOp { 765 0x0: madd({{ 766 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 767 temp1 = temp1 + (Rs.sw * Rt.sw); 768 xc->miscRegs.hi->temp1<63:32>; 769 xc->miscRegs.lo->temp1<31:0> 770 }}); 771 772 0x1: maddu({{ 773 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 774 temp1 = temp1 + (Rs.uw * Rt.uw); 775 xc->miscRegs.hi->temp1<63:32>; 776 xc->miscRegs.lo->temp1<31:0> 777 }}); 778 779 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 780 781 0x4: msub({{ 782 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 783 temp1 = temp1 - (Rs.sw * Rt.sw); 784 xc->miscRegs.hi->temp1<63:32>; 785 xc->miscRegs.lo->temp1<31:0> 786 }}); 787 788 0x5: msubu({{ 789 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 790 temp1 = temp1 - (Rs.uw * Rt.uw); 791 xc->miscRegs.hi->temp1<63:32>; 792 xc->miscRegs.lo->temp1<31:0> 793 }}); 794 } 795 } 796 797 0x4: decode FUNCTION_LO { 798 format BasicOp { 799 0x0: clz({{ 800 int cnt = 0; 801 int idx = 0; 802 while ( Rs.uw<idx>!= 1) { 803 cnt++; 804 idx--; 805 } 806 807 Rd.uw = cnt; 808 }}); 809 810 0x1: clo({{ 811 int cnt = 0; 812 int idx = 0; 813 while ( Rs.uw<idx>!= 0) { 814 cnt++; 815 idx--; 816 } 817 818 Rd.uw = cnt; 819 }}); 820 } 821 } 822 823 0x7: decode FUNCTION_LO { 824 0x7: WarnUnimpl::sdbbp(); 825 } 826 } 827 828 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 829 0x7: decode FUNCTION_HI { 830 831 0x0: decode FUNCTION_LO { 832 format WarnUnimpl { 833 0x1: ext(); 834 0x4: ins(); 835 } 836 } 837 838 0x1: decode FUNCTION_LO { 839 format WarnUnimpl { 840 0x0: fork(); 841 0x1: yield(); 842 } 843 } 844 845 846 //Table A-10 MIPS32 BSHFL Encoding of sa Field 847 0x4: decode SA { 848 849 0x02: WarnUnimpl::wsbh(); 850 851 format BasicOp { 852 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}}); 853 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}}); 854 } 855 } 856 857 0x6: decode FUNCTION_LO { 858 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}}); 859 } 860 } 861 } 862 863 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 864 format LoadMemory { 865 0x0: lb({{ Rb.sw = Mem.sb; }}); 866 0x1: lh({{ Rb.sw = Mem.sh; }}); 867 0x2: lwl({{ Rb.sw = Mem.sw; }});//, WordAlign); 868 0x3: lw({{ Rb.uq = Mem.sb; }}); 869 0x4: lbu({{ Rb.uw = Mem.ub; }}); 870 0x5: lhu({{ Rb.uw = Mem.uh; }}); 871 0x6: lwr({{ Rb.uw = Mem.uw; }});//, WordAlign); 872 } 873 874 0x7: FailUnimpl::reserved(); 875 } 876 877 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 878 format StoreMemory { 879 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 880 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 881 0x2: swl({{ Mem.ub = Rt<31:0>; }});//,WordAlign); 882 0x3: sw({{ Mem.ub = Rt<31:0>; }}); 883 0x6: swr({{ Mem.ub = Rt<31:0>; }});//,WordAlign); 884 } 885 886 format WarnUnimpl { 887 0x7: cache(); 888 } 889 890 } 891 892 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 893 0x0: WarnUnimpl::ll(); 894 895 format LoadMemory { 896 0x1: lwc1({{ Ft<31:0> = Mem.sf; }}); 897 0x5: ldc1({{ Ft<63:0> = Mem.df; }}); 898 } 899 } 900 901 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 902 0x0: WarnUnimpl::sc(); 903 904 format StoreMemory { 905 0x1: swc1({{ Mem.sf = Ft<31:0>; }}); 906 0x5: sdc1({{ Mem.df = Ft<63:0>; }}); 907 } 908 909 } 910} 911 912 913