decoder.isa revision 2104
1// -*- mode:c++ -*- 2 3//////////////////////////////////////////////////////////////////// 4// 5// The actual MIPS32 ISA decoder 6// ----------------------------- 7// The following instructions are specified in the MIPS32 ISA 8// Specification. Decoding closely follows the style specified 9// in the MIPS32 ISAthe specification document starting with Table 10// A-2 (document available @ www.mips.com) 11// 12//@todo: Distinguish "unknown/future" use insts from "reserved" 13// ones 14decode OPCODE_HI default Unknown::unknown() { 15 16 // Derived From ... Table A-2 MIPS32 ISA Manual 17 0x0: decode OPCODE_LO { 18 19 0x0: decode FUNCTION_HI { 20 0x0: decode FUNCTION_LO { 21 0x1: decode MOVCI { 22 format BasicOp { 23 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}}); 24 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}}); 25 } 26 } 27 28 format BasicOp { 29 30 //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 31 //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." 32 33 0x0: sll({{ Rd = Rt.uw << SA; }}); 34 35 0x2: decode SRL { 36 0: srl({{ Rd = Rt.uw >> SA; }}); 37 38 //Hardcoded assuming 32-bit ISA, probably need parameter here 39 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 40 } 41 42 0x3: sra({{ Rd = Rt.sw >> SA; }}); 43 44 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 45 46 0x6: decode SRLV { 47 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 48 49 //Hardcoded assuming 32-bit ISA, probably need parameter here 50 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 51 } 52 53 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); 54 } 55 } 56 57 0x1: decode FUNCTION_LO { 58 59 //Table A-3 Note: "Specific encodings of the hint field are used 60 //to distinguish JR from JR.HB and JALR from JALR.HB" 61 format Unconditional { 62 0x0: decode HINT { 63 0:jr({{ }},IsReturn,IsLink); 64 1:jr_hb({{ }},IsReturn,IsLink); 65 } 66 67 0x1: decode HINT { 68 0: jalr({{ }},'IsCall','IsReturn','IsLink'); 69 1: jalr_hb({{ }},IsCall,IsReturn,IsLink); 70 } 71 } 72 73 format BasicOp { 74 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 75 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 76 } 77 78 79 format WarnUnimpl { 80 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative 81 0x5: break(); 82 0x7: sync(); 83 } 84 } 85 86 0x2: decode FUNCTION_LO { 87 format BasicOp { 88 0x0: mfhi({{ Rd = xc->miscRegs.hi; }}); 89 0x1: mthi({{ xc->miscRegs.hi = Rs; }}); 90 0x2: mflo({{ Rd = xc->miscRegs.lo; }}); 91 0x3: mtlo({{ xc->miscRegs.lo = Rs; }}); 92 } 93 } 94 95 0x3: decode FUNCTION_LO { 96 format IntOp { 97 0x0: mult({{ 98 INT64 temp1 = Rs.sw * Rt.sw; 99 xc->miscRegs.hi->temp1<63:32>; 100 xc->miscRegs.lo->temp1<31:0>; 101 }}); 102 103 0x1: multu({{ 104 INT64 temp1 = Rs.uw * Rt.uw; 105 xc->miscRegs.hi->temp1<63:32>; 106 xc->miscRegs.lo->temp1<31:0> 107 Rd.sw = Rs.uw * Rt.uw; 108 }}); 109 110 0x2: div({{ 111 xc->miscRegs.hi = Rs.sw % Rt.sw; 112 xc->miscRegs.lo = Rs.sw / Rt.sw; 113 }}); 114 115 0x3: divu({{ 116 xc->miscRegs.hi = Rs.uw % Rt.uw; 117 xc->miscRegs.lo = Rs.uw / Rt.uw; 118 }}); 119 } 120 } 121 122 0x4: decode FUNCTION_LO { 123 format IntOp { 124 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}}); 125 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}}); 126 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}}); 127 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}}); 128 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}}); 129 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}}); 130 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}}); 131 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}}); 132 } 133 } 134 135 0x5: decode FUNCTION_LO { 136 format IntOp{ 137 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 138 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 139 } 140 } 141 142 0x6: decode FUNCTION_LO { 143 format Trap { 144 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 145 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 146 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 147 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 148 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 149 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 150 } 151 } 152 } 153 154 0x1: decode REGIMM_HI { 155 0x0: decode REGIMM_LO { 156 format Branch { 157 0x0: bltz({{ cond = (Rs.sw < 0); }}); 158 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 159 } 160 161 format BranchLikely { 162 //MIPS obsolete instructions 163 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 164 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 165 } 166 } 167 168 0x1: decode REGIMM_LO { 169 format Trap { 170 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 171 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 172 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 173 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 174 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 175 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 176 } 177 } 178 179 0x2: decode REGIMM_LO { 180 format Branch { 181 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsLink); 182 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsLink); 183 } 184 185 format BranchLikely { 186 //Will be removed in future MIPS releases 187 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsLink); 188 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsLink); 189 } 190 } 191 192 0x3: decode REGIMM_LO { 193 format WarnUnimpl { 194 0x7: synci(); 195 } 196 } 197 } 198 199 format Unconditional { 200 0x2: j({{ }}); 201 0x3: jal({{ }},IsCall,IsLink); 202 } 203 204 format Branch { 205 0x4: beq({{ cond = (Rs.sw == 0); }}); 206 0x5: bne({{ cond = (Rs.sw != 0); }}); 207 0x6: blez({{ cond = (Rs.sw <= 0); }}); 208 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 209 } 210 } 211 212 0x1: decode OPCODE_LO { 213 format IntOp { 214 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }}); 215 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}}); 216 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }}); 217 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }}); 218 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); 219 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); 220 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); 221 0x7: lui({{ Rt = INTIMM << 16}}); 222 } 223 } 224 225 0x2: decode OPCODE_LO { 226 227 //Table A-11 MIPS32 COP0 Encoding of rs Field 228 0x0: decode RS_MSB { 229 0x0: decode RS { 230 format BasicOp { 231 0x0: mfc0({{ 232 //The contents of the coprocessor 0 register specified by the 233 //combination of rd and sel are loaded into general register 234 //rt. Note that not all coprocessor 0 registers support the 235 //sel field. In those instances, the sel field must be zero. 236 237 if (SEL > 0) 238 panic("Can't Handle Cop0 with register select yet\n"); 239 240 uint64_t reg_num = Rd.uw; 241 242 Rt = xc->miscRegs.cop0[reg_num]; 243 }}); 244 245 0x4: mtc0({{ 246 //The contents of the coprocessor 0 register specified by the 247 //combination of rd and sel are loaded into general register 248 //rt. Note that not all coprocessor 0 registers support the 249 //sel field. In those instances, the sel field must be zero. 250 251 if (SEL > 0) 252 panic("Can't Handle Cop0 with register select yet\n"); 253 254 uint64_t reg_num = Rd.uw; 255 256 xc->miscRegs.cop0[reg_num] = Rt; 257 }}); 258 259 0x8: mftr({{ 260 //The contents of the coprocessor 0 register specified by the 261 //combination of rd and sel are loaded into general register 262 //rt. Note that not all coprocessor 0 registers support the 263 //sel field. In those instances, the sel field must be zero. 264 265 //MT Code Needed Here 266 }}); 267 268 0xC: mttr({{ 269 //The contents of the coprocessor 0 register specified by the 270 //combination of rd and sel are loaded into general register 271 //rt. Note that not all coprocessor 0 registers support the 272 //sel field. In those instances, the sel field must be zero. 273 274 //MT Code Needed Here 275 }}); 276 277 278 0xA: rdpgpr({{ 279 //Accessing Previous Shadow Set Register Number 280 uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 281 uint64_t reg_num = Rt.uw; 282 283 Rd = xc->shadowIntRegFile[prev][reg_num]; 284 }}); 285 286 0xB: decode RD { 287 288 0x0: decode SC { 289 0x0: dvpe({{ 290 Rt.sw = xc->miscRegs.cop0.MVPControl; 291 xc->miscRegs.cop0.MVPControl[EVP] = 0; 292 }}); 293 294 0x1: evpe({{ 295 Rt.sw = xc->miscRegs.cop0.MVPControl; 296 xc->miscRegs.cop0.MVPControl[EVP] = 1; 297 }}); 298 } 299 300 0x1: decode SC { 301 0x0: dmt({{ 302 Rt.sw = xc->miscRegs.cop0.VPEControl; 303 xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0; 304 }}); 305 306 0x1: emt({{ 307 Rt.sw = xc->miscRegs.cop0.VPEControl; 308 xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1; 309 }}); 310 } 311 312 0xC: decode SC { 313 0x0: di({{ 314 Rt.sw = xc->miscRegs.cop0.Status; 315 xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0; 316 }}); 317 318 0x1: ei({{ 319 Rt.sw = xc->miscRegs.cop0.Status; 320 xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1; 321 }}); 322 } 323 } 324 325 0xE: wrpgpr({{ 326 //Accessing Previous Shadow Set Register Number 327 uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 328 uint64_t reg_num = Rd.uw; 329 330 xc->shadowIntRegFile[prev][reg_num] = Rt; 331 }}); 332 } 333 } 334 335 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 336 0x1: decode FUNCTION { 337 format Trap { 338 0x01: tlbr({{ }}); 339 0x02: tlbwi({{ }}); 340 0x06: tlbwr({{ }}); 341 0x08: tlbp({{ }}); 342 } 343 344 format WarnUnimpl { 345 0x18: eret(); 346 0x1F: deret(); 347 0x20: wait(); 348 } 349 } 350 } 351 352 //Table A-13 MIPS32 COP1 Encoding of rs Field 353 0x1: decode RS_MSB { 354 355 0x0: decode RS_HI { 356 0x0: decode RS_LO { 357 format FloatOp { 358 0x0: mfc1({{ Rt = Fs<31:0>; }}); 359 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}}); 360 0x3: mfhc1({{ Rt = Fs<63:32>;}}); 361 0x4: mtc1({{ Fs<31:0> = Rt}}); 362 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}}); 363 0x7: mftc1({{ Fs<63:32> = Rt}}); 364 } 365 } 366 367 0x1: decode ND { 368 0x0: decode TF { 369 format Branch { 370 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }}); 371 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }}); 372 } 373 } 374 375 0x1: decode TF { 376 format BranchLikely { 377 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }}); 378 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }}); 379 } 380 } 381 } 382 } 383 384 0x1: decode RS_HI { 385 0x2: decode RS_LO { 386 387 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 388 //(( single-word )) 389 0x0: decode RS_HI { 390 0x0: decode RS_LO { 391 format FloatOp { 392 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); 393 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); 394 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); 395 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); 396 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); 397 0x5: abss({{ Fd.sf = abs(Fs.sf);}}); 398 0x6: movs({{ Fd.sf = Fs.sf;}}); 399 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); 400 } 401 } 402 403 0x1: decode RS_LO { 404 //only legal for 64 bit-FP 405 format Float64Op { 406 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}}); 407 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}}); 408 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}}); 409 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}}); 410 } 411 412 format FloatOp { 413 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}}); 414 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}}); 415 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}}); 416 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}}); 417 } 418 } 419 420 0x2: decode RS_LO { 421 0x1: decode MOVCF { 422 format FloatOp { 423 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }}); 424 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}}); 425 } 426 } 427 428 format BasicOp { 429 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 430 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); 431 } 432 433 format Float64Op { 434 0x2: recips({{ Fd = 1 / Fs; }}); 435 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}}); 436 } 437 } 438 439 0x4: decode RS_LO { 440 441 format FloatOp { 442 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr; 443 Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE); 444 }}); 445 446 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr; 447 Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE); 448 }}); 449 } 450 451 //only legal for 64 bit 452 format Float64Op { 453 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr; 454 Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE); 455 }}); 456 457 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }}); 458 } 459 } 460 } 461 462 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 463 0x1: decode RS_HI { 464 0x0: decode RS_LO { 465 format FloatOp { 466 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 467 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 468 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 469 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 470 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 471 0x5: absd({{ Fd.df = abs(Fs.df);}}); 472 0x6: movd({{ Fd.df = Fs.df;}}); 473 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 474 } 475 } 476 477 0x1: decode RS_LO { 478 //only legal for 64 bit 479 format Float64Op { 480 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 481 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}}); 482 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}}); 483 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}}); 484 } 485 486 format FloatOp { 487 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 488 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }}); 489 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }}); 490 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }}); 491 } 492 } 493 494 0x2: decode RS_LO { 495 0x1: decode MOVCF { 496 format FloatOp { 497 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }}); 498 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }}); 499 } 500 } 501 502 format BasicOp { 503 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }}); 504 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }}); 505 } 506 507 format Float64Op { 508 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 509 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 510 } 511 } 512 513 0x4: decode RS_LO { 514 format FloatOp { 515 0x0: cvt_s_d({{ 516 int rnd_mode = xc->miscRegs.fcsr; 517 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE); 518 }}); 519 520 0x4: cvt_w_d({{ 521 int rnd_mode = xc->miscRegs.fcsr; 522 Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE); 523 }}); 524 } 525 526 //only legal for 64 bit 527 format Float64Op { 528 0x5: cvt_l_d({{ 529 int rnd_mode = xc->miscRegs.fcsr; 530 Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE); 531 }}); 532 } 533 } 534 } 535 536 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 537 0x4: decode FUNCTION { 538 format FloatOp { 539 0x10: cvt_s({{ 540 int rnd_mode = xc->miscRegs.fcsr; 541 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); 542 }}); 543 544 0x10: cvt_d({{ 545 int rnd_mode = xc->miscRegs.fcsr; 546 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); 547 }}); 548 } 549 } 550 551 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 552 //Note: "1. Format type L is legal only if 64-bit floating point operations 553 //are enabled." 554 0x5: decode FUNCTION_HI { 555 format FloatOp { 556 0x10: cvt_s_l({{ 557 int rnd_mode = xc->miscRegs.fcsr; 558 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG); 559 }}); 560 561 0x11: cvt_d_l({{ 562 int rnd_mode = xc->miscRegs.fcsr; 563 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG); 564 }}); 565 } 566 } 567 568 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 569 //Note: "1. Format type PS is legal only if 64-bit floating point operations 570 //are enabled. " 571 0x6: decode RS_HI { 572 0x0: decode RS_LO { 573 format Float64Op { 574 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 575 //Lower Halves Independently but we take simulator shortcut 576 Fd.df = Fs.df + Ft.df; 577 }}); 578 579 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 580 //Lower Halves Independently but we take simulator shortcut 581 Fd.df = Fs.df - Ft.df; 582 }}); 583 584 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 585 //Lower Halves Independently but we take simulator shortcut 586 Fd.df = Fs.df * Ft.df; 587 }}); 588 589 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 590 //Lower Halves Independently but we take simulator shortcut 591 Fd.df = abs(Fs.df); 592 }}); 593 594 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 595 //Lower Halves Independently but we take simulator shortcut 596 Fd.df = Fs<31:0> | Ft<31:0>; 597 }}); 598 599 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 600 //Lower Halves Independently but we take simulator shortcut 601 Fd.df = -1 * Fs.df; 602 }}); 603 } 604 } 605 606 0x2: decode RS_LO { 607 0x1: decode MOVCF { 608 format Float64Op { 609 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 610 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 611 } 612 } 613 614 } 615 616 0x4: decode RS_LO { 617 0x0: Float64Op::cvt_s_pu({{ 618 int rnd_mode = xc->miscRegs.fcsr; 619 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI); 620 }}); 621 } 622 623 0x5: decode RS_LO { 624 format Float64Op { 625 0x0: cvt_s_pl({{ 626 int rnd_mode = xc->miscRegs.fcsr; 627 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO); 628 }}); 629 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}}); 630 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}}); 631 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}}); 632 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}}); 633 } 634 } 635 } 636 } 637 } 638 } 639 640 //Table A-19 MIPS32 COP2 Encoding of rs Field 641 0x2: decode RS_MSB { 642 0x0: decode RS_HI { 643 0x0: decode RS_LO { 644 format WarnUnimpl { 645 0x0: mfc2(); 646 0x2: cfc2(); 647 0x3: mfhc2(); 648 0x4: mtc2(); 649 0x6: ctc2(); 650 0x7: mftc2(); 651 } 652 } 653 654 0x1: decode ND { 655 0x0: decode TF { 656 format WarnUnimpl { 657 0x0: bc2f(); 658 0x1: bc2t(); 659 } 660 } 661 662 0x1: decode TF { 663 format WarnUnimpl { 664 0x0: bc2fl(); 665 0x1: bc2tl(); 666 } 667 } 668 } 669 } 670 } 671 672 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 673 //Note: "COP1X instructions are legal only if 64-bit floating point 674 //operations are enabled." 675 0x3: decode FUNCTION_HI { 676 0x0: decode FUNCTION_LO { 677 format Memory { 678 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.uf; }}); 679 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }}); 680 0x5: luxc1({{ //Need to make EA<2:0> = 0 681 EA = Rs + Rt; 682 }}, 683 {{ Ft<31:0> = Mem.df; }}); 684 } 685 } 686 687 0x1: decode FUNCTION_LO { 688 format Memory { 689 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<31:0>; }}); 690 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<63:0>}}); 691 0x5: suxc1({{ //Need to make EA<2:0> = 0 692 EA = Rs + Rt; 693 }}, 694 {{ Mem.df = Ft<63:0>;}}); 695 } 696 697 0x7: WarnUnimpl::prefx(); 698 } 699 700 format FloatOp { 701 0x3: WarnUnimpl::alnv_ps(); 702 703 format BasicOp { 704 0x4: decode FUNCTION_LO { 705 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 706 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 707 0x6: madd_ps({{ 708 //Must Check for Exception Here... Supposed to Operate on Upper and 709 //Lower Halves Independently but we take simulator shortcut 710 Fd.df = (Fs.df * Fs.df) + Fr.df; 711 }}); 712 } 713 714 0x5: decode FUNCTION_LO { 715 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 716 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 717 0x6: msub_ps({{ 718 //Must Check for Exception Here... Supposed to Operate on Upper and 719 //Lower Halves Independently but we take simulator shortcut 720 Fd.df = (Fs.df * Fs.df) - Fr.df; 721 }}); 722 } 723 724 0x6: decode FUNCTION_LO { 725 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 726 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 727 0x6: nmadd_ps({{ 728 //Must Check for Exception Here... Supposed to Operate on Upper and 729 //Lower Halves Independently but we take simulator shortcut 730 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 731 }}); 732 } 733 734 0x7: decode FUNCTION_LO { 735 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 736 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 737 0x6: nmsub_ps({{ 738 //Must Check for Exception Here... Supposed to Operate on Upper and 739 //Lower Halves Independently but we take simulator shortcut 740 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 741 }}); 742 } 743 } 744 } 745 } 746 747 //MIPS obsolete instructions 748 format BranchLikely { 749 0x4: beql({{ cond = (Rs.sw == 0); }}); 750 0x5: bnel({{ cond = (Rs.sw != 0); }}); 751 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 752 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 753 } 754 } 755 756 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 757 758 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 759 0x4: decode FUNCTION_HI { 760 761 0x0: decode FUNCTION_LO { 762 format IntOp { 763 0x0: madd({{ 764 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 765 temp1 = temp1 + (Rs.sw * Rt.sw); 766 xc->miscRegs.hi->temp1<63:32>; 767 xc->miscRegs.lo->temp1<31:0> 768 }}); 769 770 0x1: maddu({{ 771 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 772 temp1 = temp1 + (Rs.uw * Rt.uw); 773 xc->miscRegs.hi->temp1<63:32>; 774 xc->miscRegs.lo->temp1<31:0> 775 }}); 776 777 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 778 779 0x4: msub({{ 780 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 781 temp1 = temp1 - (Rs.sw * Rt.sw); 782 xc->miscRegs.hi->temp1<63:32>; 783 xc->miscRegs.lo->temp1<31:0> 784 }}); 785 786 0x5: msubu({{ 787 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 788 temp1 = temp1 - (Rs.uw * Rt.uw); 789 xc->miscRegs.hi->temp1<63:32>; 790 xc->miscRegs.lo->temp1<31:0> 791 }}); 792 } 793 } 794 795 0x4: decode FUNCTION_LO { 796 format BasicOp { 797 0x0: clz({{ 798 int cnt = 0; 799 int idx = 0; 800 while ( Rs.uw<idx>!= 1) { 801 cnt++; 802 idx--; 803 } 804 805 Rd.uw = cnt; 806 }}); 807 808 0x1: clo({{ 809 int cnt = 0; 810 int idx = 0; 811 while ( Rs.uw<idx>!= 0) { 812 cnt++; 813 idx--; 814 } 815 816 Rd.uw = cnt; 817 }}); 818 } 819 } 820 821 0x7: decode FUNCTION_LO { 822 0x7: WarnUnimpl::sdbbp(); 823 } 824 } 825 826 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 827 0x7: decode FUNCTION_HI { 828 829 0x0: decode FUNCTION_LO { 830 format WarnUnimpl { 831 0x1: ext(); 832 0x4: ins(); 833 } 834 } 835 836 0x1: decode FUNCTION_LO { 837 format WarnUnimpl { 838 0x0: fork(); 839 0x1: yield(); 840 } 841 } 842 843 844 //Table A-10 MIPS32 BSHFL Encoding of sa Field 845 0x4: decode SA { 846 847 0x02: WarnUnimpl::wsbh(); 848 849 format BasicOp { 850 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}}); 851 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}}); 852 } 853 } 854 855 0x6: decode FUNCTION_LO { 856 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}}); 857 } 858 } 859 } 860 861 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 862 format Memory { 863 0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }}); 864 0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }}); 865 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }});//, WordAlign); 866 0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }}); 867 0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }}); 868 0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }}); 869 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }});//, WordAlign); 870 } 871 872 0x7: FailUnimpl::reserved(); 873 } 874 875 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 876 format Memory { 877 0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }}); 878 0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }}); 879 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign); 880 0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }}); 881 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign); 882 } 883 884 format WarnUnimpl { 885 0x7: cache(); 886 } 887 888 } 889 890 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 891 0x0: WarnUnimpl::ll(); 892 893 format Memory { 894 0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }}); 895 0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }}); 896 } 897 } 898 899 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 900 0x0: WarnUnimpl::sc(); 901 902 format Memory { 903 0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }}); 904 0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }}); 905 } 906 907 } 908} 909 910 911