decoder.isa revision 2083
16145Snate@binkert.org//////////////////////////////////////////////////////////////////// 26145Snate@binkert.org// 36145Snate@binkert.org// The actual MIPS32 ISA decoder 46145Snate@binkert.org// ----------------------------- 56145Snate@binkert.org// The following instructions are specified in the MIPS32 ISA 66145Snate@binkert.org// Specification. Decoding closely follows the style specified 76145Snate@binkert.org// in the MIPS32 ISAthe specification document starting with Table 86145Snate@binkert.org// A-2 (document available @ www.mips.com) 96145Snate@binkert.org// 106145Snate@binkert.org//@todo: Distinguish "unknown/future" use insts from "reserved" 116145Snate@binkert.org// ones 126145Snate@binkert.orgdecode OPCODE_HI default Unknown::unknown() { 136145Snate@binkert.org 146145Snate@binkert.org // Derived From ... Table A-2 MIPS32 ISA Manual 156145Snate@binkert.org 0x0: decode OPCODE_LO default FailUnimpl::reserved(){ 166145Snate@binkert.org 176145Snate@binkert.org 0x0: decode FUNCTION_HI { 186145Snate@binkert.org 0x0: decode FUNCTION_LO { 196145Snate@binkert.org 0x1: decode MOVCI { 206145Snate@binkert.org format BasicOp { 216145Snate@binkert.org 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}}); 226145Snate@binkert.org 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}}); 236145Snate@binkert.org } 246145Snate@binkert.org } 256145Snate@binkert.org 266145Snate@binkert.org format BasicOp { 276145Snate@binkert.org 286145Snate@binkert.org //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 296145Snate@binkert.org //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." 306145Snate@binkert.org 316145Snate@binkert.org 0x0: sll({{ Rd = Rt.uw << SA; }}); 326145Snate@binkert.org 336145Snate@binkert.org 0x2: decode SRL { 346145Snate@binkert.org 0: srl({{ Rd = Rt.uw >> SA; }}); 356145Snate@binkert.org 366145Snate@binkert.org //Hardcoded assuming 32-bit ISA, probably need parameter here 376145Snate@binkert.org 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 386145Snate@binkert.org } 396145Snate@binkert.org 406154Snate@binkert.org 0x3: sra({{ Rd = Rt.sw >> SA; }}); 416154Snate@binkert.org 426154Snate@binkert.org 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 436145Snate@binkert.org 446285Snate@binkert.org 0x6: decode SRLV { 456285Snate@binkert.org 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 466145Snate@binkert.org 476145Snate@binkert.org //Hardcoded assuming 32-bit ISA, probably need parameter here 486145Snate@binkert.org 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 496145Snate@binkert.org } 506145Snate@binkert.org 516145Snate@binkert.org 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); 526145Snate@binkert.org } 536145Snate@binkert.org } 546145Snate@binkert.org 556145Snate@binkert.org 0x1: decode FUNCTION_LO { 566145Snate@binkert.org 576145Snate@binkert.org //Table A-3 Note: "Specific encodings of the hint field are used 586285Snate@binkert.org //to distinguish JR from JR.HB and JALR from JALR.HB" 596145Snate@binkert.org format Jump { 606145Snate@binkert.org 0x0: jr(IsReturn); 616145Snate@binkert.org 0x1: jalr(IsCall,IsReturn); 626145Snate@binkert.org } 636145Snate@binkert.org 646145Snate@binkert.org format BasicOp { 656145Snate@binkert.org 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 666145Snate@binkert.org 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 676145Snate@binkert.org } 686145Snate@binkert.org 696145Snate@binkert.org 706145Snate@binkert.org format WarnUnimpl { 716145Snate@binkert.org 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative 726145Snate@binkert.org 0x5: break(); 736145Snate@binkert.org 0x7: sync(); 746145Snate@binkert.org } 756145Snate@binkert.org } 766145Snate@binkert.org 776145Snate@binkert.org 0x2: decode FUNCTION_LO { 786145Snate@binkert.org format BasicOp { 796145Snate@binkert.org 0x0: mfhi({{ Rd = xc->miscRegs.hi; }}); 806145Snate@binkert.org 0x1: mthi({{ xc->miscRegs.hi = Rs; }}); 816145Snate@binkert.org 0x2: mflo({{ Rd = xc->miscRegs.lo; }}); 826145Snate@binkert.org 0x3: mtlo({{ xc->miscRegs.lo = Rs; }}); 836145Snate@binkert.org } 846145Snate@binkert.org } 85 86 0x3: decode FUNCTION_LO { 87 format IntOp { 88 0x0: mult({{ 89 INT64 temp1 = Rs.sw * Rt.sw; 90 xc->miscRegs.hi->temp1<63:32>; 91 xc->miscRegs.lo->temp1<31:0>; 92 }}); 93 94 0x1: multu({{ 95 INT64 temp1 = Rs.uw * Rt.uw; 96 xc->miscRegs.hi->temp1<63:32>; 97 xc->miscRegs.lo->temp1<31:0> 98 Rd.sw = Rs.uw * Rt.uw; 99 }}); 100 101 0x2: div({{ 102 xc->miscRegs.hi = Rs.sw % Rt.sw; 103 xc->miscRegs.lo = Rs.sw / Rt.sw; 104 }}); 105 106 0x3: divu({{ 107 xc->miscRegs.hi = Rs.uw % Rt.uw; 108 xc->miscRegs.lo = Rs.uw / Rt.uw; 109 }}); 110 } 111 }; 112 113 0x4: decode FUNCTION_LO { 114 format IntOp { 115 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}}); 116 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}}); 117 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}}); 118 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}}); 119 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}}); 120 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}}); 121 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}}); 122 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}}); 123 } 124 } 125 126 0x5: decode FUNCTION_LO { 127 format IntOp{ 128 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 129 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 130 } 131 }; 132 133 0x6: decode FUNCTION_LO { 134 format Trap { 135 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 136 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 137 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 138 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 139 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 140 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 141 } 142 } 143 } 144 145 0x1: decode REGIMM_HI { 146 0x0: decode REGIMM_LO { 147 format Branch { 148 0x0: bltz({{ cond = (Rs.sq < 0); }}); 149 0x1: bgez({{ cond = (Rs.sq >= 0); }}); 150 151 //MIPS obsolete instructions 152 0x2: bltzl({{ cond = (Rs.sq < 0); }}); 153 0x3: bgezl({{ cond = (Rs.sq >= 0); }}); 154 } 155 } 156 157 0x1: decode REGIMM_LO { 158 format Trap { 159 0x0: tgei({{ cond = (Rs.sw >= INTIMM; }}); 160 0x1: tgeiu({{ cond = (Rs.uw < INTIMM); }}); 161 0x2: tlti({{ cond = (Rs.sw < INTIMM); }}); 162 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 163 0x4: teqi({{ cond = (Rs.sw == INTIMM); }}); 164 0x6: tnei({{ cond = (Rs.sw != INTIMM); }}); 165 } 166 } 167 168 0x2: decode REGIMM_LO { 169 format Branch { 170 0x0: bltzal({{ cond = (Rs.sq < 0); }}); 171 0x1: bgezal({{ cond = (Rs.sq >= 0); }}); 172 173 //MIPS obsolete instructions 174 0x2: bltzall({{ cond = (Rs.sq < 0); }}); 175 0x3: bgezall({{ cond = (Rs.sq >= 0); }}); 176 } 177 } 178 179 0x3: decode REGIMM_LO { 180 format WarnUnimpl { 181 0x7: synci({{ }}); 182 } 183 } 184 } 185 186 format Jump { 187 0x2: j(); 188 0x3: jal(IsCall); 189 } 190 191 format Branch { 192 0x4: beq({{ cond = (Rs.sq == 0); }}); 193 0x5: bne({{ cond = (Rs.sq != 0); }}); 194 0x6: blez({{ cond = (Rs.sq <= 0); }}); 195 0x7: bgtz({{ cond = (Rs.sq > 0); }}); 196 } 197 }; 198 199 0x1: decode OPCODE_LO default FailUnimpl::reserved(){ 200 format IntOp { 201 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }}); 202 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}}); 203 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }}); 204 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }}); 205 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); 206 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); 207 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); 208 0x7: lui({{ Rt = INTIMM << 16}}); 209 }; 210 }; 211 212 0x2: decode OPCODE_LO default FailUnimpl::reserved(){ 213 214 //Table A-11 MIPS32 COP0 Encoding of rs Field 215 0x0: decode RS_MSB { 216 0x0: decode RS { 217 218 format BasicOp { 219 0x0: mfc0({{ 220 //The contents of the coprocessor 0 register specified by the 221 //combination of rd and sel are loaded into general register 222 //rt. Note that not all coprocessor 0 registers support the 223 //sel field. In those instances, the sel field must be zero. 224 225 if (SEL > 0) 226 panic("Can't Handle Cop0 with register select yet\n"); 227 228 uint64_t reg_num = Rd.uw; 229 230 Rt = xc->miscRegs.cop0[reg_num]; 231 }}); 232 233 0x4: mtc0({{ 234 //The contents of the coprocessor 0 register specified by the 235 //combination of rd and sel are loaded into general register 236 //rt. Note that not all coprocessor 0 registers support the 237 //sel field. In those instances, the sel field must be zero. 238 239 if (SEL > 0) 240 panic("Can't Handle Cop0 with register select yet\n"); 241 242 uint64_t reg_num = Rd.uw; 243 244 xc->miscRegs.cop0[reg_num] = Rt; 245 }}); 246 247 0x8: mftr({{ 248 //The contents of the coprocessor 0 register specified by the 249 //combination of rd and sel are loaded into general register 250 //rt. Note that not all coprocessor 0 registers support the 251 //sel field. In those instances, the sel field must be zero. 252 253 //MT Code Needed Here 254 }}); 255 256 0xC: mttr({{ 257 //The contents of the coprocessor 0 register specified by the 258 //combination of rd and sel are loaded into general register 259 //rt. Note that not all coprocessor 0 registers support the 260 //sel field. In those instances, the sel field must be zero. 261 262 //MT Code Needed Here 263 }}); 264 265 266 0xA: rdpgpr({{ 267 //Accessing Previous Shadow Set Register Number 268 uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 269 uint64_t reg_num = Rt.uw; 270 271 Rd = xc->shadowIntRegFile[prev][reg_num]; 272 }}); 273 } 274 275 0xB: decode RD { 276 277 0x0: decode SC { 278 format BasicOp { 279 0x0: dvpe({{ 280 Rt.sw = xc->miscRegs.cop0.MVPControl; 281 xc->miscRegs.cop0.MVPControl[EVP] = 0; 282 }}); 283 284 0x1: evpe({{ 285 Rt.sw = xc->miscRegs.cop0.MVPControl; 286 xc->miscRegs.cop0.MVPControl[EVP] = 1; 287 }}); 288 } 289 } 290 291 0x1: decode SC { 292 format BasicOp { 293 0x0: dmt({{ 294 Rt.sw = xc->miscRegs.cop0.VPEControl; 295 xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0; 296 }}); 297 298 0x1: emt({{ 299 Rt.sw = xc->miscRegs.cop0.VPEControl; 300 xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1; 301 }}); 302 } 303 } 304 305 0xC: decode SC { 306 format BasicOp { 307 0x0: di({{ 308 Rt.sw = xc->miscRegs.cop0.Status; 309 xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0; 310 }}); 311 312 0x1: ei({{ 313 Rt.sw = xc->miscRegs.cop0.Status; 314 xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1; 315 }}); 316 } 317 } 318 } 319 320 0xE: BasicOp::wrpgpr({{ 321 //Accessing Previous Shadow Set Register Number 322 uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 323 uint64_t reg_num = Rd.uw; 324 325 xc->shadowIntRegFile[prev][reg_num] = Rt; 326 }}); 327 } 328 329 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 330 0x1: decode FUNCTION { 331 format Trap { 332 0x01: tlbr({{ }}); 333 0x02: tlbwi({{ }}); 334 0x06: tlbwr({{ }}); 335 0x08: tlbp({{ }}); 336 } 337 338 format WarnUnimpl { 339 0x18: eret({{ }}); 340 0x1F: deret({{ }}); 341 0x20: wait({{ }}); 342 } 343 } 344 } 345 346 //Table A-13 MIPS32 COP1 Encoding of rs Field 347 0x1: decode RS_MSB { 348 349 0x0: decode RS_HI { 350 0x0: decode RS_LO { 351 format FloatOp { 352 0x0: mfc1({{ Rt = Fs<31:0>; }}); 353 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}}); 354 0x3: mfhc1({{ Rt = Fs<63:32>;}}); 355 0x4: mtc1({{ Fs<31:0> = Rt}}); 356 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}}); 357 0x7: mftc1({{ Fs<63:32> = Rt}}); 358 } 359 } 360 361 0x1: decode ND { 362 0x0: decode TF { 363 format Branch { 364 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }}); 365 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }}); 366 } 367 } 368 369 0x1: decode TF { 370 format Branch { 371 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }}); 372 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }}); 373 } 374 } 375 } 376 } 377 378 0x1: decode RS_HI { 379 0x2: decode RS_LO { 380 381 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 382 //(( single-word )) 383 0x0: decode RS_HI { 384 0x0: decode RS_LO { 385 format FloatOp { 386 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); 387 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); 388 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); 389 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); 390 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); 391 0x5: abss({{ Fd.sf = abs(Fs.sf);}}); 392 0x6: movs({{ Fd.sf = Fs.sf;}}); 393 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); 394 } 395 } 396 397 0x1: decode RS_LO { 398 //only legal for 64 bit 399 format Float64Op { 400 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}}); 401 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}}); 402 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}}); 403 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}}); 404 } 405 406 format FloatOp { 407 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}}); 408 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}}); 409 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}}); 410 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}}); 411 } 412 } 413 414 0x2: decode RS_LO { 415 0x1: decode MOVCF { 416 format FloatOp { 417 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }}); 418 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}}); 419 } 420 } 421 422 format BasicOp { 423 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 424 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); 425 } 426 427 format Float64Op { 428 0x2: recips({{ Fd = 1 / Fs; }}); 429 0x3: rsqrts{{ Fd = 1 / sqrt(Fs); }}); 430 } 431 } 432 433 0x4: decode RS_LO { 434 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr; 435 Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE); 436 }}); 437 438 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr; 439 Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE); 440 }}); 441 442 //only legal for 64 bit 443 format Float64Op { 444 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr; 445 Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE); 446 }}); 447 448 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }}); 449 } 450 } 451 } 452 453 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 454 0x1: decode RS_HI { 455 0x0: decode RS_LO { 456 format FloatOp { 457 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 458 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 459 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 460 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 461 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 462 0x5: absd({{ Fd.df = abs(Fs.df);}}); 463 0x6: movd({{ Fd.df = Fs.df;}}); 464 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 465 } 466 } 467 468 0x1: decode RS_LO { 469 //only legal for 64 bit 470 format FloatOp64 { 471 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 472 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}}); 473 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}}); 474 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}}); 475 } 476 477 format FloatOp { 478 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 479 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }}); 480 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }}); 481 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }}); 482 } 483 } 484 485 0x2: decode RS_LO { 486 0x1: decode MOVCF { 487 format FloatOp { 488 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }}); 489 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }}); 490 } 491 } 492 493 format BasicOp { 494 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }}); 495 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }}); 496 } 497 498 format FloatOp64 { 499 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 500 0x6: rsqrtd{{ Fd.df = 1 / sqrt(Fs.df) }}); 501 } 502 } 503 504 0x4: decode RS_LO { 505 format FloatOp { 506 0x0: cvt_s_d({{ 507 int rnd_mode = xc->miscRegs.fcsr; 508 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE); 509 }}); 510 511 0x4: cvt_w_d({{ 512 int rnd_mode = xc->miscRegs.fcsr; 513 Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE); 514 }}); 515 } 516 517 //only legal for 64 bit 518 format FloatOp64 { 519 0x5: cvt_l_d({{ 520 int rnd_mode = xc->miscRegs.fcsr; 521 Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE); 522 }}); 523 } 524 } 525 } 526 527 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 528 0x4: decode FUNCTION { 529 format FloatOp { 530 0x10: cvt_s({{ 531 int rnd_mode = xc->miscRegs.fcsr; 532 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); 533 }}); 534 535 0x10: cvt_d({{ 536 int rnd_mode = xc->miscRegs.fcsr; 537 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); 538 }}); 539 } 540 } 541 542 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 543 //Note: "1. Format type L is legal only if 64-bit floating point operations 544 //are enabled." 545 0x5: decode FUNCTION_HI { 546 format FloatOp { 547 0x10: cvt_s_l({{ 548 int rnd_mode = xc->miscRegs.fcsr; 549 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG); 550 }}); 551 552 0x11: cvt_d_l({{ 553 int rnd_mode = xc->miscRegs.fcsr; 554 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG); 555 }}); 556 } 557 } 558 559 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 560 //Note: "1. Format type PS is legal only if 64-bit floating point operations 561 //are enabled. " 562 0x6: decode RS_HI { 563 0x0: decode RS_LO { 564 format FloatOp64 { 565 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 566 //Lower Halves Independently but we take simulator shortcut 567 Fd.df = Fs.df + Ft.df; 568 }}); 569 570 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 571 //Lower Halves Independently but we take simulator shortcut 572 Fd.df = Fs.df - Ft.df; 573 }}); 574 575 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 576 //Lower Halves Independently but we take simulator shortcut 577 Fd.df = Fs.df * Ft.df; 578 }}); 579 580 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 581 //Lower Halves Independently but we take simulator shortcut 582 Fd.df = abs(Fs.df); 583 }}); 584 585 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 586 //Lower Halves Independently but we take simulator shortcut 587 Fd.df = Fs<31:0> | Ft<31:0>; 588 }}); 589 590 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 591 //Lower Halves Independently but we take simulator shortcut 592 Fd.df = -1 * Fs.df; 593 }}); 594 } 595 } 596 597 0x2: decode RS_LO { 598 0x1: decode MOVCF { 599 format FloatOp64 { 600 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}) 601 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}) 602 } 603 } 604 605 } 606 607 0x4: decode RS_LO { 608 0x0: FloatOp64::cvt_s_pu({{ 609 int rnd_mode = xc->miscRegs.fcsr; 610 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI); 611 }}); 612 } 613 614 0x5: decode RS_LO { 615 format FloatOp64 { 616 0x0: cvt_s_pl({{ 617 int rnd_mode = xc->miscRegs.fcsr; 618 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO); 619 }}); 620 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}}); 621 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}}); 622 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}}); 623 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}}); 624 } 625 } 626 } 627 } 628 629 //Table A-19 MIPS32 COP2 Encoding of rs Field 630 0x2: decode RS_MSB { 631 0x0: decode RS_HI { 632 0x0: decode RS_LO { 633 format WarnUnimpl { 634 0x0: mfc2({{ }}); 635 0x2: cfc2({{ }}); 636 0x3: mfhc2({{ }}); 637 0x4: mtc2({{ }}); 638 0x6: ctc2({{ }}); 639 0x7: mftc2({{ }}); 640 } 641 } 642 643 0x1: decode ND { 644 0x0: decode TF { 645 format WarnUnimpl { 646 0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2); 647 0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}}); 648 } 649 } 650 651 0x1: decode TF { 652 format WarnUnimpl { 653 0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}}); 654 0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}}); 655 } 656 } 657 } 658 } 659 } 660 661 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 662 //Note: "COP1X instructions are legal only if 64-bit floating point 663 //operations are enabled." 664 0x3: decode FUNCTION_HI { 665 0x0: decode FUNCTION_LO { 666 format Memory { 667 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.uf; }}); 668 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }}); 669 0x5: luxc1({{ //Need to make EA<2:0> = 0 670 EA = Rs + Rt; 671 }}, 672 {{ Ft<31:0> = Mem.df; }}); 673 } 674 } 675 676 0x1: decode FUNCTION_LO { 677 format Memory { 678 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<31:0>; }}); 679 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<63:0>}}); 680 0x5: suxc1({{ //Need to make EA<2:0> = 0 681 EA = Rs + Rt; 682 }}, 683 {{ Mem.df = Ft<63:0>;}}); 684 0x7: prefx({{ }}); 685 } 686 } 687 688 format FloatOp { 689 0x3: WarnUnimpl::alnv_ps({{ }}); 690 691 format BasicOp { 692 0x4: decode FUNCTION_LO { 693 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 694 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 695 0x6: madd_ps({{ 696 //Must Check for Exception Here... Supposed to Operate on Upper and 697 //Lower Halves Independently but we take simulator shortcut 698 Fd.df = (Fs.df * Fs.df) + Fr.df; 699 }}); 700 } 701 702 0x5: decode FUNCTION_LO { 703 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 704 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 705 0x6: msub_ps({{ 706 //Must Check for Exception Here... Supposed to Operate on Upper and 707 //Lower Halves Independently but we take simulator shortcut 708 Fd.df = (Fs.df * Fs.df) - Fr.df; 709 }}); 710 } 711 712 0x6: decode FUNCTION_LO { 713 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 714 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 715 0x6: nmadd_ps({{ 716 //Must Check for Exception Here... Supposed to Operate on Upper and 717 //Lower Halves Independently but we take simulator shortcut 718 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 719 }}); 720 } 721 722 0x7: decode FUNCTION_LO { 723 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 724 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 725 0x6: nmsub_ps({{ 726 //Must Check for Exception Here... Supposed to Operate on Upper and 727 //Lower Halves Independently but we take simulator shortcut 728 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 729 }}); 730 } 731 } 732 } 733 } 734 735 //MIPS obsolete instructions 736 format Branch { 737 0x4: beql({{ cond = (Rs.sq == 0); }}); 738 0x5: bnel({{ cond = (Rs.sq != 0); }}); 739 0x6: blezl({{ cond = (Rs.sq <= 0); }}); 740 0x7: bgtzl({{ cond = (Rs.sq > 0); }}); 741 } 742 }; 743 744 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 745 746 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 747 0x4: decode FUNCTION_HI { 748 749 0x0: decode FUNCTION_LO { 750 format IntOp { 751 0x0: madd({{ 752 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 753 temp1 = temp1 + (Rs.sw * Rt.sw); 754 xc->miscRegs.hi->temp1<63:32>; 755 xc->miscRegs.lo->temp1<31:0> 756 }}); 757 758 0x1: maddu({{ 759 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 760 temp1 = temp1 + (Rs.uw * Rt.uw); 761 xc->miscRegs.hi->temp1<63:32>; 762 xc->miscRegs.lo->temp1<31:0> 763 }}); 764 765 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 766 767 0x4: msub({{ 768 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 769 temp1 = temp1 - (Rs.sw * Rt.sw); 770 xc->miscRegs.hi->temp1<63:32>; 771 xc->miscRegs.lo->temp1<31:0> 772 }}); 773 774 0x5: msubu({{ 775 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 776 temp1 = temp1 - (Rs.uw * Rt.uw); 777 xc->miscRegs.hi->temp1<63:32>; 778 xc->miscRegs.lo->temp1<31:0> 779 }}); 780 } 781 } 782 783 0x4: decode FUNCTION_LO { 784 format BasicOp { 785 0x0: clz({{ 786 int cnt = 0; 787 int idx = 0; 788 while ( Rs.uw<idx>!= 1) { 789 cnt++; 790 idx--; 791 } 792 793 Rd.uw = cnt; 794 }}); 795 796 0x1: clo({{ 797 int cnt = 0; 798 int idx = 0; 799 while ( Rs.uw<idx>!= 0) { 800 cnt++; 801 idx--; 802 } 803 804 Rd.uw = cnt; 805 }}); 806 } 807 } 808 809 0x7: decode FUNCTION_LO { 810 0x7: WarnUnimpl::sdbbp({{ }}); 811 } 812 } 813 814 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 815 0x7: decode FUNCTION_HI { 816 817 0x0: decode FUNCTION_LO { 818 format WarnUnimpl { 819 0x1: ext({{ }}); 820 0x4: ins({{ }}); 821 } 822 } 823 824 0x1: decode FUNCTION_LO { 825 format WarnUnimpl { 826 0x0: fork({{ }}); 827 0x1: yield({{ }}); 828 } 829 } 830 831 832 //Table A-10 MIPS32 BSHFL Encoding of sa Field 833 0x4: decode SA { 834 835 0x02: WarnUnimpl::wsbh({{ }}); 836 837 format BasicOp { 838 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}}); 839 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}}); 840 } 841 } 842 843 0x6: decode FUNCTION_LO { 844 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}}); 845 } 846 } 847 }; 848 849 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 850 format Memory { 851 0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }}); 852 0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }}); 853 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign); 854 0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }}); 855 0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }}); 856 0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }}); 857 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign); 858 }; 859 860 0x7: FailUnimpl::reserved({{ }}); 861 }; 862 863 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 864 format Memory { 865 0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }}); 866 0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }}); 867 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign); 868 0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }}); 869 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign); 870 }; 871 872 format WarnUnimpl { 873 0x7: cache({{ }}); 874 }; 875 876 }; 877 878 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 879 0x0: WarnUnimpl::ll({{ }}); 880 881 format Memory { 882 0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }}); 883 0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }}); 884 }; 885 }; 886 887 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 888 0x0: WarnUnimpl::sc({{ }}); 889 890 format Memory { 891 0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }}); 892 0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }}); 893 }; 894 895 } 896} 897 898 899