decoder.isa revision 2055
1//////////////////////////////////////////////////////////////////// 2// 3// The actual MIPS32 ISA decoder 4// ----------------------------- 5// The following instructions are specified in the MIPS32 ISA 6// Specification. Decoding closely follows the style specified 7// in the MIPS32 ISAthe specification document starting with Table 8// A-2 (document available @ www.mips.com) 9// 10//@todo: Distinguish "unknown/future" use insts from "reserved" 11// ones 12decode OPCODE_HI default FailUnimpl::unknown() { 13 14 // Derived From ... Table A-2 MIPS32 ISA Manual 15 0x0: decode OPCODE_LO default FailUnimpl::reserved(){ 16 17 0x0: decode FUNCTION_HI { 18 0x0: decode FUNCTION_LO { 19 0x1: decode MOVCI { 20 format BasicOp { 21 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}}); 22 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}}); 23 } 24 } 25 26 format BasicOp { 27 28 //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 29 //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." 30 31 0x0: sll({{ Rd = Rt.uw << SA; }}); 32 33 0x2: decode SRL { 34 0: srl({{ Rd = Rt.uw >> SA; }}); 35 36 //Hardcoded assuming 32-bit ISA, probably need parameter here 37 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 38 } 39 40 0x3: sra({{ Rd = Rt.sw >> SA; }}); 41 42 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 43 44 0x6: decode SRLV { 45 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 46 47 //Hardcoded assuming 32-bit ISA, probably need parameter here 48 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 49 } 50 51 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); 52 } 53 } 54 55 0x1: decode FUNCTION_LO { 56 57 //Table A-3 Note: "Specific encodings of the hint field are used 58 //to distinguish JR from JR.HB and JALR from JALR.HB" 59 format Jump { 60 0x0: jr(IsReturn); 61 0x1: jalr(IsCall,IsReturn); 62 } 63 64 format BasicOp { 65 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 66 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 67 } 68 69 format WarnUnimpl { 70 0x4: syscall({{ xc->syscall()}},IsNonSpeculative); 71 0x5: break({{ }}); 72 0x7: sync({{ }}); 73 } 74 } 75 76 0x2: decode FUNCTION_LO { 77 format BasicOp { 78 0x0: mfhi({{ Rd = xc->miscRegs.hi; }}); 79 0x1: mthi({{ xc->miscRegs.hi = Rs; }}); 80 0x2: mflo({{ Rd = xc->miscRegs.lo; }}); 81 0x3: mtlo({{ xc->miscRegs.lo = Rs; }}); 82 } 83 }; 84 85 0x3: decode FUNCTION_LO { 86 format IntOp { 87 0x0: mult({{ 88 INT64 temp1 = Rs.sw * Rt.sw; 89 xc->miscRegs.hi->temp1<63:32>; 90 xc->miscRegs.lo->temp1<31:0> 91 }}); 92 93 0x1: multu({{ 94 INT64 temp1 = Rs.uw * Rt.uw; 95 xc->miscRegs.hi->temp1<63:32>; 96 xc->miscRegs.lo->temp1<31:0> 97 Rd.sw = Rs.uw * Rt.uw; 98 }}); 99 100 0x2: div({{ 101 xc->miscRegs.hi = Rs.sw % Rt.sw; 102 xc->miscRegs.lo = Rs.sw / Rt.sw; 103 }}); 104 105 0x3: divu({{ 106 xc->miscRegs.hi = Rs.uw % Rt.uw; 107 xc->miscRegs.lo = Rs.uw / Rt.uw; 108 }}); 109 } 110 }; 111 112 0x4: decode FUNCTION_LO { 113 format IntOp { 114 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}}); 115 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}}); 116 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}}); 117 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}}); 118 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}}); 119 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}}); 120 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}}); 121 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}}); 122 } 123 } 124 125 0x5: decode FUNCTION_LO { 126 format IntOp{ 127 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 128 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 129 } 130 }; 131 132 0x6: decode FUNCTION_LO { 133 format Trap { 134 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 135 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 136 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 137 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 138 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 139 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 140 } 141 } 142 } 143 144 0x1: decode REGIMM_HI { 145 0x0: decode REGIMM_LO { 146 format Branch { 147 0x0: bltz({{ cond = (Rs.sq < 0); }}); 148 0x1: bgez({{ cond = (Rs.sq >= 0); }}); 149 150 //MIPS obsolete instructions 151 0x2: bltzl({{ cond = (Rs.sq < 0); }}); 152 0x3: bgezl({{ cond = (Rs.sq >= 0); }}); 153 } 154 } 155 156 0x1: decode REGIMM_LO { 157 format Trap { 158 0x0: tgei({{ cond = (Rs.sw >= INTIMM; }}); 159 0x1: tgeiu({{ cond = (Rs.uw < INTIMM); }}); 160 0x2: tlti({{ cond = (Rs.sw < INTIMM); }}); 161 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 162 0x4: teqi({{ cond = (Rs.sw == INTIMM); }}); 163 0x6: tnei({{ cond = (Rs.sw != INTIMM); }}); 164 } 165 } 166 167 0x2: decode REGIMM_LO { 168 format Branch { 169 0x0: bltzal({{ cond = (Rs.sq < 0); }}); 170 0x1: bgezal({{ cond = (Rs.sq >= 0); }}); 171 172 //MIPS obsolete instructions 173 0x2: bltzall({{ cond = (Rs.sq < 0); }}); 174 0x3: bgezall({{ cond = (Rs.sq >= 0); }}); 175 } 176 } 177 178 0x3: decode REGIMM_LO { 179 format WarnUnimpl { 180 0x7: synci({{ }}); 181 } 182 } 183 } 184 185 format Jump { 186 0x2: j(); 187 0x3: jal(IsCall); 188 } 189 190 format Branch { 191 0x4: beq({{ cond = (Rs.sq == 0); }}); 192 0x5: bne({{ cond = (Rs.sq != 0); }}); 193 0x6: blez({{ cond = (Rs.sq <= 0); }}); 194 0x7: bgtz({{ cond = (Rs.sq > 0); }}); 195 } 196 }; 197 198 0x1: decode OPCODE_LO default FailUnimpl::reserved(){ 199 format IntOp { 200 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }}); 201 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}}); 202 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }}); 203 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }}); 204 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); 205 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); 206 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); 207 0x7: lui({{ Rt = INTIMM << 16}}); 208 }; 209 }; 210 211 0x2: decode OPCODE_LO default FailUnimpl::reserved(){ 212 213 //Table A-11 MIPS32 COP0 Encoding of rs Field 214 0x0: decode RS_MSB { 215 0x0: decode RS { 216 217 format BasicOp { 218 0x0: mfc0({{ 219 //The contents of the coprocessor 0 register specified by the 220 //combination of rd and sel are loaded into general register 221 //rt. Note that not all coprocessor 0 registers support the 222 //sel field. In those instances, the sel field must be zero. 223 224 if (SEL > 0) 225 panic("Can't Handle Cop0 with register select yet\n"); 226 227 uint64_t reg_num = Rd.uw; 228 229 Rt = xc->miscRegs.cop0[reg_num]; 230 }}); 231 232 0xC: mtc0({{ 233 //The contents of the coprocessor 0 register specified by the 234 //combination of rd and sel are loaded into general register 235 //rt. Note that not all coprocessor 0 registers support the 236 //sel field. In those instances, the sel field must be zero. 237 238 if (SEL > 0) 239 panic("Can't Handle Cop0 with register select yet\n"); 240 241 uint64_t reg_num = Rd.uw; 242 243 xc->miscRegs.cop0[reg_num] = Rt; 244 }}); 245 246 0xA: rdpgpr({{ 247 //Accessing Previous Shadow Set Register Number 248 uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 249 uint64_t reg_num = Rt.uw; 250 251 Rd = xc->shadowIntRegFile[prev][reg_num]; 252 }}); 253 } 254 255 0xB: decode SC { 256 format BasicOp { 257 0x0: di({{ 258 //Accessing Coprocessor 0 "Status" Register 259 Rt.sw = xc->miscRegs.cop0[12]; 260 xc->miscRegs.cop0[12][INTERRUPT_ENABLE] = 0; 261 }}); 262 263 0x1: ei({{ 264 //Accessing Coprocessor 0 "Status" Register 265 Rt.sw = xc->miscRegs.cop0[12]; 266 xc->miscRegs.cop0[12][INTERRUPT_ENABLE] = 1; 267 }}); 268 } 269 } 270 271 0xE: BasicOp::wrpgpr({{ 272 //Accessing Previous Shadow Set Register Number 273 uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 274 uint64_t reg_num = Rd.uw; 275 276 xc->shadowIntRegFile[prev][reg_num] = Rt; 277 }}); 278 } 279 280 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 281 0x1: decode FUNCTION { 282 format Trap { 283 0x01: tlbr({{ }}); 284 0x02: tlbwi({{ }}); 285 0x06: tlbwr({{ }}); 286 0x08: tlbp({{ }}); 287 } 288 289 format WarnUnimpl { 290 0x18: eret({{ }}); 291 0x1F: deret({{ }}); 292 0x20: wait({{ }}); 293 } 294 } 295 } 296 297 //Table A-13 MIPS32 COP1 Encoding of rs Field 298 0x1: decode RS_MSB { 299 300 0x0: decode RS_HI { 301 0x0: decode RS_LO { 302 format FloatOp { 303 0x0: mfc1({{ Rt = Fs<31:0>; }}); 304 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}}); 305 0x3: mfhc1({{ Rt = Fs<63:32>;}}); 306 0x4: mtc1({{ Fs<31:0> = Rt}}); 307 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}}); 308 0x7: mftc1({{ Fs<63:32> = Rt}}); 309 } 310 } 311 312 0x1: decode ND { 313 0x0: decode TF { 314 format Branch { 315 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }}); 316 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }}); 317 } 318 } 319 320 0x1: decode TF { 321 format Branch { 322 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }}); 323 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }}); 324 } 325 } 326 } 327 } 328 329 0x1: decode RS_HI { 330 0x2: decode RS_LO { 331 332 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 333 //(( single-word )) 334 0x0: decode RS_HI { 335 0x0: decode RS_LO { 336 format FloatOp { 337 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); 338 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); 339 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); 340 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); 341 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); 342 0x5: abss({{ Fd.sf = abs(Fs.sf);}}); 343 0x6: movs({{ Fd.sf = Fs.sf;}}); 344 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); 345 } 346 } 347 348 0x1: decode RS_LO { 349 //only legal for 64 bit 350 format Float64Op { 351 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}}); 352 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}}); 353 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}}); 354 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}}); 355 } 356 357 format FloatOp { 358 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}}); 359 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}}); 360 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}}); 361 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}}); 362 } 363 } 364 365 0x2: decode RS_LO { 366 0x1: decode MOVCF { 367 format FloatOp { 368 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }}); 369 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}}); 370 } 371 } 372 373 format BasicOp { 374 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 375 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); 376 } 377 378 format Float64Op { 379 0x2: recips({{ Fd = 1 / Fs; }}); 380 0x3: rsqrts{{ Fd = 1 / sqrt(Fs); }}); 381 } 382 } 383 384 0x4: decode RS_LO { 385 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr; 386 Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE); 387 }}); 388 389 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr; 390 Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE); 391 }}); 392 393 //only legal for 64 bit 394 format Float64Op { 395 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr; 396 Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE); 397 }}); 398 399 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }}); 400 } 401 } 402 } 403 404 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 405 0x1: decode RS_HI { 406 0x0: decode RS_LO { 407 format FloatOp { 408 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 409 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 410 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 411 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 412 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 413 0x5: absd({{ Fd.df = abs(Fs.df);}}); 414 0x6: movd({{ Fd.df = Fs.df;}}); 415 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 416 } 417 } 418 419 0x1: decode RS_LO { 420 //only legal for 64 bit 421 format FloatOp64 { 422 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 423 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}}); 424 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}}); 425 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}}); 426 } 427 428 format FloatOp { 429 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 430 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }}); 431 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }}); 432 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }}); 433 } 434 } 435 436 0x2: decode RS_LO { 437 0x1: decode MOVCF { 438 format FloatOp { 439 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }}); 440 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }}); 441 } 442 } 443 444 format BasicOp { 445 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }}); 446 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }}); 447 } 448 449 format FloatOp64 { 450 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 451 0x6: rsqrtd{{ Fd.df = 1 / sqrt(Fs.df) }}); 452 } 453 } 454 455 0x4: decode RS_LO { 456 format FloatOp { 457 0x0: cvt_s_d({{ 458 int rnd_mode = xc->miscRegs.fcsr; 459 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE); 460 }}); 461 462 0x4: cvt_w_d({{ 463 int rnd_mode = xc->miscRegs.fcsr; 464 Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE); 465 }}); 466 } 467 468 //only legal for 64 bit 469 format FloatOp64 { 470 0x5: cvt_l_d({{ 471 int rnd_mode = xc->miscRegs.fcsr; 472 Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE); 473 }}); 474 } 475 } 476 } 477 478 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 479 0x4: decode FUNCTION { 480 format FloatOp { 481 0x10: cvt_s({{ 482 int rnd_mode = xc->miscRegs.fcsr; 483 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); 484 }}); 485 486 0x10: cvt_d({{ 487 int rnd_mode = xc->miscRegs.fcsr; 488 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); 489 }}); 490 } 491 } 492 493 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 494 //Note: "1. Format type L is legal only if 64-bit floating point operations 495 //are enabled." 496 0x5: decode FUNCTION_HI { 497 format FloatOp { 498 0x10: cvt_s_l({{ 499 int rnd_mode = xc->miscRegs.fcsr; 500 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG); 501 }}); 502 503 0x11: cvt_d_l({{ 504 int rnd_mode = xc->miscRegs.fcsr; 505 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG); 506 }}); 507 } 508 } 509 510 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 511 //Note: "1. Format type PS is legal only if 64-bit floating point operations 512 //are enabled. " 513 0x6: decode RS_HI { 514 0x0: decode RS_LO { 515 format FloatOp64 { 516 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 517 //Lower Halves Independently but we take simulator shortcut 518 Fd.df = Fs.df + Ft.df; 519 }}); 520 521 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 522 //Lower Halves Independently but we take simulator shortcut 523 Fd.df = Fs.df - Ft.df; 524 }}); 525 526 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 527 //Lower Halves Independently but we take simulator shortcut 528 Fd.df = Fs.df * Ft.df; 529 }}); 530 531 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 532 //Lower Halves Independently but we take simulator shortcut 533 Fd.df = abs(Fs.df); 534 }}); 535 536 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 537 //Lower Halves Independently but we take simulator shortcut 538 Fd.df = Fs<31:0> | Ft<31:0>; 539 }}); 540 541 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 542 //Lower Halves Independently but we take simulator shortcut 543 Fd.df = -1 * Fs.df; 544 }}); 545 } 546 } 547 548 0x2: decode RS_LO { 549 0x1: decode MOVCF { 550 format FloatOp64 { 551 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}) 552 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}) 553 } 554 } 555 556 } 557 558 0x4: decode RS_LO { 559 0x0: FloatOp64::cvt_s_pu({{ 560 int rnd_mode = xc->miscRegs.fcsr; 561 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI); 562 }}); 563 } 564 565 0x5: decode RS_LO { 566 format FloatOp64 { 567 0x0: cvt_s_pl({{ 568 int rnd_mode = xc->miscRegs.fcsr; 569 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO); 570 }}); 571 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}}); 572 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}}); 573 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}}); 574 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}}); 575 } 576 } 577 } 578 } 579 580 //Table A-19 MIPS32 COP2 Encoding of rs Field 581 0x2: decode RS_MSB { 582 0x0: decode RS_HI { 583 0x0: decode RS_LO { 584 format WarnUnimpl { 585 0x0: mfc2({{ }}); 586 0x2: cfc2({{ }}); 587 0x3: mfhc2({{ }}); 588 0x4: mtc2({{ }}); 589 0x6: ctc2({{ }}); 590 0x7: mftc2({{ }}); 591 } 592 } 593 594 0x1: decode ND { 595 0x0: decode TF { 596 format WarnUnimpl { 597 0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2); 598 0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}}); 599 } 600 } 601 602 0x1: decode TF { 603 format WarnUnimpl { 604 0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}}); 605 0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}}); 606 } 607 } 608 } 609 } 610 } 611 612 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 613 //Note: "COP1X instructions are legal only if 64-bit floating point 614 //operations are enabled." 615 0x3: decode FUNCTION_HI { 616 0x0: decode FUNCTION_LO { 617 format Memory { 618 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.uf; }}); 619 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }}); 620 0x5: luxc1({{ //Need to make EA<2:0> = 0 621 EA = Rs + Rt; 622 }}, 623 {{ Ft<31:0> = Mem.df; }}); 624 } 625 } 626 627 0x1: decode FUNCTION_LO { 628 format Memory { 629 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<31:0>; }}); 630 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<63:0>}}); 631 0x5: suxc1({{ //Need to make EA<2:0> = 0 632 EA = Rs + Rt; 633 }}, 634 {{ Mem.df = Ft<63:0>;}}); 635 0x7: prefx({{ }}); 636 } 637 } 638 639 format FloatOp { 640 0x3: WarnUnimpl::alnv_ps({{ }}); 641 642 format BasicOp { 643 0x4: decode FUNCTION_LO { 644 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 645 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 646 0x6: madd_ps({{ 647 //Must Check for Exception Here... Supposed to Operate on Upper and 648 //Lower Halves Independently but we take simulator shortcut 649 Fd.df = (Fs.df * Fs.df) + Fr.df; 650 }}); 651 } 652 653 0x5: decode FUNCTION_LO { 654 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 655 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 656 0x6: msub_ps({{ 657 //Must Check for Exception Here... Supposed to Operate on Upper and 658 //Lower Halves Independently but we take simulator shortcut 659 Fd.df = (Fs.df * Fs.df) - Fr.df; 660 }}); 661 } 662 663 0x6: decode FUNCTION_LO { 664 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 665 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 666 0x6: nmadd_ps({{ 667 //Must Check for Exception Here... Supposed to Operate on Upper and 668 //Lower Halves Independently but we take simulator shortcut 669 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 670 }}); 671 } 672 673 0x7: decode FUNCTION_LO { 674 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 675 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 676 0x6: nmsub_ps({{ 677 //Must Check for Exception Here... Supposed to Operate on Upper and 678 //Lower Halves Independently but we take simulator shortcut 679 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 680 }}); 681 } 682 } 683 } 684 } 685 686 //MIPS obsolete instructions 687 format Branch { 688 0x4: beql({{ cond = (Rs.sq == 0); }}); 689 0x5: bnel({{ cond = (Rs.sq != 0); }}); 690 0x6: blezl({{ cond = (Rs.sq <= 0); }}); 691 0x7: bgtzl({{ cond = (Rs.sq > 0); }}); 692 } 693 }; 694 695 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 696 697 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 698 0x4: decode FUNCTION_HI { 699 700 0x0: decode FUNCTION_LO { 701 format IntOp { 702 0x0: madd({{ 703 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 704 temp1 = temp1 + (Rs.sw * Rt.sw); 705 xc->miscRegs.hi->temp1<63:32>; 706 xc->miscRegs.lo->temp1<31:0> 707 }}); 708 709 0x1: maddu({{ 710 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 711 temp1 = temp1 + (Rs.uw * Rt.uw); 712 xc->miscRegs.hi->temp1<63:32>; 713 xc->miscRegs.lo->temp1<31:0> 714 }}); 715 716 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 717 718 0x4: msub({{ 719 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 720 temp1 = temp1 - (Rs.sw * Rt.sw); 721 xc->miscRegs.hi->temp1<63:32>; 722 xc->miscRegs.lo->temp1<31:0> 723 }}); 724 725 0x5: msubu({{ 726 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 727 temp1 = temp1 - (Rs.uw * Rt.uw); 728 xc->miscRegs.hi->temp1<63:32>; 729 xc->miscRegs.lo->temp1<31:0> 730 }}); 731 } 732 } 733 734 0x4: decode FUNCTION_LO { 735 format BasicOp { 736 0x0: clz({{ 737 int cnt = 0; 738 int idx = 0; 739 while ( Rs.uw<idx>!= 1) { 740 cnt++; 741 idx--; 742 } 743 744 Rd.uw = cnt; 745 }}); 746 747 0x1: clo({{ 748 int cnt = 0; 749 int idx = 0; 750 while ( Rs.uw<idx>!= 0) { 751 cnt++; 752 idx--; 753 } 754 755 Rd.uw = cnt; 756 }}); 757 } 758 } 759 760 0x7: decode FUNCTION_LO { 761 0x7: WarnUnimpl::sdbbp({{ }}); 762 } 763 } 764 765 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 766 0x7: decode FUNCTION_HI { 767 768 0x0: decode FUNCTION_LO { 769 format WarnUnimpl { 770 0x1: ext({{ }}); 771 0x4: ins({{ }}); 772 } 773 } 774 775 //Table A-10 MIPS32 BSHFL Encoding of sa Field 776 0x4: decode SA { 777 778 0x02: WarnUnimpl::wsbh({{ }}); 779 780 format BasicOp { 781 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}}); 782 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}}); 783 } 784 } 785 786 0x6: decode FUNCTION_LO { 787 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}}); 788 } 789 } 790 }; 791 792 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 793 format Memory { 794 0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }}); 795 0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }}); 796 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign); 797 0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }}); 798 0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }}); 799 0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }}); 800 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign); 801 }; 802 803 0x7: FailUnimpl::reserved({{ }}); 804 }; 805 806 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 807 format Memory { 808 0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }}); 809 0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }}); 810 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign); 811 0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }}); 812 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign); 813 }; 814 815 format WarnUnimpl { 816 0x7: cache({{ }}); 817 }; 818 819 }; 820 821 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 822 0x0: WarnUnimpl::ll({{ }}); 823 824 format Memory { 825 0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }}); 826 0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }}); 827 }; 828 }; 829 830 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 831 0x0: WarnUnimpl::sc({{ }}); 832 833 format Memory { 834 0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }}); 835 0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }}); 836 }; 837 838 } 839} 840 841 842