decoder.isa revision 2042 
1////////////////////////////////////////////////////////////////////
2//
3// The actual MIPS32 ISA decoder 
4// -----------------------------
5// The following instructions are specified in the MIPS32 ISA
6// Specification. Decoding closely follows the style specified 
7// in the MIPS32 ISAthe specification document starting with Table
8// A-2 (document available @ www.mips.com)
9//
10//@todo: Distinguish "unknown/future" use insts from "reserved"
11// ones
12decode OPCODE_HI default FailUnimpl::unknown() {
13    
14    // Derived From ... Table A-2 MIPS32 ISA Manual
15    0x0: decode OPCODE_LO default FailUnimpl::reserved(){
16	
17	0x0: decode FUNCTION_HI {
18	    0x0: decode FUNCTION_LO {
19	      0x1: decode MOVCI {
20		format Move {
21		  0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}});
22		  1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}});
23		}  
24	      }
25
26	      format BasicOp {
27
28		//Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 
29		//are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
30
31		0x0: sll({{ Rd = Rt.uw << SA; }});
32		
33		0x2: decode SRL {
34		   0: srl({{ Rd = Rt.uw >> SA; }});
35
36		   //Hardcoded assuming 32-bit ISA, probably need parameter here
37		   1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
38		 }	
39	
40		 0x3: sra({{ Rd = Rt.sw >> SA; }});
41		
42		 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
43
44		 0x6: decode SRLV {
45		   0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
46
47		   //Hardcoded assuming 32-bit ISA, probably need parameter here
48		   1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
49		 }
50
51		 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }});
52	      }
53	    }
54
55	    0x1: decode FUNCTION_LO {
56	     
57	      //Table A-3 Note: "Specific encodings of the hint field are used 
58	      //to distinguish JR from JR.HB and JALR from JALR.HB"
59	      format Jump {
60		0x0: jr(IsReturn);
61		0x1: jalr(IsCall,IsReturn);
62	      }
63
64	      format Move {
65		0x2: movz({{ if (Rt == 0) Rd = Rs; }});
66		0x3: movn({{ if (Rt != 0) Rd = Rs; }});
67	      }
68
69	      format Trap {
70	      	0x4: syscall({{ xc->syscall()}},IsNonSpeculative);
71	      	0x5: break({{ }});
72	      	0x7: sync({{ }});
73	      }
74	    }
75
76	    0x2: decode FUNCTION_LO {
77	      format BasicOp {
78		0x0: mfhi({{ Rd = xc->miscRegs.Hi; }});
79		0x1: mthi({{ xc->miscRegs.Hi = Rs; }});
80		0x2: mflo({{ Rd = xc->miscRegs.Lo; }});
81		0x3: mtlo({{ xc->miscRegs.Lo = Rs; }});
82	      }
83	    };
84
85	    0x3: decode FUNCTION_LO {
86	      format IntOp {
87		0x0: mult({{ 
88			INT64 temp1 = Rs.sw * Rt.sw;
89			xc->miscRegs.Hi->temp1<63:32>;
90			xc->miscRegs.Lo->temp1<31:0>
91		}});
92
93		0x1: multu({{ 
94			INT64 temp1 = Rs.uw * Rt.uw;
95			xc->miscRegs.Hi->temp1<63:32>;
96			xc->miscRegs.Lo->temp1<31:0>
97			Rd.sw = Rs.uw * Rt.uw;
98		}});
99
100		0x2: div({{ 
101			xc->miscRegs.Hi = Rs.sw % Rt.sw;
102			xc->miscRegs.Lo = Rs.sw / Rt.sw;
103			}});	
104
105		0x3: divu({{ 
106			xc->miscRegs.Hi = Rs.uw % Rt.uw;
107			xc->miscRegs.Lo = Rs.uw / Rt.uw;	
108			}});
109	      }
110	    };
111
112	    0x4: decode FUNCTION_LO {
113	      format IntOp {
114		0x0: add({{  Rd.sw = Rs.sw + Rt.sw;}});
115		0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}});
116		0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}});
117		0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}});	      
118		0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}});
119		0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}});
120		0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}});
121		0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}});
122	      }
123	    }
124
125	    0x5: decode FUNCTION_LO {
126	      format IntOp{
127		0x2: slt({{  Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
128		0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
129	      }
130	    };
131
132	    0x6: decode FUNCTION_LO {
133	      format Trap {
134		 0x0: tge({{ }});
135		 0x1: tgeu({{ }});
136		 0x2: tlt({{ }});
137		 0x3: tltu({{ }});
138		 0x4: teq({{ }});
139		 0x6: tne({{ }});
140	      }
141	    }
142	}
143
144	0x1: decode REGIMM_HI {
145	    0x0: decode REGIMM_LO {
146	      format Branch {
147		0x0: bltz({{ cond = (Rs.sq < 0); }});
148		0x1: bgez({{ cond = (Rs.sq >= 0); }});
149
150		//MIPS obsolete instructions
151		0x2: bltzl({{ cond = (Rs.sq < 0); }});
152		0x3: bgezl({{ cond = (Rs.sq >= 0); }});
153	      }
154	    }
155
156	    0x1: decode REGIMM_LO {
157	      format Trap {
158		 0x0: tgei({{ }});
159		 0x1: tgeiu({{ }});
160		 0x2: tlti({{ }});
161		 0x3: tltiu({{ }});
162		 0x4: teqi({{ }});
163		 0x6: tnei({{ }});
164	      }
165	    }
166
167	    0x2: decode REGIMM_LO {
168	      format Branch {
169		0x0: bltzal({{ cond = (Rs.sq < 0); }});
170		0x1: bgezal({{ cond = (Rs.sq >= 0); }});
171
172		//MIPS obsolete instructions
173		0x2: bltzall({{ cond = (Rs.sq < 0); }});
174		0x3: bgezall({{ cond = (Rs.sq >= 0); }});
175	      }
176	    }
177
178	    0x3: decode REGIMM_LO {
179	      format Trap {
180	      	0x7: synci({{ }});
181	      }
182	    }      
183	}
184
185	format Jump {
186	    0x2: j();
187	    0x3: jal(IsCall);
188	}
189
190	format Branch {
191	    0x4: beq({{ cond = (Rs.sq == 0); }});
192	    0x5: bne({{ cond = (Rs.sq !=  0); }});
193	    0x6: blez({{ cond = (Rs.sq <= 0); }});
194	    0x7: bgtz({{ cond = (Rs.sq > 0); }});
195	}
196    };
197
198    0x1: decode OPCODE_LO default FailUnimpl::reserved(){
199	format IntOp {
200	    0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }});
201	    0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}});
202	    0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }});
203	    0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }});
204	    0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
205	    0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
206	    0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
207	    0x7: lui({{ Rt = INTIMM << 16}});
208	};
209    };
210
211    0x2: decode OPCODE_LO default FailUnimpl::reserved(){
212
213      //Table A-11 MIPS32 COP0 Encoding of rs Field
214      0x0: decode RS_MSB {
215	0x0: decode RS {
216	  0x0: mfc0({{ }});
217	  0xC: mtc0({{ }});
218	  0xA: rdpgpr({{ }});
219
220  	  0xB: decode SC {
221	    format BasicOp {
222		0x0: di({{ }});
223		0x1: ei({{ }}); 	      
224	    }
225	  }
226
227  	  0xE: wrpgpr({{ }});
228	}
229
230	//Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
231	0x1: decode FUNCTION {
232	  format Trap {
233	        0x01: tlbr({{ }});
234	        0x02: tlbwi({{ }});
235	        0x06: tlbwr({{ }});
236	        0x08: tlbp({{ }});
237	  }
238
239	  format BasicOp {
240	        0x18: eret({{ }});
241	        0x1F: deret({{ }});
242	        0x20: wait({{ }});
243          }
244	}
245      }
246
247      //Table A-13 MIPS32 COP1 Encoding of rs Field
248      0x1: decode RS_MSB {
249
250	0x0: decode RS_HI {
251	  0x0: decode RS_LO {
252	    0x0: mfc1({{ }});
253	    0x2: cfc1({{ }});
254	    0x3: mfhc1({{ }});
255	    0x4: mtc1({{ }});
256	    0x6: ctc1({{ }});
257	    0x7: mftc1({{ }});
258	  }
259
260	  0x1: decode ND {
261	    0x0: decode TF {
262	      format Branch {
263	      	0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
264	      	0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
265	      }
266	    }
267
268	    0x1: decode TF {
269	      format Branch {
270		0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
271	      	0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
272	      }
273	    }
274	  }
275	}
276
277	0x1: decode RS_HI {
278	  0x2: decode RS_LO {
279
280	    //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
281	    //(( single-word ))
282	    0x0: decode RS_HI {
283	      0x0: decode RS_LO {
284		0x0: add_fmt({{ }});
285		0x1: sub_fmt({{ }});
286		0x2: mul_fmt({{ }});
287		0x3: div_fmt({{ }});
288		0x4: sqrt_fmt({{ }});
289		0x5: abs_fmt({{ }});
290		0x6: mov_fmt({{ }});
291		0x7: neg_fmt({{ }});
292	      }
293
294	      0x1: decode RS_LO {
295		//only legal for 64 bit
296		format mode64 {
297		  0x0: round_l({{ }});
298		  0x1: trunc_l({{ }});
299		  0x2: ceil_l({{ }});
300		  0x3: floor_l({{ }});
301		}
302
303		0x4: round_w({{ }});
304		0x5: trunc_w({{ }});
305		0x6: ceil_w({{ }});
306		0x7: floor_w({{ }});
307	      }
308
309	      0x2: decode RS_LO {
310		0x1: decode MOVCF {
311		  0x0: movf_fmt({{ }});
312		  0x1: movt_fmt({{ }});
313		}
314
315		format Move {
316		  0x2: movz({{ if (Rt == 0) Rd = Rs; }});
317         	  0x3: movn({{ if (Rt != 0) Rd = Rs; }});
318	      	}
319
320		format mode64 {
321		  0x2: recip({{ }});
322		  0x3: rsqrt{{ }});
323		}
324	      }
325
326	      0x4: decode RS_LO {
327		0x1: cvt_d({{ }});
328		0x4: cvt_w({{ }});
329
330		//only legal for 64 bit
331		format mode64 {
332		  0x5: cvt_l({{ }});
333		  0x6: cvt_ps({{ }});
334		}
335	      }
336	    }
337
338	    //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
339	    0x1: decode RS_HI {
340	      0x0: decode RS_LO {
341		0x0: add_fmt({{ }});
342		0x1: sub_fmt({{ }});
343		0x2: mul_fmt({{ }});
344		0x3: div_fmt({{ }});
345		0x4: sqrt_fmt({{ }});
346		0x5: abs_fmt({{ }});
347		0x6: mov_fmt({{ }});
348		0x7: neg_fmt({{ }});
349	      }
350
351	      0x1: decode RS_LO {
352		//only legal for 64 bit
353		format mode64 {
354		  0x0: round_l({{ }});
355		  0x1: trunc_l({{ }});
356		  0x2: ceil_l({{ }});
357		  0x3: floor_l({{ }});
358		}
359
360		0x4: round_w({{ }});
361		0x5: trunc_w({{ }});
362		0x6: ceil_w({{ }});
363		0x7: floor_w({{ }});
364	      }
365
366	      0x2: decode RS_LO {
367		0x1: decode MOVCF {
368		  0x0: movf_fmt({{ }});
369		  0x1: movt_fmt({{ }});
370		}
371
372		format Move {
373		  0x2: movz({{ if (Rt == 0) Rd = Rs; }});
374         	  0x3: movn({{ if (Rt != 0) Rd = Rs; }});
375	      	}
376
377		format mode64 {
378		  0x5: recip({{ }});
379		  0x6: rsqrt{{ }});
380		}
381	      }
382
383	      0x4: decode RS_LO {
384		0x0: cvt_s({{ }});
385		0x4: cvt_w({{ }});
386
387		//only legal for 64 bit
388		format mode64 {
389		  0x5: cvt_l({{ }});
390		}
391	      }
392	    }
393
394	    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
395	    0x4: decode FUNCTION {
396	      0x10: cvt_s({{ }});
397	      0x10: cvt_d({{ }});
398	    }
399
400	    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
401	    //Note: "1. Format type L is legal only if 64-bit floating point operations 
402	    //are enabled."
403	    0x5: decode FUNCTION_HI {
404	      0x10: cvt_s({{ }});
405	      0x11: cvt_d({{ }});
406	    }
407
408	    //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
409	    //Note: "1. Format type PS is legal only if 64-bit floating point operations 
410	    //are enabled. "
411	    0x6: decode RS_HI {
412	      0x0: decode RS_LO {
413		0x0: add_fmt({{ }});
414		0x1: sub_fmt({{ }});
415		0x2: mul_fmt({{ }});
416		0x5: abs_fmt({{ }});
417		0x6: mov_fmt({{ }});
418		0x7: neg_fmt({{ }});
419	      }
420
421	      0x2: decode RS_LO {
422		0x1: decode MOVCF {
423		  0x0: movf_fmt({{ }});
424		  0x1: movt_fmt({{ }});
425		}
426
427	      }
428
429	      0x4: decode RS_LO {
430		0x0: cvt_s_pu({{ }});
431	      }
432
433	      0x5: decode RS_LO {
434		0x0: cvt_s_pl({{ }});
435		0x4: pll_s_pl({{ }});
436		0x5: plu_s_pl({{ }});
437		0x6: pul_s_pl({{ }});
438		0x7: puu_s_pl({{ }});
439	      }
440	    }
441      }
442
443      //Table A-19 MIPS32 COP2 Encoding of rs Field 
444      0x2: decode RS_MSB {
445	0x0: decode RS_HI {
446	  0x0: decode RS_LO {
447	    0x0: mfc2({{ }});
448	    0x2: cfc2({{ }});
449	    0x3: mfhc2({{ }});
450	    0x4: mtc2({{ }});
451	    0x6: ctc2({{ }});
452	    0x7: mftc2({{ }});
453	  }
454
455	  0x1: decode ND {
456	    0x0: decode TF {
457	      format Branch { 
458	        0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2);
459	        0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
460	      }
461	    }
462
463	    0x1: decode TF {
464	      format Branch {
465	      	0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}});
466	      	0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
467	      }
468	    }
469	  }
470	}
471      }
472
473      //Table A-20 MIPS64 COP1X Encoding of Function Field 1
474      //Note: "COP1X instructions are legal only if 64-bit floating point 
475      //operations are enabled."
476      0x3: decode FUNCTION_HI {
477	0x0: decode FUNCTION_LO {
478	  0x0: lwxc1({{ }});
479	  0x1: ldxc1({{ }});
480	  0x5: luxc1({{ }});
481	}
482
483	0x1: decode FUNCTION_LO {
484	  0x0: swxc1({{ }});
485	  0x1: sdxc1({{ }});
486	  0x5: suxc1({{ }});
487	  0x7: prefx({{ }});
488	}
489
490	0x3: alnv_ps({{ }});
491
492	0x4: decode FUNCTION_LO {
493	  0x0: madd_s({{ }});
494	  0x1: madd_d({{ }});
495	  0x6: madd_ps({{ }});
496	}
497
498	0x5: decode FUNCTION_LO {
499	  0x0: msub_s({{ }});
500	  0x1: msub_d({{ }});
501	  0x6: msub_ps({{ }});	
502	}
503
504	0x6: decode FUNCTION_LO {
505	  0x0: nmadd_s({{ }});
506	  0x1: nmadd_d({{ }});
507	  0x6: nmadd_ps({{ }});	
508	}
509
510	0x7: decode FUNCTION_LO {
511	  0x0: nmsub_s({{ }});
512	  0x1: nmsub_d({{ }});
513	  0x6: nmsub_ps({{ }});
514	}
515      } 
516
517      //MIPS obsolete instructions 
518      0x4: beql({{ cond = (Rs.sq == 0); }});
519      0x5: bnel({{ cond = (Rs.sq != 0); }});
520      0x6: blezl({{ cond = (Rs.sq <= 0); }});
521      0x7: bgtzl({{ cond = (Rs.sq > 0); }});
522    };
523
524    0x3: decode OPCODE_LO default FailUnimpl::reserved() {
525
526	//Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
527	0x4: decode FUNCTION_HI {
528
529	    0x0: decode FUNCTION_LO {
530		format IntOp {
531		   0x0: madd({{ 
532			INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
533			temp1 = temp1 + (Rs.sw * Rt.sw);
534			xc->miscRegs.Hi->temp1<63:32>;
535			xc->miscRegs.Lo->temp1<31:0>
536			}});
537
538	      	   0x1: maddu({{ 
539			INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
540			temp1 = temp1 + (Rs.uw * Rt.uw);
541			xc->miscRegs.Hi->temp1<63:32>;
542			xc->miscRegs.Lo->temp1<31:0>
543			}});
544
545	      	   0x2: mul({{ 	Rd.sw = Rs.sw * Rt.sw; 	}});
546
547	      	   0x4: msub({{ 
548			INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
549			temp1 = temp1 - (Rs.sw * Rt.sw);
550			xc->miscRegs.Hi->temp1<63:32>;
551			xc->miscRegs.Lo->temp1<31:0>
552			}});
553
554	      	   0x5: msubu({{ 
555			INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
556			temp1 = temp1 - (Rs.uw * Rt.uw);
557			xc->miscRegs.Hi->temp1<63:32>;
558			xc->miscRegs.Lo->temp1<31:0>
559			}});
560		}
561	    }
562
563	    0x4: decode FUNCTION_LO {
564	      0x0: clz({{ }});
565	      0x1: clo({{ }});
566	    }
567
568	    0x7: decode FUNCTION_LO {
569	      0x7: sdbbp({{ }});
570	    }	      
571	}
572
573	//Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture
574	0x7: decode FUNCTION_HI {
575	  
576	  0x0: decode FUNCTION_LO {
577	    0x1: ext({{ }});
578	    0x4: ins({{ }});
579	  }
580
581	  //Table A-10 MIPS32 BSHFL Encoding of sa Field
582	  0x4: decode SA {
583	    0x02: wsbh({{ }});
584	    0x10: seb({{ }});
585	    0x18: seh({{ }});
586	  }
587
588	  0x6: decode FUNCTION_LO {
589	    0x7: rdhwr({{ }});
590	  }
591	}
592    };
593
594    0x4: decode OPCODE_LO default FailUnimpl::reserved() {
595	format Memory {
596	    0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }});
597	    0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }});
598	    0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign);
599	    0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }});
600	    0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }});
601	    0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }});
602	    0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign);
603	};
604
605	0x7: FailUnimpl::reserved({{ }});
606    };
607
608    0x5: decode OPCODE_LO default FailUnimpl::reserved() {
609	format Memory {
610	    0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }});
611	    0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }});
612	    0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
613	    0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});
614	    0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
615	};
616
617	format FailUnimpl {
618	    0x4: reserved({{ }});
619	    0x5: reserved({{ }});
620	    0x7: cache({{ }});
621	};
622
623    };
624
625    0x6: decode OPCODE_LO default FailUnimpl::reserved() {
626	format Memory {
627	    0x0: ll({{ }});
628	    0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
629	    0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }});
630	};
631    };
632
633    0x7: decode OPCODE_LO default FailUnimpl::reserved() {
634	format Memory {
635	    0x0: sc({{ }});
636	    0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }});
637	    0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }});
638	};
639
640    }
641}
642
643
644