decoder.isa revision 2024 
1////////////////////////////////////////////////////////////////////
2//
3// The actual MIPS32 ISA decoder
4// -----------------------------
5// The following instructions are specified in the MIPS32 ISA
6// Specification. Decoding closely follows the style specified
7// in the MIPS32 ISAthe specification document starting with Table
8// A-2 (document available @ www.mips.com)
9//
10//
11decode OPCODE_HI default FailUnimpl::unknown() {
12
13    // Derived From ... Table A-2 MIPS32 ISA Manual
14    0x0: decode OPCODE_LO {
15
16        0x0: decode SPECIAL {
17            0x0:;
18            0x1:;
19            0x2:;
20            0x3:;
21            0x4:;
22            0x5:;
23            0x6:;
24        }
25
26        0x1: decode REGIMM {
27            0x0:;
28            0x1:;
29            0x2:;
30            0x3:;
31            0x4:;
32            0x5:;
33            0x6:;
34        }
35
36        format Jump {
37            0x2: j({{ }});
38            0x3: jal({{ }});
39        }
40
41        format Branch {
42            0x4: beq({{ }});
43            0x5: bne({{ }});
44            0x6: blez({{ }});
45            0x7: bgtz({{ }});
46        }
47    };
48
49    0x1: decode OPCODE_LO {
50        format IntImmediate {
51            0x0: addi({{ }});
52            0x1: addiu({{ }});
53            0x2: slti({{ }});
54            0x3: sltiu({{ }});
55            0x4: andi({{ }});
56            0x5: ori({{ }});
57            0x6: xori({{ }});
58            0x7: lui({{ }});
59        };
60    };
61
62    0x2: decode OPCODE_LO {
63        format FailUnimpl{
64            0x0: coprocessor_op({{ }});
65            0x1: coprocessor_op({{ }});
66            0x2: coprocessor_op({{ }});
67            0x3: coprocessor_op({{ }});
68        };
69
70        //MIPS obsolete instructions
71        0x4: beql({{ }});
72        0x5: bnel({{ }});
73        0x6: blezl({{ }});
74        0x7: bgtzl({{ }});
75    };
76
77    0x3: decode OPCODE_LO {
78        format FailUnimpl{
79            0x0: reserved({{ }})
80            0x1: reserved({{ }})
81            0x2: reserved({{ }})
82            0x3: reserved({{ }})
83            0x5: reserved({{ }})
84            0x6: reserved({{ }})
85        };
86
87        4: decode SPECIAL2 {
88            0x0:;
89            0x1:;
90            0x2:;
91            0x3:;
92            0x4:;
93            0x5:;
94            0x6:;
95        }
96
97        7: decode SPECIAL3 {
98            0x0:;
99            0x1:;
100            0x2:;
101            0x3:;
102            0x4:;
103            0x5:;
104            0x6:;
105        }
106    };
107
108    0x4: decode OPCODE_LO {
109        format LoadMemory{
110            0x0: lb({{ }});
111            0x1: lh({{ }});
112            0x2: lwl({{ }});
113            0x3: lw({{ }});
114            0x4: lbu({{ }});
115            0x5: lhu({{ }});
116            0x6: lhu({{ }});
117        };
118
119        0x7: FailUnimpl::reserved({{ }});
120    };
121
122    0x5: decode OPCODE_LO {
123        format StoreMemory{
124            0x0: sb({{ }});
125            0x1: sh({{ }});
126            0x2: swl({{ }});
127            0x3: sw({{ }});
128            0x6: swr({{ }});
129        };
130
131        format FailUnimpl{
132            0x4: reserved({{ }});
133            0x5: reserved({{ }});
134            0x2: cache({{ }});
135        };
136
137    };
138
139    0x6: decode OPCODE_LO {
140        format LoadMemory{
141            0x0: ll({{ }});
142            0x1: lwc1({{ }});
143            0x5: ldc1({{ }});
144        };
145
146        format FailUnimpl{
147            0x2: lwc2({{ }});
148            0x3: pref({{ }});
149            0x4: reserved({{ }});
150            0x6: ldc2({{ }});
151            0x7: reserved({{ }});
152        };
153
154    };
155
156    0x7: decode OPCODE_LO {
157        format StoreMemory{
158            0x0: sc({{ }});
159            0x1: swc1({{ }});
160            0x5: sdc1({{ }});
161        };
162
163        format FailUnimpl{
164            0x2: swc2({{ }});
165            0x3: reserved({{ }});
166            0x4: reserved({{ }});
167            0x6: sdc2({{ }});
168            0x7: reserved({{ }});
169        };
170
171    };
172
173
174    //Table 3-1 CPU Arithmetic Instructions ( )
175    format IntegerOperate {
176
177        0x10: decode INTFUNC {	// integer arithmetic operations
178
179           //ADD Add Word
180
181           //ADDI Add Immediate Word
182
183           //ADDIU Add Immediate Unsigned Word
184
185           //ADDU Add Unsigned Word
186
187            0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
188            0x40: addlv({{
189                uint32_t tmp  = Ra.sl + Rb_or_imm.sl;
190                // signed overflow occurs when operands have same sign
191                // and sign of result does not match.
192                if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
193                    fault = Integer_Overflow_Fault;
194                Rc.sl = tmp;
195            }});
196            0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
197            0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
198
199            0x20: addq({{ Rc = Ra + Rb_or_imm; }});
200            0x60: addqv({{
201                uint64_t tmp = Ra + Rb_or_imm;
202                // signed overflow occurs when operands have same sign
203                // and sign of result does not match.
204                if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
205                    fault = Integer_Overflow_Fault;
206                Rc = tmp;
207            }});
208            0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
209            0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
210
211            0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
212            0x49: sublv({{
213                uint32_t tmp  = Ra.sl - Rb_or_imm.sl;
214                // signed overflow detection is same as for add,
215                // except we need to look at the *complemented*
216                // sign bit of the subtrahend (Rb), i.e., if the initial
217                // signs are the *same* then no overflow can occur
218                if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
219                    fault = Integer_Overflow_Fault;
220                Rc.sl = tmp;
221            }});
222            0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
223            0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
224
225            0x29: subq({{ Rc = Ra - Rb_or_imm; }});
226            0x69: subqv({{
227                uint64_t tmp  = Ra - Rb_or_imm;
228                // signed overflow detection is same as for add,
229                // except we need to look at the *complemented*
230                // sign bit of the subtrahend (Rb), i.e., if the initial
231                // signs are the *same* then no overflow can occur
232                if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
233                    fault = Integer_Overflow_Fault;
234                Rc = tmp;
235            }});
236            0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
237            0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
238
239            0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
240            0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
241            0x4d: cmplt({{ Rc = (Ra.sq <  Rb_or_imm.sq); }});
242            0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
243            0x1d: cmpult({{ Rc = (Ra.uq <  Rb_or_imm.uq); }});
244
245            0x0f: cmpbge({{
246                int hi = 7;
247                int lo = 0;
248                uint64_t tmp = 0;
249                for (int i = 0; i < 8; ++i) {
250                    tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
251                    hi += 8;
252                    lo += 8;
253                }
254                Rc = tmp;
255            }});
256        }
257
258        0x11: decode INTFUNC {	// integer logical operations
259
260            0x00: and({{ Rc = Ra & Rb_or_imm; }});
261            0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
262            0x20: bis({{ Rc = Ra | Rb_or_imm; }});
263            0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
264            0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
265            0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
266
267            // conditional moves
268            0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
269            0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
270            0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
271            0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
272            0x44: cmovlt({{ Rc = (Ra.sq <  0) ? Rb_or_imm : Rc; }});
273            0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
274            0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
275            0x66: cmovgt({{ Rc = (Ra.sq >  0) ? Rb_or_imm : Rc; }});
276
277            // For AMASK, RA must be R31.
278            0x61: decode RA {
279                31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
280            }
281
282            // For IMPLVER, RA must be R31 and the B operand
283            // must be the immediate value 1.
284            0x6c: decode RA {
285                31: decode IMM {
286                    1: decode INTIMM {
287                        // return EV5 for FULL_SYSTEM and EV6 otherwise
288                        1: implver({{
289#if FULL_SYSTEM
290                             Rc = 1;
291#else
292                             Rc = 2;
293#endif
294                        }});
295                    }
296                }
297            }
298
299#if FULL_SYSTEM
300            // The mysterious 11.25...
301            0x25: WarnUnimpl::eleven25();
302#endif
303        }
304
305        0x12: decode INTFUNC {
306            0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
307            0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
308            0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
309
310            0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
311            0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
312            0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
313            0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
314
315            0x52: mskwh({{
316                int bv = Rb_or_imm<2:0>;
317                Rc =  bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
318            }});
319            0x62: msklh({{
320                int bv = Rb_or_imm<2:0>;
321                Rc =  bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
322            }});
323            0x72: mskqh({{
324                int bv = Rb_or_imm<2:0>;
325                Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
326            }});
327
328            0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
329            0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
330            0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
331            0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
332
333            0x5a: extwh({{
334                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
335            0x6a: extlh({{
336                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
337            0x7a: extqh({{
338                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
339
340            0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
341            0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
342            0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
343            0x3b: insql({{ Rc = Ra       << (Rb_or_imm<2:0> * 8); }});
344
345            0x57: inswh({{
346                int bv = Rb_or_imm<2:0>;
347                Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
348            }});
349            0x67: inslh({{
350                int bv = Rb_or_imm<2:0>;
351                Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
352            }});
353            0x77: insqh({{
354                int bv = Rb_or_imm<2:0>;
355                Rc = bv ? (Ra.uq       >> (64 - 8 * bv)) : 0;
356            }});
357
358            0x30: zap({{
359                uint64_t zapmask = 0;
360                for (int i = 0; i < 8; ++i) {
361                    if (Rb_or_imm<i:>)
362                        zapmask |= (mask(8) << (i * 8));
363                }
364                Rc = Ra & ~zapmask;
365            }});
366            0x31: zapnot({{
367                uint64_t zapmask = 0;
368                for (int i = 0; i < 8; ++i) {
369                    if (!Rb_or_imm<i:>)
370                        zapmask |= (mask(8) << (i * 8));
371                }
372                Rc = Ra & ~zapmask;
373            }});
374        }
375
376        0x13: decode INTFUNC {	// integer multiplies
377            0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
378            0x20: mulq({{ Rc    = Ra    * Rb_or_imm;    }}, IntMultOp);
379            0x30: umulh({{
380                uint64_t hi, lo;
381                mul128(Ra, Rb_or_imm, hi, lo);
382                Rc = hi;
383            }}, IntMultOp);
384            0x40: mullv({{
385                // 32-bit multiply with trap on overflow
386                int64_t Rax = Ra.sl;	// sign extended version of Ra.sl
387                int64_t Rbx = Rb_or_imm.sl;
388                int64_t tmp = Rax * Rbx;
389                // To avoid overflow, all the upper 32 bits must match
390                // the sign bit of the lower 32.  We code this as
391                // checking the upper 33 bits for all 0s or all 1s.
392                uint64_t sign_bits = tmp<63:31>;
393                if (sign_bits != 0 && sign_bits != mask(33))
394                    fault = Integer_Overflow_Fault;
395                Rc.sl = tmp<31:0>;
396            }}, IntMultOp);
397            0x60: mulqv({{
398                // 64-bit multiply with trap on overflow
399                uint64_t hi, lo;
400                mul128(Ra, Rb_or_imm, hi, lo);
401                // all the upper 64 bits must match the sign bit of
402                // the lower 64
403                if (!((hi == 0 && lo<63:> == 0) ||
404                      (hi == mask(64) && lo<63:> == 1)))
405                    fault = Integer_Overflow_Fault;
406                Rc = lo;
407            }}, IntMultOp);
408        }
409
410        0x1c: decode INTFUNC {
411            0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
412            0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
413            0x32: ctlz({{
414                             uint64_t count = 0;
415                             uint64_t temp = Rb;
416                             if (temp<63:32>) temp >>= 32; else count += 32;
417                             if (temp<31:16>) temp >>= 16; else count += 16;
418                             if (temp<15:8>) temp >>= 8; else count += 8;
419                             if (temp<7:4>) temp >>= 4; else count += 4;
420                             if (temp<3:2>) temp >>= 2; else count += 2;
421                             if (temp<1:1>) temp >>= 1; else count += 1;
422                             if ((temp<0:0>) != 0x1) count += 1;
423                             Rc = count;
424                           }}, IntAluOp);
425
426            0x33: cttz({{
427                             uint64_t count = 0;
428                             uint64_t temp = Rb;
429                             if (!(temp<31:0>)) { temp >>= 32; count += 32; }
430                             if (!(temp<15:0>)) { temp >>= 16; count += 16; }
431                             if (!(temp<7:0>)) { temp >>= 8; count += 8; }
432                             if (!(temp<3:0>)) { temp >>= 4; count += 4; }
433                             if (!(temp<1:0>)) { temp >>= 2; count += 2; }
434                             if (!(temp<0:0> & ULL(0x1))) count += 1;
435                             Rc = count;
436                           }}, IntAluOp);
437
438            format FailUnimpl {
439                0x30: ctpop();
440                0x31: perr();
441                0x34: unpkbw();
442                0x35: unpkbl();
443                0x36: pkwb();
444                0x37: pklb();
445                0x38: minsb8();
446                0x39: minsw4();
447                0x3a: minub8();
448                0x3b: minuw4();
449                0x3c: maxub8();
450                0x3d: maxuw4();
451                0x3e: maxsb8();
452                0x3f: maxsw4();
453            }
454
455            format BasicOperateWithNopCheck {
456                0x70: decode RB {
457                    31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
458                }
459                0x78: decode RB {
460                    31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
461                              FloatCvtOp);
462                }
463            }
464        }
465    }
466
467    //Table 3-2 CPU Branch and Jump Instructions ( )
468    //Table 3-10 Obsolete CPU Branch Instructions ( )
469
470    //Table 3-3 CPU Instruction Control Instructions ( )
471
472    //Table 3-4 CPU Load, Store, and Memory Control Instructions ( )
473
474    //Table 3-5 CPU Logical Instructions ( )
475
476    //Table 3-6 CPU Insert/Extract Instructions ( )
477
478    //Table 3-7 CPU Move Instructions ( )
479
480    //Table 3-9 CPU Trap Instructions ( )
481
482    //Table 3-11 FPU Arithmetic Instructions ( )
483
484    //Table 3-12 FPU Branch Instructions ( )
485    //Table 3-17 Obsolete  FPU Branch Instructions ()
486
487    //Table 3-13 FPU Compare Instructions ( )
488
489    //Table 3-14 FPU Convert Instructions ( )
490
491    //Table 3-15 FPU Load, Store, and Memory Control Instructions ( )
492
493    //Table 3-16 FPU Move Instructions ( )
494
495    //Tables 3-18 thru 3-22 are Co-Processor Instructions ( )
496
497    //Table 3-23 Privileged Instructions ( )
498
499    //Table 3-24 EJTAG Instructions ( )
500
501
502
503
504    format LoadAddress {
505        0x08: lda({{ Ra = Rb + disp; }});
506        0x09: ldah({{ Ra = Rb + (disp << 16); }});
507    }
508
509    format LoadOrNop {
510        0x0a: ldbu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.ub; }});
511        0x0c: ldwu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uw; }});
512        0x0b: ldq_u({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }});
513        0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
514        0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
515        0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
516        0x20: copy_load({{EA = Ra;}},
517                        {{fault = xc->copySrcTranslate(EA);}},
518                        IsMemRef, IsLoad, IsCopy);
519    }
520
521    format LoadOrPrefetch {
522        0x28: ldl({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }});
523        0x29: ldq({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, EVICT_NEXT);
524        // IsFloating flag on lds gets the prefetch to disassemble
525        // using f31 instead of r31... funcitonally it's unnecessary
526        0x22: lds({{ EA = Rb + disp; }}, {{ Fa.uq = s_to_t(Mem.ul); }},
527                  PF_EXCLUSIVE, IsFloating);
528    }
529
530    format Store {
531        0x0e: stb({{ EA = Rb + disp; }}, {{ Mem.ub = Ra<7:0>; }});
532        0x0d: stw({{ EA = Rb + disp; }}, {{ Mem.uw = Ra<15:0>; }});
533        0x2c: stl({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }});
534        0x2d: stq({{ EA = Rb + disp; }}, {{ Mem.uq = Ra.uq; }});
535        0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
536        0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
537        0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
538        0x24: copy_store({{EA = Rb;}},
539                         {{fault = xc->copy(EA);}},
540                         IsMemRef, IsStore, IsCopy);
541    }
542
543    format StoreCond {
544        0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
545                    {{
546                        uint64_t tmp = Mem_write_result;
547                        // see stq_c
548                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
549                    }}, LOCKED);
550        0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
551                    {{
552                        uint64_t tmp = Mem_write_result;
553                        // If the write operation returns 0 or 1, then
554                        // this was a conventional store conditional,
555                        // and the value indicates the success/failure
556                        // of the operation.  If another value is
557                        // returned, then this was a Turbolaser
558                        // mailbox access, and we don't update the
559                        // result register at all.
560                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
561                    }}, LOCKED);
562    }
563
564
565
566    // Conditional branches.
567    format CondBranch {
568        0x39: beq({{ cond = (Ra == 0); }});
569        0x3d: bne({{ cond = (Ra != 0); }});
570        0x3e: bge({{ cond = (Ra.sq >= 0); }});
571        0x3f: bgt({{ cond = (Ra.sq >  0); }});
572        0x3b: ble({{ cond = (Ra.sq <= 0); }});
573        0x3a: blt({{ cond = (Ra.sq < 0); }});
574        0x38: blbc({{ cond = ((Ra & 1) == 0); }});
575        0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
576
577        0x31: fbeq({{ cond = (Fa == 0); }});
578        0x35: fbne({{ cond = (Fa != 0); }});
579        0x36: fbge({{ cond = (Fa >= 0); }});
580        0x37: fbgt({{ cond = (Fa >  0); }});
581        0x33: fble({{ cond = (Fa <= 0); }});
582        0x32: fblt({{ cond = (Fa < 0); }});
583    }
584
585    // unconditional branches
586    format UncondBranch {
587        0x30: br();
588        0x34: bsr(IsCall);
589    }
590
591    // indirect branches
592    0x1a: decode JMPFUNC {
593        format Jump {
594            0: jmp();
595            1: jsr(IsCall);
596            2: ret(IsReturn);
597            3: jsr_coroutine(IsCall, IsReturn);
598        }
599    }
600
601    // Square root and integer-to-FP moves
602    0x14: decode FP_SHORTFUNC {
603        // Integer to FP register moves must have RB == 31
604        0x4: decode RB {
605            31: decode FP_FULLFUNC {
606                format BasicOperateWithNopCheck {
607                    0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
608                    0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
609                    0x014: FailUnimpl::itoff();	// VAX-format conversion
610                }
611            }
612        }
613
614        // Square root instructions must have FA == 31
615        0xb: decode FA {
616            31: decode FP_TYPEFUNC {
617                format FloatingPointOperate {
618#if SS_COMPATIBLE_FP
619                    0x0b: sqrts({{
620                        if (Fb < 0.0)
621                            fault = Arithmetic_Fault;
622                        Fc = sqrt(Fb);
623                    }}, FloatSqrtOp);
624#else
625                    0x0b: sqrts({{
626                        if (Fb.sf < 0.0)
627                            fault = Arithmetic_Fault;
628                        Fc.sf = sqrt(Fb.sf);
629                    }}, FloatSqrtOp);
630#endif
631                    0x2b: sqrtt({{
632                        if (Fb < 0.0)
633                            fault = Arithmetic_Fault;
634                        Fc = sqrt(Fb);
635                    }}, FloatSqrtOp);
636                }
637            }
638        }
639
640        // VAX-format sqrtf and sqrtg are not implemented
641        0xa: FailUnimpl::sqrtfg();
642    }
643
644    // IEEE floating point
645    0x16: decode FP_SHORTFUNC_TOP2 {
646        // The top two bits of the short function code break this
647        // space into four groups: binary ops, compares, reserved, and
648        // conversions.  See Table 4-12 of AHB.  There are different
649        // special cases in these different groups, so we decode on
650        // these top two bits first just to select a decode strategy.
651        // Most of these instructions may have various trapping and
652        // rounding mode flags set; these are decoded in the
653        // FloatingPointDecode template used by the
654        // FloatingPointOperate format.
655
656        // add/sub/mul/div: just decode on the short function code
657        // and source type.  All valid trapping and rounding modes apply.
658        0: decode FP_TRAPMODE {
659            // check for valid trapping modes here
660            0,1,5,7: decode FP_TYPEFUNC {
661                   format FloatingPointOperate {
662#if SS_COMPATIBLE_FP
663                       0x00: adds({{ Fc = Fa + Fb; }});
664                       0x01: subs({{ Fc = Fa - Fb; }});
665                       0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
666                       0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
667#else
668                       0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
669                       0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
670                       0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
671                       0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
672#endif
673
674                       0x20: addt({{ Fc = Fa + Fb; }});
675                       0x21: subt({{ Fc = Fa - Fb; }});
676                       0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
677                       0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
678                   }
679             }
680        }
681
682        // Floating-point compare instructions must have the default
683        // rounding mode, and may use the default trapping mode or
684        // /SU.  Both trapping modes are treated the same by M5; the
685        // only difference on the real hardware (as far a I can tell)
686        // is that without /SU you'd get an imprecise trap if you
687        // tried to compare a NaN with something else (instead of an
688        // "unordered" result).
689        1: decode FP_FULLFUNC {
690            format BasicOperateWithNopCheck {
691                0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
692                                     FloatCmpOp);
693                0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
694                                     FloatCmpOp);
695                0x0a6, 0x5a6: cmptlt({{ Fc = (Fa <  Fb) ? 2.0 : 0.0; }},
696                                     FloatCmpOp);
697                0x0a4, 0x5a4: cmptun({{ // unordered
698                    Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
699                }}, FloatCmpOp);
700            }
701        }
702
703        // The FP-to-integer and integer-to-FP conversion insts
704        // require that FA be 31.
705        3: decode FA {
706            31: decode FP_TYPEFUNC {
707                format FloatingPointOperate {
708                    0x2f: decode FP_ROUNDMODE {
709                        format FPFixedRounding {
710                            // "chopped" i.e. round toward zero
711                            0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
712                                     Chopped);
713                            // round to minus infinity
714                            1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
715                                     MinusInfinity);
716                        }
717                      default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
718                    }
719
720                    // The cvtts opcode is overloaded to be cvtst if the trap
721                    // mode is 2 or 6 (which are not valid otherwise)
722                    0x2c: decode FP_FULLFUNC {
723                        format BasicOperateWithNopCheck {
724                            // trap on denorm version "cvtst/s" is
725                            // simulated same as cvtst
726                            0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
727                        }
728                      default: cvtts({{ Fc.sf = Fb; }});
729                    }
730
731                    // The trapping mode for integer-to-FP conversions
732                    // must be /SUI or nothing; /U and /SU are not
733                    // allowed.  The full set of rounding modes are
734                    // supported though.
735                    0x3c: decode FP_TRAPMODE {
736                        0,7: cvtqs({{ Fc.sf = Fb.sq; }});
737                    }
738                    0x3e: decode FP_TRAPMODE {
739                        0,7: cvtqt({{ Fc    = Fb.sq; }});
740                    }
741                }
742            }
743        }
744    }
745
746    // misc FP operate
747    0x17: decode FP_FULLFUNC {
748        format BasicOperateWithNopCheck {
749            0x010: cvtlq({{
750                Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
751            }});
752            0x030: cvtql({{
753                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
754            }});
755
756            // We treat the precise & imprecise trapping versions of
757            // cvtql identically.
758            0x130, 0x530: cvtqlv({{
759                // To avoid overflow, all the upper 32 bits must match
760                // the sign bit of the lower 32.  We code this as
761                // checking the upper 33 bits for all 0s or all 1s.
762                uint64_t sign_bits = Fb.uq<63:31>;
763                if (sign_bits != 0 && sign_bits != mask(33))
764                    fault = Integer_Overflow_Fault;
765                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
766            }});
767
768            0x020: cpys({{  // copy sign
769                Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
770            }});
771            0x021: cpysn({{ // copy sign negated
772                Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
773            }});
774            0x022: cpyse({{ // copy sign and exponent
775                Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
776            }});
777
778            0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
779            0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
780            0x02c: fcmovlt({{ Fc = (Fa <  0) ? Fb : Fc; }});
781            0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
782            0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
783            0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
784
785            0x024: mt_fpcr({{ FPCR = Fa.uq; }});
786            0x025: mf_fpcr({{ Fa.uq = FPCR; }});
787        }
788    }
789
790    // miscellaneous mem-format ops
791    0x18: decode MEMFUNC {
792        format WarnUnimpl {
793            0x8000: fetch();
794            0xa000: fetch_m();
795            0xe800: ecb();
796        }
797
798        format MiscPrefetch {
799            0xf800: wh64({{ EA = Rb & ~ULL(63); }},
800                         {{ xc->writeHint(EA, 64, memAccessFlags); }},
801                         IsMemRef, IsDataPrefetch, IsStore, MemWriteOp,
802                         NO_FAULT);
803        }
804
805        format BasicOperate {
806            0xc000: rpcc({{
807#if FULL_SYSTEM
808        /* Rb is a fake dependency so here is a fun way to get
809         * the parser to understand that.
810         */
811                Ra = xc->readIpr(MipsISA::IPR_CC, fault) + (Rb & 0);
812
813#else
814                Ra = curTick;
815#endif
816            }});
817
818            // All of the barrier instructions below do nothing in
819            // their execute() methods (hence the empty code blocks).
820            // All of their functionality is hard-coded in the
821            // pipeline based on the flags IsSerializing,
822            // IsMemBarrier, and IsWriteBarrier.  In the current
823            // detailed CPU model, the execute() function only gets
824            // called at fetch, so there's no way to generate pipeline
825            // behavior at any other stage.  Once we go to an
826            // exec-in-exec CPU model we should be able to get rid of
827            // these flags and implement this behavior via the
828            // execute() methods.
829
830            // trapb is just a barrier on integer traps, where excb is
831            // a barrier on integer and FP traps.  "EXCB is thus a
832            // superset of TRAPB." (Mips ARM, Sec 4.11.4) We treat
833            // them the same though.
834            0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
835            0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
836            0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
837            0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
838        }
839
840#if FULL_SYSTEM
841        format BasicOperate {
842            0xe000: rc({{
843                Ra = xc->readIntrFlag();
844                xc->setIntrFlag(0);
845            }}, IsNonSpeculative);
846            0xf000: rs({{
847                Ra = xc->readIntrFlag();
848                xc->setIntrFlag(1);
849            }}, IsNonSpeculative);
850        }
851#else
852        format FailUnimpl {
853            0xe000: rc();
854            0xf000: rs();
855        }
856#endif
857    }
858
859#if FULL_SYSTEM
860    0x00: CallPal::call_pal({{
861        if (!palValid ||
862            (palPriv
863             && xc->readIpr(MipsISA::IPR_ICM, fault) != MipsISA::mode_kernel)) {
864            // invalid pal function code, or attempt to do privileged
865            // PAL call in non-kernel mode
866            fault = Unimplemented_Opcode_Fault;
867        }
868        else {
869            // check to see if simulator wants to do something special
870            // on this PAL call (including maybe suppress it)
871            bool dopal = xc->simPalCheck(palFunc);
872
873            if (dopal) {
874                MipsISA::swap_palshadow(&xc->xcBase()->regs, true);
875                xc->setIpr(MipsISA::IPR_EXC_ADDR, NPC);
876                NPC = xc->readIpr(MipsISA::IPR_PAL_BASE, fault) + palOffset;
877            }
878        }
879    }}, IsNonSpeculative);
880#else
881    0x00: decode PALFUNC {
882        format EmulatedCallPal {
883            0x00: halt ({{
884                SimExit(curTick, "halt instruction encountered");
885            }}, IsNonSpeculative);
886            0x83: callsys({{
887                xc->syscall();
888            }}, IsNonSpeculative, IsSerializeAfter);
889            // Read uniq reg into ABI return value register (r0)
890            0x9e: rduniq({{ R0 = Runiq; }});
891            // Write uniq reg with value from ABI arg register (r16)
892            0x9f: wruniq({{ Runiq = R16; }});
893        }
894    }
895#endif
896
897#if FULL_SYSTEM
898    format HwLoadStore {
899        0x1b: decode HW_LDST_QUAD {
900            0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
901            1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
902        }
903
904        0x1f: decode HW_LDST_COND {
905            0: decode HW_LDST_QUAD {
906                0: hw_st({{ EA = (Rb + disp) & ~3; }},
907                         {{ Mem.ul = Ra<31:0>; }}, L);
908                1: hw_st({{ EA = (Rb + disp) & ~7; }},
909                         {{ Mem.uq = Ra.uq; }}, Q);
910            }
911
912            1: FailUnimpl::hw_st_cond();
913        }
914    }
915
916    format HwMoveIPR {
917        0x19: hw_mfpr({{
918            // this instruction is only valid in PAL mode
919            if (!xc->inPalMode()) {
920                fault = Unimplemented_Opcode_Fault;
921            }
922            else {
923                Ra = xc->readIpr(ipr_index, fault);
924            }
925        }});
926        0x1d: hw_mtpr({{
927            // this instruction is only valid in PAL mode
928            if (!xc->inPalMode()) {
929                fault = Unimplemented_Opcode_Fault;
930            }
931            else {
932                xc->setIpr(ipr_index, Ra);
933                if (traceData) { traceData->setData(Ra); }
934            }
935        }});
936    }
937
938    format BasicOperate {
939        0x1e: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
940
941        // M5 special opcodes use the reserved 0x01 opcode space
942        0x01: decode M5FUNC {
943            0x00: arm({{
944                MipsPseudo::arm(xc->xcBase());
945            }}, IsNonSpeculative);
946            0x01: quiesce({{
947                MipsPseudo::quiesce(xc->xcBase());
948            }}, IsNonSpeculative);
949            0x10: ivlb({{
950                MipsPseudo::ivlb(xc->xcBase());
951            }}, No_OpClass, IsNonSpeculative);
952            0x11: ivle({{
953                MipsPseudo::ivle(xc->xcBase());
954            }}, No_OpClass, IsNonSpeculative);
955            0x20: m5exit_old({{
956                MipsPseudo::m5exit_old(xc->xcBase());
957            }}, No_OpClass, IsNonSpeculative);
958            0x21: m5exit({{
959                MipsPseudo::m5exit(xc->xcBase());
960            }}, No_OpClass, IsNonSpeculative);
961            0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
962            0x40: resetstats({{
963                MipsPseudo::resetstats(xc->xcBase());
964            }}, IsNonSpeculative);
965            0x41: dumpstats({{
966                MipsPseudo::dumpstats(xc->xcBase());
967            }}, IsNonSpeculative);
968            0x42: dumpresetstats({{
969                MipsPseudo::dumpresetstats(xc->xcBase());
970            }}, IsNonSpeculative);
971            0x43: m5checkpoint({{
972                MipsPseudo::m5checkpoint(xc->xcBase());
973            }}, IsNonSpeculative);
974            0x50: m5readfile({{
975                MipsPseudo::readfile(xc->xcBase());
976            }}, IsNonSpeculative);
977            0x51: m5break({{
978                MipsPseudo::debugbreak(xc->xcBase());
979            }}, IsNonSpeculative);
980            0x52: m5switchcpu({{
981                MipsPseudo::switchcpu(xc->xcBase());
982            }}, IsNonSpeculative);
983            0x53: m5addsymbol({{
984                MipsPseudo::addsymbol(xc->xcBase());
985            }}, IsNonSpeculative);
986
987        }
988    }
989#endif
990}
991
992