decoder.isa revision 2022
11689SN/A//////////////////////////////////////////////////////////////////// 27598Sminkyu.jeong@arm.com// 37598Sminkyu.jeong@arm.com// The actual decoder specification 47598Sminkyu.jeong@arm.com// 57598Sminkyu.jeong@arm.com 67598Sminkyu.jeong@arm.comdecode OP default Trap::unknown({{illegal_instruction}}) { 77598Sminkyu.jeong@arm.com 87598Sminkyu.jeong@arm.com 0x0: decode OP2 { 97598Sminkyu.jeong@arm.com 0x0: Trap::illtrap({{illegal_instruction}}); //ILLTRAP 107598Sminkyu.jeong@arm.com 0x1: Branch::bpcc({{ 117598Sminkyu.jeong@arm.com switch((CC12 << 1) | CC02) 127598Sminkyu.jeong@arm.com { 137598Sminkyu.jeong@arm.com case 1: case 3: 142326SN/A throw illegal_instruction; 151689SN/A case 0: 161689SN/A if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2)) 171689SN/A ;//branchHere 181689SN/A break; 191689SN/A case 2: 201689SN/A if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND2)) 211689SN/A ;//branchHere 221689SN/A break; 231689SN/A } 241689SN/A }});//BPcc 251689SN/A 0x2: Branch::bicc({{ 261689SN/A if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2)) 271689SN/A ;//branchHere 281689SN/A }});//Bicc 291689SN/A 0x3: Branch::bpr({{ 301689SN/A switch(RCOND) 311689SN/A { 321689SN/A case 0: case 4: 331689SN/A throw illegal_instruction; 341689SN/A case 1: 351689SN/A if(Rs1 == 0) ;//branchHere 361689SN/A break; 371689SN/A case 2: 381689SN/A if(Rs1 <= 0) ;//branchHere 392665Ssaidi@eecs.umich.edu break; 402665Ssaidi@eecs.umich.edu case 3: 411689SN/A if(Rs1 < 0) ;//branchHere 421689SN/A break; 431060SN/A case 5: 441060SN/A if(Rs1 != 0) ;//branchHere 451689SN/A break; 461060SN/A case 6: 471060SN/A if(Rs1 > 0) ;//branchHere 481060SN/A break; 491060SN/A case 7: 506658Snate@binkert.org if(Rs1 >= 0) ;//branchHere 512292SN/A break; 521717SN/A } 535529Snate@binkert.org }}); //BPr 541060SN/A 0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}}); //SETHI (or NOP if rd == 0 and imm == 0) 556221Snate@binkert.org 0x5: Trap::fbpfcc({{throw fp_disabled;}}); //FBPfcc 566221Snate@binkert.org 0x6: Trap::fbfcc({{throw fp_disabled;}}); //FBfcc 571681SN/A } 585529Snate@binkert.org 0x1: Branch::call({{ 592873Sktlim@umich.edu //branch here 604329Sktlim@umich.edu Rd = xc->pc; 614329Sktlim@umich.edu }}); 624329Sktlim@umich.edu 0x2: decode OP3 { 632292SN/A format IntegerOp { 642292SN/A 0x00: add({{ 652292SN/A INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 662292SN/A Rd = Rs1.sdw + val2; 672820Sktlim@umich.edu }});//ADD 682292SN/A 0x01: and({{ 692820Sktlim@umich.edu UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); 702820Sktlim@umich.edu Rd = Rs1.udw & val2; 715529Snate@binkert.org }});//AND 722307SN/A 0x02: or({{ 731060SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); 742292SN/A Rd = Rs1.udw | val2; 752292SN/A }});//OR 762292SN/A 0x03: xor({{ 771060SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); 781060SN/A Rd = Rs1.udw ^ val2; 791060SN/A }});//XOR 801060SN/A 0x04: sub({{ 811060SN/A INT64 val2 = ~((UINT64)(I ? SIMM13.sdw : Rs2.udw))+1; 821060SN/A Rd = Rs1.sdw + val2; 831681SN/A }});//SUB 846221Snate@binkert.org 0x05: andn({{ 856221Snate@binkert.org UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); 866221Snate@binkert.org Rd = Rs1.udw & ~val2; 876221Snate@binkert.org }});//ANDN 882292SN/A 0x06: orn({{ 892292SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); 902820Sktlim@umich.edu Rd = Rs1.udw | ~val2; 912820Sktlim@umich.edu }});//ORN 922292SN/A 0x07: xnor({{ 932292SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); 942820Sktlim@umich.edu Rd = ~(Rs1.udw ^ val2); 952820Sktlim@umich.edu }});//XNOR 962292SN/A 0x08: addc({{ 972292SN/A INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 982292SN/A INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; 992292SN/A Rd = Rs1.sdw + val2 + carryin; 1002292SN/A }});//ADDC 1012292SN/A 0x09: mulx({{ 1022292SN/A INT64 val2 = (I ? SIMM13.sdw : Rs2); 1032292SN/A Rd = Rs1 * val2; 1041060SN/A }});//MULX 1051060SN/A 0x0A: umul({{ 1061681SN/A UINT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw); 1071062SN/A Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; 1082292SN/A xc->regs.MiscRegs.yFields.value = resTemp<63:32>; 1091062SN/A }});//UMUL 1102301SN/A 0x0B: smul({{ 1112301SN/A INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw); 1121062SN/A rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>; 1132727Sktlim@umich.edu xc->regs.MiscRegs.yFields.value = resTemp<63:32>; 1141062SN/A }});//SMUL 1151062SN/A 0x0C: subc({{ 1161062SN/A INT64 val2 = ~((INT64)(I ? SIMM13.sdw : Rs2.sdw))+1; 1171062SN/A INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; 1181062SN/A Rd.sdw = Rs1.sdw + val2 + carryin; 1191062SN/A }});//SUBC 1201062SN/A 0x0D: udivx({{ 1211062SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); 1221062SN/A if(val2 == 0) throw division_by_zero; 1231062SN/A Rd.udw = Rs1.udw / val2; 1241062SN/A }});//UDIVX 1251062SN/A 0x0E: udiv({{ 1261062SN/A UINT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>); 1271062SN/A if(val2 == 0) throw division_by_zero; 1281062SN/A resTemp = (UINT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2; 1291062SN/A INT32 overflow = (resTemp<63:32> != 0); 1301062SN/A if(overflow) rd.udw = resTemp = 0xFFFFFFFF; 1311062SN/A else rd.udw = resTemp; 1321062SN/A }}); //UDIV 1331062SN/A 0x0F: sdiv({{ 1341062SN/A INT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>); 1351062SN/A if(val2 == 0) throw division_by_zero; 1361062SN/A Rd.sdw = resTemp = (INT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2; 1371062SN/A INT32 overflow = (resTemp<63:31> != 0); 1381062SN/A INT32 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); 1391062SN/A if(overflow) rd.udw = resTemp = 0x7FFFFFFF; 1401062SN/A else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000; 1411062SN/A else rd.udw = resTemp; 1421062SN/A }});//SDIV 1431062SN/A } 1441062SN/A format IntegerOpCc { 1451062SN/A 0x10: addcc({{ 1461062SN/A INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); 1471062SN/A Rd = resTemp = Rs1 + val2;}}, 1481062SN/A {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 1491062SN/A {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 1501062SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 1511062SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 1521062SN/A );//ADDcc 1531062SN/A 0x11: andcc({{ 1541062SN/A INT64 val2 = (I ? SIMM13.sdw : Rs2); 1552292SN/A Rd = Rs1 & val2;}} 1562292SN/A ,{{0}},{{0}},{{0}},{{0}});//ANDcc 1572292SN/A 0x12: orcc({{ 1582292SN/A INT64 val2 = (I ? SIMM13.sdw : Rs2); 1591062SN/A Rd = Rs1 | val2;}} 1601062SN/A ,{{0}},{{0}},{{0}},{{0}});//ORcc 1611062SN/A 0x13: xorcc({{ 1621062SN/A INT64 val2 = (I ? SIMM13.sdw : Rs2); 1631062SN/A Rd = Rs1 ^ val2;}} 1641062SN/A ,{{0}},{{0}},{{0}},{{0}});//XORcc 1651062SN/A 0x14: subcc({{ 1662292SN/A INT64 resTemp, val2 = (INT64)(I ? SIMM13.sdw : Rs2); 1672292SN/A Rd = resTemp = Rs1 - val2;}}, 1682292SN/A {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}}, 1692292SN/A {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 1702292SN/A {{((Rs1 >> 1) + (~val2) >> 1) + ((Rs1 | ~val2) & 0x1))<63:>}}, 1712292SN/A {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 1722292SN/A );//SUBcc 1732292SN/A 0x15: andncc({{ 1742292SN/A INT64 val2 = (I ? SIMM13.sdw : Rs2); 1752292SN/A Rd = Rs1 & ~val2;}} 1762301SN/A ,{{0}},{{0}},{{0}},{{0}});//ANDNcc 1772727Sktlim@umich.edu 0x16: orncc({{ 1782353SN/A INT64 val2 = (I ? SIMM13.sdw : Rs2); 1792727Sktlim@umich.edu Rd = Rs1 | ~val2;}} 1802727Sktlim@umich.edu ,{{0}},{{0}},{{0}},{{0}});//ORNcc 1812727Sktlim@umich.edu 0x17: xnorcc({{ 1826221Snate@binkert.org INT64 val2 = (I ? SIMM13.sdw : Rs2); 1832353SN/A Rd = ~(Rs1 ^ val2);}} 1842727Sktlim@umich.edu ,{{0}},{{0}},{{0}},{{0}});//XNORcc 1852727Sktlim@umich.edu 0x18: addccc({{ 1862727Sktlim@umich.edu INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); 1872727Sktlim@umich.edu INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; 1882353SN/A Rd = resTemp = Rs1 + val2 + carryin;}}, 1892727Sktlim@umich.edu {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31 + carryin)}}, 1902727Sktlim@umich.edu {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 1912727Sktlim@umich.edu {{((Rs1 >> 1) + (val2 >> 1) + ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}}, 1926221Snate@binkert.org {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 1932301SN/A );//ADDCcc 1942301SN/A 0x1A: umulcc({{ 1952727Sktlim@umich.edu UINT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); 1962301SN/A Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; 1972727Sktlim@umich.edu xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}} 1986221Snate@binkert.org ,{{0}},{{0}},{{0}},{{0}});//UMULcc 1992301SN/A 0x1B: smulcc({{ 2002301SN/A INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); 2012727Sktlim@umich.edu Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>; 2022301SN/A xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}} 2032727Sktlim@umich.edu ,{{0}},{{0}},{{0}},{{0}});//SMULcc 2046221Snate@binkert.org 0x1C: subccc({{ 2052301SN/A INT64 resTemp, val2 = (INT64)(I ? SIMM13.sdw : Rs2); 2062301SN/A INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; 2072727Sktlim@umich.edu Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, 2082301SN/A {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}}, 2092727Sktlim@umich.edu {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 2106221Snate@binkert.org {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}}, 2112301SN/A {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 2122301SN/A );//SUBCcc 2132727Sktlim@umich.edu 0x1D: udivxcc({{ 2142301SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); 2152301SN/A if(val2 == 0) throw division_by_zero; 2162301SN/A Rd.udw = Rs1.udw / val2;}} 2172301SN/A ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc 2182727Sktlim@umich.edu 0x1E: udivcc({{ 2192727Sktlim@umich.edu UINT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>); 2202727Sktlim@umich.edu if(val2 == 0) throw division_by_zero; 2212727Sktlim@umich.edu resTemp = (UINT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2; 2222727Sktlim@umich.edu INT32 overflow = (resTemp<63:32> != 0); 2232727Sktlim@umich.edu if(overflow) rd.udw = resTemp = 0xFFFFFFFF; 2242727Sktlim@umich.edu else rd.udw = resTemp;}}, 2252727Sktlim@umich.edu {{0}}, 2262727Sktlim@umich.edu {{overflow}}, 2272301SN/A {{0}}, 2282301SN/A {{0}} 2296221Snate@binkert.org );//UDIVcc 2302301SN/A 0x1F: sdivcc({{ 2312301SN/A INT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>); 2322727Sktlim@umich.edu if(val2 == 0) throw division_by_zero; 2332301SN/A Rd.sdw = resTemp = (INT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2; 2342326SN/A INT32 overflow = (resTemp<63:31> != 0); 2356221Snate@binkert.org INT32 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); 2362301SN/A if(overflow) rd.udw = resTemp = 0x7FFFFFFF; 2372301SN/A else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000; 2382727Sktlim@umich.edu else rd.udw = resTemp;}}, 2392301SN/A {{0}}, 2402326SN/A {{overflow || underflow}}, 2416221Snate@binkert.org {{0}}, 2422301SN/A {{0}} 2432301SN/A );//SDIVcc 2442727Sktlim@umich.edu 0x20: taddcc({{ 2452301SN/A INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); 2462326SN/A Rd = resTemp = Rs1 + val2; 2476221Snate@binkert.org INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 2482301SN/A {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 2492301SN/A {{overflow}}, 2502727Sktlim@umich.edu {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2512301SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2522326SN/A );//TADDcc 2536221Snate@binkert.org 0x21: tsubcc({{ 2542301SN/A INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); 2552301SN/A Rd = resTemp = Rs1 + val2; 2562727Sktlim@umich.edu INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 2572301SN/A {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 2582326SN/A {{overflow}}, 2592301SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2602301SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2612727Sktlim@umich.edu );//TSUBcc 2622301SN/A 0x22: taddcctv({{ 2632326SN/A INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); 2642301SN/A Rd = resTemp = Rs1 + val2; 2652326SN/A INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 2662301SN/A if(overflow) throw tag_overflow;}}, 2672301SN/A {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 2682727Sktlim@umich.edu {{overflow}}, 2692301SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2702326SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2712301SN/A );//TADDccTV 2722326SN/A 0x23: tsubcctv({{ 2732301SN/A INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); 2742301SN/A Rd = resTemp = Rs1 + val2; 2752727Sktlim@umich.edu INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 2762326SN/A if(overflow) throw tag_overflow;}}, 2771062SN/A {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 2781062SN/A {{overflow}}, 2791681SN/A {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 2801060SN/A {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 2812292SN/A );//TSUBccTV 2821060SN/A 0x24: mulscc({{ 2836221Snate@binkert.org INT64 resTemp, multiplicand = (I ? SIMM13.sdw : Rs2); 2842292SN/A INT32 multiplier = Rs1<31:0>; 2852292SN/A INT32 savedLSB = Rs1<0:>; 2862292SN/A multiplier = multipler<31:1> | 2872292SN/A ((xc->regs.MiscRegs.ccrFields.iccFields.n 2882292SN/A ^ xc->regs.MiscRegs.ccrFields.iccFields.v) << 32); 2892292SN/A if(!xc->regs.MiscRegs.yFields.value<0:>) 2902292SN/A multiplicand = 0; 2912292SN/A Rd = resTemp = multiplicand + multiplier; 2922292SN/A xc->regs.MiscRegs.yFields.value = xc->regs.MiscRegs.yFields.value<31:1> | (savedLSB << 31);}}, 2932733Sktlim@umich.edu {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 2941060SN/A {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 2951060SN/A {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 2961681SN/A {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 2971060SN/A );//MULScc 2982292SN/A } 2991060SN/A format IntegerOp 3001060SN/A { 3011060SN/A 0x25: decode X { 3021060SN/A 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL 3031060SN/A 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX 3041060SN/A } 3051060SN/A 0x26: decode X { 3061060SN/A 0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL 3071060SN/A 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX 3082292SN/A } 3092292SN/A 0x27: decode X { 3101060SN/A 0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA 3111060SN/A 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX 3121060SN/A } 3131060SN/A 0x28: decode RS1 { 3141681SN/A 0x0: rdy({{Rd = xc->regs.MiscRegs.yFields.value;}}); //RDY 3151060SN/A 0x2: rdccr({{Rd = xc->regs.MiscRegs.ccr;}}); //RDCCR 3162292SN/A 0x3: rdasi({{Rd = xc->regs.MiscRegs.asi;}}); //RDASI 3171060SN/A 0x4: rdtick({{ 3181060SN/A if(xc->regs.MiscRegs.pstateFields.priv == 0 && 3191060SN/A xc->regs.MiscRegs.tickFields.npt == 1) 3201060SN/A throw privileged_action; 3211060SN/A Rd = xc->regs.MiscRegs.tick; 3221060SN/A }});//RDTICK 3231060SN/A 0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC 3241681SN/A 0x6: rdfprs({{Rd = xc->regs.MiscRegs.fprs;}}); //RDFPRS 3251060SN/A 0xF: decode I { 3262292SN/A 0x0: Noop::membar({{//Membar isn't needed yet}}); //MEMBAR 3271060SN/A 0x1: Noop::stbar({{//Stbar isn/'t needed yet}}); //STBAR 3281060SN/A } 3291060SN/A } 3301060SN/A 3311060SN/A 0x2A: decode RS1 { 3321060SN/A 0x0: rdprtpc({{checkPriv Rd = xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl];}}); 3331060SN/A 0x1: rdprtnpc({{checkPriv Rd = xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl];}}); 3341681SN/A 0x2: rdprtstate({{checkPriv Rd = xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl];}}); 3351060SN/A 0x3: rdprtt({{checkPriv Rd = xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl];}}); 3366221Snate@binkert.org 0x4: rdprtick({{checkPriv Rd = xc->regs.MiscRegs.tick;}}); 3371060SN/A 0x5: rdprtba({{checkPriv Rd = xc->regs.MiscRegs.tba;}}); 3382292SN/A 0x6: rdprpstate({{checkPriv Rd = xc->regs.MiscRegs.pstate;}}); 3392292SN/A 0x7: rdprtl({{checkPriv Rd = xc->regs.MiscRegs.tl;}}); 3402292SN/A 0x8: rdprpil({{checkPriv Rd = xc->regs.MiscRegs.pil;}}); 3412292SN/A 0x9: rdprcwp({{checkPriv Rd = xc->regs.MiscRegs.cwp;}}); 3421060SN/A 0xA: rdprcansave({{checkPriv Rd = xc->regs.MiscRegs.cansave;}}); 3431060SN/A 0xB: rdprcanrestore({{checkPriv Rd = xc->regs.MiscRegs.canrestore;}}); 3441681SN/A 0xC: rdprcleanwin({{checkPriv Rd = xc->regs.MiscRegs.cleanwin;}}); 3451060SN/A 0xD: rdprotherwin({{checkPriv Rd = xc->regs.MiscRegs.otherwin;}}); 3462292SN/A 0xE: rdprwstate({{checkPriv Rd = xc->regs.MiscRegs.wstate;}}); 3471060SN/A 0xF: rdprfq({{throw illegal_instruction;}}); //The floating point queue isn't implemented right now. 3482292SN/A } 3491060SN/A 0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW 3501060SN/A 0x2C: movcc({{ 3512307SN/A ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0); 3522863Sktlim@umich.edu switch(ccBank) 3532843Sktlim@umich.edu { 3542307SN/A case 0: case 1: case 2: case 3: 3552843Sktlim@umich.edu throw fp_disabled; 3562843Sktlim@umich.edu break; 3572863Sktlim@umich.edu case 5: case 7: 3581681SN/A throw illegal_instruction; 3591681SN/A break; 3602316SN/A case 4: 3611681SN/A if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND4)) 3622843Sktlim@umich.edu Rd = (I ? SIMM11.sdw : RS2); 3632843Sktlim@umich.edu break; 3642843Sktlim@umich.edu case 6: 3652843Sktlim@umich.edu if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND4)) 3662843Sktlim@umich.edu Rd = (I ? SIMM11.sdw : RS2); 3672843Sktlim@umich.edu break; 3682843Sktlim@umich.edu } 3691681SN/A }});//MOVcc 3702348SN/A 0x2D: sdivx({{ 3712307SN/A INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 3722367SN/A if(val2 == 0) throw division_by_zero; 3732367SN/A Rd.sdw = Rs1.sdw / val2; 3741681SN/A }});//SDIVX 3752307SN/A 0x2E: decode RS1 { 3762307SN/A 0x0: IntegerOp::popc({{ 3772307SN/A INT64 count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw); 3782307SN/A UINT8 oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4} 3796221Snate@binkert.org for(unsigned int x = 0; x < 16; x++) 3806221Snate@binkert.org { 3816221Snate@binkert.org count += oneBits[val2 & 0xF]; 3826221Snate@binkert.org val2 >> 4; 3836221Snate@binkert.org } 3842307SN/A }});//POPC 3851681SN/A } 3861681SN/A 0x2F: movr({{ 3872307SN/A UINT64 val2 = (I ? SIMM10.sdw : Rs2.sdw); 3881681SN/A switch(RCOND) 3892307SN/A { 3901060SN/A case 0: case 4: 3912348SN/A throw illegal_instruction; 3922307SN/A break; 3932307SN/A case 1: 3942307SN/A if(Rs1 == 0) Rd = val2; 3952307SN/A break; 3961060SN/A case 2: 3972307SN/A if(Rs1 <= 0) Rd = val2; 3982307SN/A break; 3992307SN/A case 3: 4001060SN/A if(Rs1 = 0) Rd = val2; 4012307SN/A break; 4022307SN/A case 5: 4031060SN/A if(Rs1 != 0) Rd = val2; 4046221Snate@binkert.org break; 4056221Snate@binkert.org case 6: 4066221Snate@binkert.org if(Rs1 > 0) Rd = val2; 4076221Snate@binkert.org break; 4082307SN/A case 7: 4091060SN/A if(Rs1 >= 0) Rd = val2; 4102307SN/A break; 4112307SN/A } 4122873Sktlim@umich.edu }});//MOVR 4132307SN/A 0x30: decode RD { 4141060SN/A 0x0: wry({{ 4151060SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4161060SN/A xc->regs.MiscRegs.y = Rs1 ^ val2; 4171681SN/A }});//WRY 4181060SN/A 0x2: wrccr({{ 4196221Snate@binkert.org UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4202107SN/A xc->regs.MiscRegs.ccr = Rs1 ^ val2; 4216221Snate@binkert.org }});//WRCCR 4222107SN/A 0x3: wrasi({{ 4232292SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4242292SN/A xc->regs.MiscRegs.asi = Rs1 ^ val2; 4252107SN/A }});//WRASI 4262292SN/A 0x6: wrfprs({{ 4272326SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4282292SN/A xc->regs.MiscRegs.asi = Rs1 ^ val2; 4292107SN/A }});//WRFPRS 4302292SN/A 0xF: Trap::sir({{software_initiated_reset}}); //SIR 4312935Sksewell@umich.edu } 4324632Sgblack@eecs.umich.edu 0x31: decode FCN { 4332935Sksewell@umich.edu 0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED 4342292SN/A 0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED 4352292SN/A } 4362292SN/A 0x32: decode RD { 4372292SN/A 0x0: wrprtpc({{checkPriv 4382292SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4392107SN/A xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2; 4402292SN/A }}); 4412107SN/A 0x1: wrprtnpc({{checkPriv 4422292SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4432292SN/A xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2; 4442107SN/A }}); 4452702Sktlim@umich.edu 0x2: wrprtstate({{checkPriv 4462107SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4472107SN/A xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl] = Rs1 ^ val2; 4482107SN/A }}); 4492107SN/A 0x3: wrprtt({{checkPriv 4506221Snate@binkert.org UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4512292SN/A xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl] = Rs1 ^ val2; 4522292SN/A }}); 4532292SN/A 0x4: wrprtick({{checkPriv 4542292SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4552292SN/A xc->regs.MiscRegs.tick = Rs1 ^ val2; 4562292SN/A }}); 4572292SN/A 0x5: wrprtba({{checkPriv 4582292SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4592935Sksewell@umich.edu xc->regs.MiscRegs.tba = Rs1 ^ val2; 4604632Sgblack@eecs.umich.edu }}); 4613969Sgblack@eecs.umich.edu 0x6: wrprpstate({{checkPriv 4624632Sgblack@eecs.umich.edu UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4633795Sgblack@eecs.umich.edu xc->regs.MiscRegs.pstate = Rs1 ^ val2; 4643795Sgblack@eecs.umich.edu }}); 4653795Sgblack@eecs.umich.edu 0x7: wrprtl({{checkPriv 4663093Sksewell@umich.edu UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4673093Sksewell@umich.edu xc->regs.MiscRegs.tl = Rs1 ^ val2; 4683093Sksewell@umich.edu }}); 4694632Sgblack@eecs.umich.edu 0x8: wrprpil({{checkPriv 4703093Sksewell@umich.edu UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4714632Sgblack@eecs.umich.edu xc->regs.MiscRegs.pil = Rs1 ^ val2; 4724636Sgblack@eecs.umich.edu }}); 4732292SN/A 0x9: wrprcwp({{checkPriv 4742292SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4752292SN/A xc->regs.MiscRegs.cwp = Rs1 ^ val2; 4762292SN/A }}); 4772292SN/A 0xA: wrprcansave({{checkPriv 4782292SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4792292SN/A xc->regs.MiscRegs.cansave = Rs1 ^ val2; 4802292SN/A }}); 4816221Snate@binkert.org 0xB: wrprcanrestore({{checkPriv 4822292SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4832292SN/A xc->regs.MiscRegs.canrestore = Rs1 ^ val2; 4842292SN/A }}); 4852292SN/A 0xC: wrprcleanwin({{checkPriv 4862292SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4872292SN/A xc->regs.MiscRegs.cleanwin = Rs1 ^ val2; 4882292SN/A }}); 4893795Sgblack@eecs.umich.edu 0xD: wrprotherwin({{checkPriv 4903732Sktlim@umich.edu UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4912292SN/A xc->regs.MiscRegs.otherwin = Rs1 ^ val2; 4922292SN/A }}); 4932292SN/A 0xE: wrprwstate({{checkPriv 4942292SN/A UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); 4952292SN/A xc->regs.MiscRegs.wstate = Rs1 ^ val2; 4962292SN/A }}); 4972292SN/A } 4982292SN/A 4996221Snate@binkert.org 0x34: Trap::fpop1({{Throw fp_disabled;}}); //FPOP1 5002292SN/A 0x35: Trap::fpop2({{Throw fp_disabled;}}); //FPOP2 5012292SN/A 5022292SN/A 5032292SN/A 0x38: Branch::jmpl({{//Stuff}}); //JMPL 5042292SN/A 0x39: Branch::return({{//Other Stuff}}); //RETURN 5052292SN/A 0x3A: Trap::tcc({{ 5062292SN/A switch((CC14 << 1) | (CC04 << 0)) 5073958Sgblack@eecs.umich.edu { 5083732Sktlim@umich.edu case 1: case 3: 5092292SN/A throw illegal_instruction; 5102348SN/A case 0: 5112292SN/A if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>)) 5122292SN/A throw trap_instruction; 5132292SN/A break; 5142292SN/A case 2: 5152292SN/A if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>)) 5162292SN/A throw trap_instruction; 5172292SN/A break; 5182292SN/A } 5192292SN/A }}); //Tcc 5206221Snate@binkert.org 0x3B: BasicOperate::flush({{//Lala}}); //FLUSH 5212292SN/A 0x3C: BasicOperate::save({{//leprechauns); //SAVE 5222292SN/A 0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE 5232292SN/A 0x3E: decode FCN { 5242292SN/A 0x1: BasicOperate::done({{//Done thing}}); //DONE 5252292SN/A 0x2: BasicOperate::retry({{//Retry thing}}); //RETRY 5262292SN/A } 5272292SN/A } 5282292SN/A } 5292292SN/A 0x3: decode OP3 { 5302292SN/A format Mem { 5312292SN/A 0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW 5322292SN/A 0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB 5332292SN/A 0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH 5342292SN/A 0x03: ldd({{ 5352292SN/A UINT64 val = Mem.udw; 5362292SN/A setIntReg(RD & (~1), val<31:0>); 5372292SN/A setIntReg(RD | 1, val<63:32>); 5382292SN/A }});//LDD 5396221Snate@binkert.org 0x04: stw({{Mem.sw = Rd.sw;}}); //STW 5402292SN/A 0x05: stb({{Mem.sb = Rd.sb;}}); //STB 5412292SN/A 0x06: sth({{Mem.shw = Rd.shw;}}); //STH 5422292SN/A 0x07: std({{ 5432292SN/A Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); 5442292SN/A }});//STD 5452292SN/A 0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW 5462292SN/A 0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB 5472292SN/A 0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH 5482292SN/A 0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX 5492292SN/A 5502292SN/A 0x0D: ldstub({{ 5512292SN/A Rd.ub = Mem.ub; 5522292SN/A Mem.ub = 0xFF; 5532292SN/A }}); //LDSTUB 5542292SN/A 0x0E: stx({{Rd.udw = Mem.udw;}}); //STX 5552292SN/A 0x0F: swap({{ 5562292SN/A UINT32 temp = Rd.uw; 5571060SN/A Rd.uw = Mem.uw; 5581681SN/A Mem.uw = temp; 5591060SN/A }}); //SWAP 5601060SN/A 0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA 5612292SN/A 0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA 5622292SN/A 0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA 5632292SN/A 0x13: ldda({{ 5642292SN/A UINT64 val = Mem.udw; 5652292SN/A setIntReg(RD & (~1), val<31:0>); 5662292SN/A setIntReg(RD | 1, val<63:32>); 5671681SN/A }}); //LDDA 5681681SN/A 0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA 5691060SN/A 0x15: stba({{Mem.ub = Rd.ub;}}); //STBA 5702292SN/A 0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA 5711060SN/A 0x17: stda({{ 5722292SN/A Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); 5732292SN/A }}); //STDA 5741060SN/A 0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA 5752292SN/A 0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA 5762292SN/A 0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA 5772292SN/A 0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA 5782292SN/A 5793221Sktlim@umich.edu 0x1D: ldstuba({{ 5803221Sktlim@umich.edu Rd.ub = Mem.ub; 5813221Sktlim@umich.edu Mem.ub = 0xFF; 5823221Sktlim@umich.edu }}); //LDSTUBA 5833221Sktlim@umich.edu 0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA 5842292SN/A 0x1F: swapa({{ 5852292SN/A UINT32 temp = Rd.uw; 5862292SN/A Rd.uw = Mem.uw; 5872292SN/A Mem.uw = temp; 5882326SN/A }}); //SWAPA 5892292SN/A 0x20: Trap::ldf({{throw fp_disabled;}}); //LDF 5902292SN/A 0x21: decode X { 5912820Sktlim@umich.edu 0x0: Trap::ldfsr({{throw fp_disabled;}}); //LDFSR 5922292SN/A 0x1: Trap::ldxfsr({{throw fp_disabled;}}); //LDXFSR 5932292SN/A } 5942292SN/A 0x22: Trap::ldqf({{throw fp_disabled;}}); //LDQF 5952292SN/A 0x23: Trap::lddf({{throw fp_disabled;}}); //LDDF 5962353SN/A 0x24: Trap::stf({{throw fp_disabled;}}); //STF 5972292SN/A 0x25: decode X { 5982292SN/A 0x0: Trap::stfsr({{throw fp_disabled;}}); //STFSR 5992353SN/A 0x1: Trap::stxfsr({{throw fp_disabled;}}); //STXFSR 6002353SN/A } 6012292SN/A 0x26: Trap::stqf({{throw fp_disabled;}}); //STQF 6022292SN/A 0x27: Trap::stdf({{throw fp_disabled;}}); //STDF 6032292SN/A 6042292SN/A 6052292SN/A 6062292SN/A 6072292SN/A 6082292SN/A 0x2D: Noop::prefetch({{ }}); //PREFETCH 6092292SN/A 6102292SN/A 6112292SN/A 0x30: Trap::ldfa({{throw fp_disabled;}}); //LDFA 6122292SN/A 6132731Sktlim@umich.edu 0x32: Trap::ldqfa({{throw fp_disabled;}}); //LDQFA 6142292SN/A 0x33: Trap::lddfa({{throw fp_disabled;}}); //LDDFA 6152292SN/A 0x34: Trap::stfa({{throw fp_disabled;}}); //STFA 6162292SN/A 0x35: Trap::stqfa({{throw fp_disabled;}}); //STQFA 6172292SN/A 0x36: Trap::stdfa({{throw fp_disabled;}}); //STDFA 6182292SN/A 6192292SN/A 6202292SN/A 6212292SN/A 6226221Snate@binkert.org 6232292SN/A 0x3C: Cas::casa( 6242292SN/A {{UINT64 val = Mem.uw; 6252292SN/A if(Rs2.uw == val) 6262292SN/A Mem.uw = Rd.uw; 6272292SN/A Rd.uw = val; 6282292SN/A }}); //CASA 6292292SN/A 0x3D: Noop::prefetcha({{ }}); //PREFETCHA 6302292SN/A 0x3E: Cas::casxa( 6312292SN/A {{UINT64 val = Mem.udw; 6322292SN/A if(Rs2 == val) 6332292SN/A Mem.udw = Rd; 6342292SN/A Rd = val; 6352292SN/A }}); //CASXA 6362292SN/A } 6372292SN/A } 6382292SN/A} 6392292SN/A