decoder.isa revision 13389
11689SN/A// -*- mode:c++ -*- 210333Smitch.hayenga@arm.com 39920Syasuko.eckert@amd.com// Copyright (c) 2007 MIPS Technologies, Inc. 47944SGiacomo.Gabrielli@arm.com// All rights reserved. 57944SGiacomo.Gabrielli@arm.com// 67944SGiacomo.Gabrielli@arm.com// Redistribution and use in source and binary forms, with or without 77944SGiacomo.Gabrielli@arm.com// modification, are permitted provided that the following conditions are 87944SGiacomo.Gabrielli@arm.com// met: redistributions of source code must retain the above copyright 97944SGiacomo.Gabrielli@arm.com// notice, this list of conditions and the following disclaimer; 107944SGiacomo.Gabrielli@arm.com// redistributions in binary form must reproduce the above copyright 117944SGiacomo.Gabrielli@arm.com// notice, this list of conditions and the following disclaimer in the 127944SGiacomo.Gabrielli@arm.com// documentation and/or other materials provided with the distribution; 137944SGiacomo.Gabrielli@arm.com// neither the name of the copyright holders nor the names of its 147944SGiacomo.Gabrielli@arm.com// contributors may be used to endorse or promote products derived from 152326SN/A// this software without specific prior written permission. 161689SN/A// 171689SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 281689SN/A// 291689SN/A// Authors: Korey Sewell 301689SN/A// Brett Miller 311689SN/A// Jaidev Patwardhan 321689SN/A 331689SN/A//////////////////////////////////////////////////////////////////// 341689SN/A// 351689SN/A// The actual MIPS32 ISA decoder 361689SN/A// ----------------------------- 371689SN/A// The following instructions are specified in the MIPS32 ISA 381689SN/A// Specification. Decoding closely follows the style specified 391689SN/A// in the MIPS32 ISA specification document starting with Table 402665Ssaidi@eecs.umich.edu// A-2 (document available @ http://www.mips.com) 412665Ssaidi@eecs.umich.edu// 422831Sksewell@umich.edudecode OPCODE_HI default Unknown::unknown() { 431689SN/A //Table A-2 441689SN/A 0x0: decode OPCODE_LO { 459944Smatt.horsnell@ARM.com 0x0: decode FUNCTION_HI { 469944Smatt.horsnell@ARM.com 0x0: decode FUNCTION_LO { 479944Smatt.horsnell@ARM.com 0x1: decode MOVCI { 482064SN/A format BasicOp { 491060SN/A 0: movf({{ 501060SN/A Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; 512292SN/A }}); 521717SN/A 1: movt({{ 538232Snate@binkert.org Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; 544762Snate@binkert.org }}); 556221Snate@binkert.org } 564762Snate@binkert.org } 571060SN/A 588737Skoansin.tan@gmail.com format BasicOp { 598737Skoansin.tan@gmail.com //Table A-3 Note: "Specific encodings of the rd, rs, and 608737Skoansin.tan@gmail.com //rt fields are used to distinguish SLL, SSNOP, and EHB 615529Snate@binkert.org //functions 621061SN/A 0x0: decode RS { 632292SN/A 0x0: decode RT_RD { 645606Snate@binkert.org 0x0: decode SA default Nop::nop() { 658581Ssteve.reinhardt@amd.com 0x1: ssnop({{;}}); 668581Ssteve.reinhardt@amd.com 0x3: ehb({{;}}); 671060SN/A } 682292SN/A default: sll({{ Rd = Rt << SA; }}); 692292SN/A } 702292SN/A } 712292SN/A 722292SN/A 0x2: decode RS_SRL { 732292SN/A 0x0:decode SRL { 742326SN/A 0: srl({{ Rd = Rt >> SA; }}); 752292SN/A 762292SN/A //Hardcoded assuming 32-bit ISA, 772292SN/A //probably need parameter here 782292SN/A 1: rotr({{ 792292SN/A Rd = (Rt << (32 - SA)) | (Rt >> SA); 802292SN/A }}); 815336Shines@cs.fsu.edu } 822292SN/A } 834873Sstever@eecs.umich.edu 842292SN/A 0x3: decode RS { 852292SN/A 0x0: sra({{ 862292SN/A uint32_t temp = Rt >> SA; 874329Sktlim@umich.edu if ( (Rt & 0x80000000) > 0 ) { 885529Snate@binkert.org uint32_t mask = 0x80000000; 894329Sktlim@umich.edu for(int i=0; i < SA; i++) { 904329Sktlim@umich.edu temp |= mask; 914329Sktlim@umich.edu mask = mask >> 1; 922292SN/A } 932292SN/A } 942292SN/A Rd = temp; 952292SN/A }}); 962292SN/A } 972292SN/A 985529Snate@binkert.org 0x4: sllv({{ Rd = Rt << Rs<4:0>; }}); 991060SN/A 1009920Syasuko.eckert@amd.com 0x6: decode SRLV { 1019920Syasuko.eckert@amd.com 0: srlv({{ Rd = Rt >> Rs<4:0>; }}); 1029920Syasuko.eckert@amd.com 1031060SN/A //Hardcoded assuming 32-bit ISA, 1041060SN/A //probably need parameter here 1051060SN/A 1: rotrv({{ 1062326SN/A Rd = (Rt << (32 - Rs<4:0>)) | (Rt >> Rs<4:0>); 1071060SN/A }}); 1081060SN/A } 1091060SN/A 1101060SN/A 0x7: srav({{ 1112292SN/A int shift_amt = Rs<4:0>; 1126221Snate@binkert.org 1136221Snate@binkert.org uint32_t temp = Rt >> shift_amt; 1146221Snate@binkert.org 1151060SN/A if ((Rt & 0x80000000) > 0) { 1161060SN/A uint32_t mask = 0x80000000; 1172307SN/A for (int i = 0; i < shift_amt; i++) { 1182292SN/A temp |= mask; 1192980Sgblack@eecs.umich.edu mask = mask >> 1; 1202292SN/A } 1212292SN/A } 1222292SN/A Rd = temp; 1232292SN/A }}); 1242292SN/A } 1252292SN/A } 1262292SN/A 1272292SN/A 0x1: decode FUNCTION_LO { 1282292SN/A //Table A-3 Note: "Specific encodings of the hint field are 1292292SN/A //used to distinguish JR from JR.HB and JALR from JALR.HB" 1306221Snate@binkert.org format Jump { 1316221Snate@binkert.org 0x0: decode HINT { 1322292SN/A 0x1: jr_hb({{ 1332292SN/A Config1Reg config1 = Config1; 1342292SN/A if (config1.ca == 0) { 1352292SN/A NNPC = Rs; 1362292SN/A } else { 1372292SN/A panic("MIPS16e not supported\n"); 1382292SN/A } 1392292SN/A }}, IsReturn, ClearHazards); 1402292SN/A default: jr({{ 1416221Snate@binkert.org Config1Reg config1 = Config1; 1426221Snate@binkert.org if (config1.ca == 0) { 1432292SN/A NNPC = Rs; 1442292SN/A } else { 1452831Sksewell@umich.edu panic("MIPS16e not supported\n"); 1462292SN/A } 1472292SN/A }}, IsReturn); 1482292SN/A } 1492292SN/A 1502292SN/A 0x1: decode HINT { 1512292SN/A 0x1: jalr_hb({{ 1522292SN/A Rd = NNPC; 1532292SN/A NNPC = Rs; 1542292SN/A }}, IsCall, ClearHazards); 1556221Snate@binkert.org default: jalr({{ 1566221Snate@binkert.org Rd = NNPC; 1572292SN/A NNPC = Rs; 1582292SN/A }}, IsCall); 1592831Sksewell@umich.edu } 1602292SN/A } 1612292SN/A 1622292SN/A format BasicOp { 1632292SN/A 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 1642292SN/A 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 1652292SN/A 0x4: decode FullSystemInt { 1662292SN/A 0: syscall_se({{ xc->syscall(R2, &fault); }}, 1672292SN/A IsSerializeAfter, IsNonSpeculative); 1682292SN/A default: syscall({{ fault = std::make_shared<SystemCallFault>(); }}); 1692292SN/A } 1702326SN/A 0x7: sync({{ ; }}, IsMemBarrier); 1712348SN/A 0x5: break({{fault = std::make_shared<BreakpointFault>();}}); 1722326SN/A } 1732326SN/A 1742348SN/A } 1752292SN/A 1762292SN/A 0x2: decode FUNCTION_LO { 1772292SN/A 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, 1782292SN/A IntMultOp, IsIprAccess); 1792292SN/A 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); 1802292SN/A 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, 1812292SN/A IntMultOp, IsIprAccess); 1821060SN/A 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); 1831060SN/A } 1841061SN/A 1851060SN/A 0x3: decode FUNCTION_LO { 1861062SN/A format HiLoRdSelValOp { 1871062SN/A 0x0: mult({{ val = Rs_sd * Rt_sd; }}, IntMultOp); 1882301SN/A 0x1: multu({{ val = Rs_ud * Rt_ud; }}, IntMultOp); 1891062SN/A } 1901062SN/A 1911062SN/A format HiLoOp { 1921062SN/A 0x2: div({{ 1931062SN/A if (Rt_sd != 0) { 1941062SN/A HI0 = Rs_sd % Rt_sd; 1951062SN/A LO0 = Rs_sd / Rt_sd; 1961062SN/A } 1971062SN/A }}, IntDivOp); 1981062SN/A 1992301SN/A 0x3: divu({{ 2002301SN/A if (Rt_ud != 0) { 2012301SN/A HI0 = Rs_ud % Rt_ud; 2022301SN/A LO0 = Rs_ud / Rt_ud; 2031062SN/A } 2041062SN/A }}, IntDivOp); 2051062SN/A } 2061062SN/A } 2071062SN/A 2081062SN/A 0x4: decode HINT { 2091062SN/A 0x0: decode FUNCTION_LO { 2101062SN/A format IntOp { 2111062SN/A 0x0: add({{ 2121062SN/A uint32_t result; 2131062SN/A Rd = result = Rs + Rt; 2141062SN/A if (FullSystem && 2151062SN/A findOverflow(32, result, Rs, Rt)) { 2161062SN/A fault = std::make_shared<IntegerOverflowFault>(); 2171062SN/A } 2181062SN/A }}); 2191062SN/A 0x1: addu({{ Rd = Rs_sw + Rt_sw;}}); 2201062SN/A 0x2: sub({{ 2211062SN/A uint32_t result; 2221062SN/A Rd = result = Rs - Rt; 2231062SN/A if (FullSystem && 2241062SN/A findOverflow(32, result, Rs, ~Rt)) { 2251062SN/A fault = std::make_shared<IntegerOverflowFault>(); 2261062SN/A } 2271062SN/A }}); 2281062SN/A 0x3: subu({{ Rd = Rs_sw - Rt_sw; }}); 2291062SN/A 0x4: and({{ Rd = Rs & Rt; }}); 2301062SN/A 0x5: or({{ Rd = Rs | Rt; }}); 2311062SN/A 0x6: xor({{ Rd = Rs ^ Rt; }}); 2321062SN/A 0x7: nor({{ Rd = ~(Rs | Rt); }}); 2331062SN/A } 2341062SN/A } 2351062SN/A } 2361062SN/A 2371062SN/A 0x5: decode HINT { 2381062SN/A 0x0: decode FUNCTION_LO { 2391062SN/A format IntOp{ 2401062SN/A 0x2: slt({{ Rd = (Rs_sw < Rt_sw) ? 1 : 0 }}); 2411062SN/A 0x3: sltu({{ Rd = (Rs < Rt) ? 1 : 0 }}); 2421062SN/A } 2431062SN/A } 2441062SN/A } 2451062SN/A 2461062SN/A 0x6: decode FUNCTION_LO { 2471062SN/A format Trap { 2481062SN/A 0x0: tge({{ cond = (Rs_sw >= Rt_sw); }}); 2491062SN/A 0x1: tgeu({{ cond = (Rs >= Rt); }}); 2502361SN/A 0x2: tlt({{ cond = (Rs_sw < Rt_sw); }}); 2512326SN/A 0x3: tltu({{ cond = (Rs < Rt); }}); 2522301SN/A 0x4: teq({{ cond = (Rs_sw == Rt_sw); }}); 2532301SN/A 0x6: tne({{ cond = (Rs_sw != Rt_sw); }}); 2542301SN/A } 2552301SN/A } 2562301SN/A } 2572301SN/A 2582326SN/A 0x1: decode REGIMM_HI { 2592301SN/A 0x0: decode REGIMM_LO { 2602361SN/A format Branch { 2612326SN/A 0x0: bltz({{ cond = (Rs_sw < 0); }}); 2622307SN/A 0x1: bgez({{ cond = (Rs_sw >= 0); }}); 2638240Snate@binkert.org 0x2: bltzl({{ cond = (Rs_sw < 0); }}, Likely); 2642301SN/A 0x3: bgezl({{ cond = (Rs_sw >= 0); }}, Likely); 2652307SN/A } 2662301SN/A } 2672301SN/A 2682301SN/A 0x1: decode REGIMM_LO { 2692301SN/A format TrapImm { 2708240Snate@binkert.org 0x0: tgei( {{ cond = (Rs_sw >= (int16_t)INTIMM); }}); 2712301SN/A 0x1: tgeiu({{ 2722301SN/A cond = (Rs >= (uint32_t)(int32_t)(int16_t)INTIMM); 2732301SN/A }}); 2742301SN/A 0x2: tlti( {{ cond = (Rs_sw < (int16_t)INTIMM); }}); 2752301SN/A 0x3: tltiu({{ 2762301SN/A cond = (Rs < (uint32_t)(int32_t)(int16_t)INTIMM); 2772301SN/A }}); 2782326SN/A 0x4: teqi( {{ cond = (Rs_sw == (int16_t)INTIMM); }}); 2794762Snate@binkert.org 0x6: tnei( {{ cond = (Rs_sw != (int16_t)INTIMM); }}); 2808240Snate@binkert.org } 2812301SN/A } 2822301SN/A 2832301SN/A 0x2: decode REGIMM_LO { 2844762Snate@binkert.org format Branch { 2852301SN/A 0x0: bltzal({{ cond = (Rs_sw < 0); }}, Link); 2862301SN/A 0x1: decode RS { 2872301SN/A 0x0: bal ({{ cond = 1; }}, IsCall, Link); 2882301SN/A default: bgezal({{ cond = (Rs_sw >= 0); }}, Link); 2892361SN/A } 2902326SN/A 0x2: bltzall({{ cond = (Rs_sw < 0); }}, Link, Likely); 2912301SN/A 0x3: bgezall({{ cond = (Rs_sw >= 0); }}, Link, Likely); 2928240Snate@binkert.org } 2932301SN/A } 2942301SN/A 2952301SN/A 0x3: decode REGIMM_LO { 2962301SN/A // from Table 5-4 MIPS32 REGIMM Encoding of rt Field 2972301SN/A // (DSP ASE MANUAL) 2982980Sgblack@eecs.umich.edu 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 2992301SN/A format WarnUnimpl { 3002326SN/A 0x7: synci(); 3012301SN/A } 3022361SN/A } 3032326SN/A } 3048240Snate@binkert.org 3052301SN/A format Jump { 3062301SN/A 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}); 3072301SN/A 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, 3082326SN/A IsCall, Link); 3092727Sktlim@umich.edu } 3102326SN/A 3112301SN/A format Branch { 3128240Snate@binkert.org 0x4: decode RS_RT { 3132301SN/A 0x0: b({{ cond = 1; }}); 3142301SN/A default: beq({{ cond = (Rs_sw == Rt_sw); }}); 3152301SN/A } 3162301SN/A 0x5: bne({{ cond = (Rs_sw != Rt_sw); }}); 3174762Snate@binkert.org 0x6: blez({{ cond = (Rs_sw <= 0); }}); 3182301SN/A 0x7: bgtz({{ cond = (Rs_sw > 0); }}); 3192301SN/A } 3202326SN/A } 3212301SN/A 3228240Snate@binkert.org 0x1: decode OPCODE_LO { 3232301SN/A format IntImmOp { 3242301SN/A 0x0: addi({{ 3252301SN/A uint32_t result; 3262301SN/A Rt = result = Rs + imm; 3272326SN/A if (FullSystem && 3288240Snate@binkert.org findOverflow(32, result, Rs, imm)) { 3292301SN/A fault = std::make_shared<IntegerOverflowFault>(); 3302301SN/A } 3312301SN/A }}); 3322326SN/A 0x1: addiu({{ Rt = Rs_sw + imm; }}); 3332301SN/A 0x2: slti({{ Rt = (Rs_sw < imm) ? 1 : 0 }}); 3346221Snate@binkert.org 0x3: sltiu({{ Rt = (Rs < (uint32_t)sextImm) ? 1 : 0;}}); 3352292SN/A 0x4: andi({{ Rt = Rs_sw & zextImm; }}); 3366221Snate@binkert.org 0x5: ori({{ Rt = Rs_sw | zextImm; }}); 3372292SN/A 0x6: xori({{ Rt = Rs_sw ^ zextImm; }}); 3387897Shestness@cs.utexas.edu 3397897Shestness@cs.utexas.edu 0x7: decode RS { 3407897Shestness@cs.utexas.edu 0x0: lui({{ Rt = imm << 16; }}); 3417897Shestness@cs.utexas.edu } 3427897Shestness@cs.utexas.edu } 3437897Shestness@cs.utexas.edu } 3447897Shestness@cs.utexas.edu 3457897Shestness@cs.utexas.edu 0x2: decode OPCODE_LO { 3467897Shestness@cs.utexas.edu //Table A-11 MIPS32 COP0 Encoding of rs Field 3477897Shestness@cs.utexas.edu 0x0: decode RS_MSB { 3487897Shestness@cs.utexas.edu 0x0: decode RS { 3497897Shestness@cs.utexas.edu format CP0Control { 3507897Shestness@cs.utexas.edu 0x0: mfc0({{ 3517897Shestness@cs.utexas.edu Config3Reg config3 = Config3; 3527897Shestness@cs.utexas.edu PageGrainReg pageGrain = PageGrain; 3537897Shestness@cs.utexas.edu Rt = CP0_RD_SEL; 3547897Shestness@cs.utexas.edu /* Hack for PageMask */ 3557897Shestness@cs.utexas.edu if (RD == 5) { 3567897Shestness@cs.utexas.edu // PageMask 3577897Shestness@cs.utexas.edu if (config3.sp == 0 || pageGrain.esp == 0) 3587897Shestness@cs.utexas.edu Rt &= 0xFFFFE7FF; 3597897Shestness@cs.utexas.edu } 3607897Shestness@cs.utexas.edu }}); 3617897Shestness@cs.utexas.edu 0x4: mtc0({{ 3627897Shestness@cs.utexas.edu CP0_RD_SEL = Rt; 3637897Shestness@cs.utexas.edu CauseReg cause = Cause; 3647897Shestness@cs.utexas.edu IntCtlReg intCtl = IntCtl; 3657897Shestness@cs.utexas.edu if (RD == 11) { 3667897Shestness@cs.utexas.edu // Compare 3677897Shestness@cs.utexas.edu if (cause.ti == 1) { 3687897Shestness@cs.utexas.edu cause.ti = 0; 3697897Shestness@cs.utexas.edu int offset = 10; // corresponding to cause.ip0 3707897Shestness@cs.utexas.edu offset += intCtl.ipti - 2; 3717897Shestness@cs.utexas.edu replaceBits(cause, offset, offset, 0); 3727897Shestness@cs.utexas.edu } 3737897Shestness@cs.utexas.edu } 3747897Shestness@cs.utexas.edu Cause = cause; 3757897Shestness@cs.utexas.edu }}); 3767897Shestness@cs.utexas.edu } 3777897Shestness@cs.utexas.edu format CP0Unimpl { 3787897Shestness@cs.utexas.edu 0x1: dmfc0(); 3791062SN/A 0x5: dmtc0(); 3801062SN/A default: unknown(); 3811062SN/A } 3821062SN/A format MT_MFTR { 3832307SN/A // Decode MIPS MT MFTR instruction into sub-instructions 3841060SN/A 0x8: decode MT_U { 3852307SN/A 0x0: mftc0({{ 3866221Snate@binkert.org data = xc->readRegOtherThread(RegId(MiscRegClass, 3876221Snate@binkert.org (RT << 3 | SEL))); 3886221Snate@binkert.org }}); 3892307SN/A 0x1: decode SEL { 3901060SN/A 0x0: mftgpr({{ 3912307SN/A data = xc->readRegOtherThread( 3922307SN/A RegId(IntRegClass, RT)); 3932307SN/A }}); 3942307SN/A 0x1: decode RT { 3952307SN/A 0x0: mftlo_dsp0({{ 3962307SN/A data = xc->readRegOtherThread( 3972307SN/A RegId(IntRegClass, INTREG_DSP_LO0)); 3982307SN/A }}); 3992307SN/A 0x1: mfthi_dsp0({{ 4002307SN/A data = xc->readRegOtherThread( 4012307SN/A RegId(IntRegClass, INTREG_DSP_HI0)); 4022307SN/A }}); 4036221Snate@binkert.org 0x2: mftacx_dsp0({{ 4046221Snate@binkert.org data = xc->readRegOtherThread( 4052307SN/A RegId(IntRegClass, INTREG_DSP_ACX0)); 4062307SN/A }}); 4072307SN/A 0x4: mftlo_dsp1({{ 4082307SN/A data = xc->readRegOtherThread( 4092307SN/A RegId(IntRegClass, INTREG_DSP_LO1)); 4102307SN/A }}); 4112307SN/A 0x5: mfthi_dsp1({{ 4122307SN/A data = xc->readRegOtherThread( 4132307SN/A RegId(IntRegClass, INTREG_DSP_HI1)); 4142307SN/A }}); 4157944SGiacomo.Gabrielli@arm.com 0x6: mftacx_dsp1({{ 41610333Smitch.hayenga@arm.com data = xc->readRegOtherThread( 41710333Smitch.hayenga@arm.com RegId(IntRegClass, INTREG_DSP_ACX1)); 4181060SN/A }}); 4191060SN/A 0x8: mftlo_dsp2({{ 4201061SN/A data = xc->readRegOtherThread( 4211060SN/A RegId(IntRegClass, INTREG_DSP_LO2)); 4226221Snate@binkert.org }}); 4231060SN/A 0x9: mfthi_dsp2({{ 4242292SN/A data = xc->readRegOtherThread( 4252064SN/A RegId(IntRegClass, INTREG_DSP_HI2)); 4262064SN/A }}); 4272064SN/A 0x10: mftacx_dsp2({{ 4282064SN/A data = xc->readRegOtherThread( 4292292SN/A RegId(IntRegClass, INTREG_DSP_ACX2)); 4302064SN/A }}); 4314318Sktlim@umich.edu 0x12: mftlo_dsp3({{ 4321060SN/A data = xc->readRegOtherThread( 4331060SN/A RegId(IntRegClass, INTREG_DSP_LO3)); 4341061SN/A }}); 4351060SN/A 0x13: mfthi_dsp3({{ 4361060SN/A data = xc->readRegOtherThread( 4371060SN/A RegId(IntRegClass, INTREG_DSP_HI3)); 4381060SN/A }}); 4391060SN/A 0x14: mftacx_dsp3({{ 4401060SN/A data = xc->readRegOtherThread( 4411060SN/A RegId(IntRegClass, INTREG_DSP_ACX3)); 4421060SN/A }}); 4431684SN/A 0x16: mftdsp({{ 44410510Smitch.hayenga@arm.com data = xc->readRegOtherThread( 44510510Smitch.hayenga@arm.com RegId(IntRegClass, INTREG_DSP_CONTROL)); 44610510Smitch.hayenga@arm.com }}); 44710510Smitch.hayenga@arm.com default: CP0Unimpl::unknown(); 44810510Smitch.hayenga@arm.com } 44910510Smitch.hayenga@arm.com 0x2: decode MT_H { 45010510Smitch.hayenga@arm.com 0x0: mftc1({{ 45110510Smitch.hayenga@arm.com data = xc->readRegOtherThread( 45210510Smitch.hayenga@arm.com RegId(FloatRegClass, RT)); 45310510Smitch.hayenga@arm.com }}); 45410510Smitch.hayenga@arm.com 0x1: mfthc1({{ 4552307SN/A data = xc->readRegOtherThread( 4569444SAndreas.Sandberg@ARM.com RegId(FloatRegClass, RT)); 4572307SN/A }}); 4589444SAndreas.Sandberg@ARM.com } 4599444SAndreas.Sandberg@ARM.com 0x3: cftc1({{ 4609444SAndreas.Sandberg@ARM.com uint32_t fcsr_val = xc->readRegOtherThread( 4619444SAndreas.Sandberg@ARM.com RegId(FloatRegClass, FLOATREG_FCSR)); 4622307SN/A switch (RT) { 4632307SN/A case 0: 4642307SN/A data = xc->readRegOtherThread( 4652307SN/A RegId(MiscRegClass, FLOATREG_FIR)); 4662307SN/A break; 4672307SN/A case 25: 4689444SAndreas.Sandberg@ARM.com data = (fcsr_val & 0xFE000000 >> 24) | 4692307SN/A (fcsr_val & 0x00800000 >> 23); 4702307SN/A break; 4712307SN/A case 26: 4722292SN/A data = fcsr_val & 0x0003F07C; 4736221Snate@binkert.org break; 4742292SN/A case 28: 4752292SN/A data = (fcsr_val & 0x00000F80) | 4762292SN/A (fcsr_val & 0x01000000 >> 21) | 4772292SN/A (fcsr_val & 0x00000003); 4782292SN/A break; 4792292SN/A case 31: 4802292SN/A data = fcsr_val; 4812292SN/A break; 4822292SN/A default: 4832292SN/A fatal("FP Control Value (%d) Not Valid"); 4842292SN/A } 4852292SN/A }}); 4862292SN/A default: CP0Unimpl::unknown(); 4872292SN/A } 4883867Sbinkertn@umich.edu } 4892292SN/A } 4906221Snate@binkert.org 4916221Snate@binkert.org format MT_MTTR { 4922292SN/A // Decode MIPS MT MTTR instruction into sub-instructions 4933867Sbinkertn@umich.edu 0xC: decode MT_U { 4946221Snate@binkert.org 0x0: mttc0({{ xc->setRegOtherThread( 4953867Sbinkertn@umich.edu RegId(MiscRegClass, (RD << 3 | SEL)), Rt); 4962292SN/A }}); 4973867Sbinkertn@umich.edu 0x1: decode SEL { 4982292SN/A 0x0: mttgpr({{ xc->setRegOtherThread( 4993867Sbinkertn@umich.edu RegId(IntRegClass, RD), Rt); 5002292SN/A }}); 5012292SN/A 0x1: decode RT { 5022292SN/A 0x0: mttlo_dsp0({{ xc->setRegOtherThread( 5032292SN/A RegId(IntRegClass, INTREG_DSP_LO0), Rt); 5042292SN/A }}); 5052292SN/A 0x1: mtthi_dsp0({{ xc->setRegOtherThread( 5061684SN/A RegId(IntRegClass, INTREG_DSP_HI0), Rt); 5071684SN/A }}); 5081684SN/A 0x2: mttacx_dsp0({{ xc->setRegOtherThread( 5091684SN/A RegId(IntRegClass, INTREG_DSP_ACX0), Rt); 5101684SN/A }}); 5111684SN/A 0x4: mttlo_dsp1({{ xc->setRegOtherThread( 5122292SN/A RegId(IntRegClass, INTREG_DSP_LO1), Rt); 5132292SN/A }}); 5146221Snate@binkert.org 0x5: mtthi_dsp1({{ xc->setRegOtherThread( 5152292SN/A RegId(IntRegClass, INTREG_DSP_HI1), Rt); 5162292SN/A }}); 5172292SN/A 0x6: mttacx_dsp1({{ xc->setRegOtherThread( 5182292SN/A RegId(IntRegClass, INTREG_DSP_ACX1), Rt); 5191060SN/A }}); 5201060SN/A 0x8: mttlo_dsp2({{ xc->setRegOtherThread( 5211061SN/A RegId(IntRegClass, INTREG_DSP_LO2), Rt); 5221060SN/A }}); 5231060SN/A 0x9: mtthi_dsp2({{ xc->setRegOtherThread( 5241060SN/A RegId(IntRegClass, INTREG_DSP_HI2), Rt); 5251060SN/A }}); 5261060SN/A 0x10: mttacx_dsp2({{ xc->setRegOtherThread( 5271060SN/A RegId(IntRegClass, INTREG_DSP_ACX2), Rt); 5281060SN/A }}); 5291060SN/A 0x12: mttlo_dsp3({{ xc->setRegOtherThread( 5301060SN/A RegId(IntRegClass, INTREG_DSP_LO3), Rt); 5311060SN/A }}); 5321061SN/A 0x13: mtthi_dsp3({{ xc->setRegOtherThread( 5332292SN/A RegId(IntRegClass, INTREG_DSP_HI3), Rt); 5346221Snate@binkert.org }}); 5352292SN/A 0x14: mttacx_dsp3({{ xc->setRegOtherThread( 5362292SN/A RegId(IntRegClass, INTREG_DSP_ACX3), Rt); 5372292SN/A }}); 5382292SN/A 0x16: mttdsp({{ xc->setRegOtherThread( 5392292SN/A RegId(IntRegClass, INTREG_DSP_CONTROL), Rt); 5402292SN/A }}); 5412292SN/A default: CP0Unimpl::unknown(); 5422292SN/A 5432292SN/A } 5442292SN/A 0x2: mttc1({{ 5452292SN/A uint64_t data = xc->readRegOtherThread( 5462292SN/A RegId(FloatRegClass, RD)); 5472292SN/A data = insertBits(data, MT_H ? 63 : 31, 5482292SN/A MT_H ? 32 : 0, Rt); 5492292SN/A xc->setRegOtherThread(RegId(FloatRegClass, RD), 5502292SN/A data); 5512292SN/A }}); 5522292SN/A 0x3: cttc1({{ 5532292SN/A uint32_t data; 5542292SN/A switch (RD) { 5552292SN/A case 25: 5562292SN/A data = (Rt<7:1> << 25) | // move 31-25 5572292SN/A (FCSR & 0x01000000) | // bit 24 5582292SN/A (FCSR & 0x004FFFFF); // bit 22-0 5592292SN/A break; 5602292SN/A case 26: 5611060SN/A data = (FCSR & 0xFFFC0000) | // move 31-18 5621061SN/A Rt<17:12> << 12 | // bit 17-12 5631060SN/A // bit 11-7 5647897Shestness@cs.utexas.edu (FCSR & 0x00000F80) << 7 | 5651060SN/A Rt<6:2> << 2 | // bit 6-2 5661060SN/A (FCSR & 0x00000002); // bit 1...0 5671060SN/A break; 5687720Sgblack@eecs.umich.edu case 28: 5697720Sgblack@eecs.umich.edu data = (FCSR & 0xFE000000) | // move 31-25 5701060SN/A Rt<2:2> << 24 | // bit 24 5711060SN/A // bit 23-12 5721060SN/A (FCSR & 0x00FFF000) << 23 | 5732292SN/A Rt<11:7> << 7 | // bit 24 5741060SN/A (FCSR & 0x000007E) | 5752064SN/A Rt<1:0>; // bit 22-0 5761060SN/A break; 5772292SN/A case 31: 5781060SN/A data = Rt; 5791060SN/A break; 5801060SN/A default: 5811060SN/A panic("FP Control Value (%d) " 5821060SN/A "Not Available. Ignoring " 5831060SN/A "Access to Floating Control " 5841060SN/A "S""tatus Register", FS); 5852326SN/A } 5861060SN/A xc->setRegOtherThread( 5871061SN/A RegId(FloatRegClass, FLOATREG_FCSR), data); 5882292SN/A }}); 5891062SN/A default: CP0Unimpl::unknown(); 5901062SN/A } 5911061SN/A } 5921061SN/A } 5931062SN/A 0xB: decode RD { 5941060SN/A format MT_Control { 5952292SN/A 0x0: decode POS { 5962292SN/A 0x0: decode SEL { 5971060SN/A 0x1: decode SC { 5981060SN/A 0x0: dvpe({{ 5991060SN/A MVPControlReg mvpControl = MVPControl; 6001061SN/A VPEConf0Reg vpeConf0 = VPEConf0; 6011061SN/A Rt = MVPControl; 6022292SN/A if (vpeConf0.mvp == 1) 6031061SN/A mvpControl.evp = 0; 6041061SN/A MVPControl = mvpControl; 6051061SN/A }}); 6067897Shestness@cs.utexas.edu 0x1: evpe({{ 6071061SN/A MVPControlReg mvpControl = MVPControl; 6082292SN/A VPEConf0Reg vpeConf0 = VPEConf0; 6091061SN/A Rt = MVPControl; 6102292SN/A if (vpeConf0.mvp == 1) 6111061SN/A mvpControl.evp = 1; 6127720Sgblack@eecs.umich.edu MVPControl = mvpControl; 6132326SN/A }}); 6147720Sgblack@eecs.umich.edu default:CP0Unimpl::unknown(); 6152064SN/A } 6161061SN/A default:CP0Unimpl::unknown(); 6171061SN/A } 6182292SN/A default:CP0Unimpl::unknown(); 6191061SN/A } 6202064SN/A 0x1: decode POS { 6211061SN/A 0xF: decode SEL { 6222292SN/A 0x1: decode SC { 6231061SN/A 0x0: dmt({{ 6241061SN/A VPEControlReg vpeControl = VPEControl; 6251061SN/A Rt = vpeControl; 6262326SN/A vpeControl.te = 0; 6271061SN/A VPEControl = vpeControl; 6281061SN/A }}); 6291061SN/A 0x1: emt({{ 6302292SN/A VPEControlReg vpeControl = VPEControl; 6312292SN/A Rt = vpeControl; 6321061SN/A vpeControl.te = 1; 6331062SN/A VPEControl = vpeControl; 6341062SN/A }}); 6352292SN/A default:CP0Unimpl::unknown(); 6362292SN/A } 6372292SN/A default:CP0Unimpl::unknown(); 6382292SN/A } 6391061SN/A default:CP0Unimpl::unknown(); 6401061SN/A } 6411061SN/A } 6421060SN/A 0xC: decode POS { 6432292SN/A 0x0: decode SC { 6441060SN/A 0x0: CP0Control::di({{ 6452292SN/A StatusReg status = Status; 6461060SN/A ConfigReg config = Config; 6472292SN/A // Rev 2.0 or beyond? 6482292SN/A if (config.ar >= 1) { 6491060SN/A Rt = status; 6502064SN/A status.ie = 0; 6512333SN/A } else { 6522333SN/A // Enable this else branch once we 6532333SN/A // actually set values for Config on init 6542333SN/A fault = std::make_shared<ReservedInstructionFault>(); 6552333SN/A } 6562333SN/A Status = status; 6577897Shestness@cs.utexas.edu }}); 6587897Shestness@cs.utexas.edu 0x1: CP0Control::ei({{ 6597897Shestness@cs.utexas.edu StatusReg status = Status; 6607897Shestness@cs.utexas.edu ConfigReg config = Config; 6617897Shestness@cs.utexas.edu if (config.ar >= 1) { 6622333SN/A Rt = status; 6632333SN/A status.ie = 1; 6641060SN/A } else { 6652333SN/A fault = std::make_shared<ReservedInstructionFault>(); 6662064SN/A } 6672292SN/A }}); 6682292SN/A default:CP0Unimpl::unknown(); 6692292SN/A } 6702292SN/A } 6712292SN/A default: CP0Unimpl::unknown(); 6722292SN/A } 6732292SN/A format CP0Control { 6742292SN/A 0xA: rdpgpr({{ 6752292SN/A ConfigReg config = Config; 6762292SN/A if (config.ar >= 1) { 6772292SN/A // Rev 2 of the architecture 6782292SN/A panic("Shadow Sets Not Fully Implemented.\n"); 6792292SN/A } else { 6802292SN/A fault = std::make_shared<ReservedInstructionFault>(); 6812292SN/A } 6822292SN/A }}); 6832292SN/A 0xE: wrpgpr({{ 6842292SN/A ConfigReg config = Config; 6852292SN/A if (config.ar >= 1) { 6861060SN/A // Rev 2 of the architecture 6871060SN/A panic("Shadow Sets Not Fully Implemented.\n"); 6882292SN/A } else { 6892292SN/A fault = std::make_shared<ReservedInstructionFault>(); 6902292SN/A } 6911060SN/A }}); 6922292SN/A } 6932292SN/A } 6942292SN/A 6952292SN/A //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 6962292SN/A 0x1: decode FUNCTION { 6972292SN/A format CP0Control { 6982292SN/A 0x18: eret({{ 6992292SN/A StatusReg status = Status; 7002292SN/A ConfigReg config = Config; 7012292SN/A SRSCtlReg srsCtl = SRSCtl; 7022292SN/A DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 7032292SN/A if (status.erl == 1) { 7042292SN/A status.erl = 0; 7052292SN/A NPC = ErrorEPC; 7062292SN/A // Need to adjust NNPC, otherwise things break 7072292SN/A NNPC = ErrorEPC + sizeof(MachInst); 7082292SN/A } else { 7092292SN/A NPC = EPC; 7102292SN/A // Need to adjust NNPC, otherwise things break 7112292SN/A NNPC = EPC + sizeof(MachInst); 7122292SN/A status.exl = 0; 7131060SN/A if (config.ar >=1 && 7141060SN/A srsCtl.hss > 0 && 7152292SN/A status.bev == 0) { 7161060SN/A srsCtl.css = srsCtl.pss; 7171060SN/A //xc->setShadowSet(srsCtl.pss); 7182292SN/A } 7192292SN/A } 7202292SN/A LLFlag = 0; 7212292SN/A Status = status; 7222367SN/A SRSCtl = srsCtl; 7239444SAndreas.Sandberg@ARM.com }}, IsReturn, IsSerializing, IsERET); 7242292SN/A 7252292SN/A 0x1F: deret({{ 7262292SN/A DebugReg debug = Debug; 7272292SN/A if (debug.dm == 1) { 7282326SN/A debug.dm = 1; 7292326SN/A debug.iexi = 0; 7302292SN/A NPC = DEPC; 7312326SN/A } else { 7322326SN/A NPC = NPC; 7332326SN/A // Undefined; 7345327Smengke97@hotmail.com } 7352333SN/A Debug = debug; 7362292SN/A }}, IsReturn, IsSerializing, IsERET); 7372292SN/A } 7381061SN/A format CP0TLB { 7391061SN/A 0x01: tlbr({{ 7401061SN/A MipsISA::PTE *PTEntry = 7411061SN/A dynamic_cast<MipsISA::TLB *>( 7421060SN/A xc->tcBase()->getITBPtr())-> 7431060SN/A getEntry(Index & 0x7FFFFFFF); 7441060SN/A if (PTEntry == NULL) { 7452292SN/A fatal("Invalid PTE Entry received on " 7462292SN/A "a TLBR instruction\n"); 7471060SN/A } 7481060SN/A /* Setup PageMask */ 7491060SN/A // If 1KB pages are not enabled, a read of PageMask 75010333Smitch.hayenga@arm.com // must return 0b00 in bits 12, 11 75110333Smitch.hayenga@arm.com PageMask = (PTEntry->Mask << 11); 75210333Smitch.hayenga@arm.com /* Setup EntryHi */ 75310333Smitch.hayenga@arm.com EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 75410333Smitch.hayenga@arm.com /* Setup Entry Lo0 */ 75510333Smitch.hayenga@arm.com EntryLo0 = ((PTEntry->PFN0 << 6) | 75610333Smitch.hayenga@arm.com (PTEntry->C0 << 3) | 75710333Smitch.hayenga@arm.com (PTEntry->D0 << 2) | 7587944SGiacomo.Gabrielli@arm.com (PTEntry->V0 << 1) | 7597944SGiacomo.Gabrielli@arm.com PTEntry->G); 7602292SN/A /* Setup Entry Lo1 */ 7612292SN/A EntryLo1 = ((PTEntry->PFN1 << 6) | 7622292SN/A (PTEntry->C1 << 3) | 7632292SN/A (PTEntry->D1 << 2) | 7642292SN/A (PTEntry->V1 << 1) | 7652292SN/A PTEntry->G); 7662292SN/A }}); // Need to hook up to TLB 7672292SN/A 76810333Smitch.hayenga@arm.com 0x02: tlbwi({{ 7692292SN/A //Create PTE 7702292SN/A MipsISA::PTE newEntry; 7711060SN/A //Write PTE 77210333Smitch.hayenga@arm.com newEntry.Mask = (Addr)(PageMask >> 11); 7732292SN/A newEntry.VPN = (Addr)(EntryHi >> 11); 7741060SN/A /* PageGrain _ ESP Config3 _ SP */ 7752292SN/A if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) { 7761060SN/A // If 1KB pages are *NOT* enabled, lowest bits of 7772292SN/A // the mask are 0b11 for TLB writes 7781060SN/A newEntry.Mask |= 0x3; 7797897Shestness@cs.utexas.edu // Reset bits 0 and 1 if 1KB pages are not enabled 7807897Shestness@cs.utexas.edu newEntry.VPN &= 0xFFFFFFFC; 7812292SN/A } 7821060SN/A newEntry.asid = (uint8_t)(EntryHi & 0xFF); 7832292SN/A 7842292SN/A newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 7851060SN/A newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 7862292SN/A newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 7872292SN/A newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 7882292SN/A newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 7892292SN/A newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 7902292SN/A newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 7911060SN/A newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 7921060SN/A newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 7932292SN/A /* Now, compute the AddrShiftAmount and OffsetMask - 7941060SN/A TLB optimizations */ 7952292SN/A /* Addr Shift Amount for 1KB or larger pages */ 7962292SN/A if ((newEntry.Mask & 0xFFFF) == 3) { 7972292SN/A newEntry.AddrShiftAmount = 12; 7981060SN/A } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 7991060SN/A newEntry.AddrShiftAmount = 10; 8002326SN/A } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 8019184Sandreas.hansson@arm.com newEntry.AddrShiftAmount = 14; 8026221Snate@binkert.org } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 8031060SN/A newEntry.AddrShiftAmount = 16; 8042326SN/A } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 8052326SN/A newEntry.AddrShiftAmount = 18; 8067897Shestness@cs.utexas.edu } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 8072326SN/A newEntry.AddrShiftAmount = 20; 8082326SN/A } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 8091060SN/A newEntry.AddrShiftAmount = 22; 8101060SN/A } else if ((newEntry.Mask & 0xF000) == 0x3000) { 8111060SN/A newEntry.AddrShiftAmount = 24; 8122348SN/A } else if ((newEntry.Mask & 0xC000) == 0xC000) { 8132348SN/A newEntry.AddrShiftAmount = 26; 8142326SN/A } else if ((newEntry.Mask & 0x30000) == 0x30000) { 8159184Sandreas.hansson@arm.com newEntry.AddrShiftAmount = 28; 8162292SN/A } else { 8172333SN/A fatal("Invalid Mask Pattern Detected!\n"); 8181060SN/A } 8192326SN/A newEntry.OffsetMask = 8202326SN/A (1 << newEntry.AddrShiftAmount) - 1; 8212326SN/A 8222326SN/A auto ptr = dynamic_cast<MipsISA::TLB *>( 8232292SN/A xc->tcBase()->getITBPtr()); 8249184Sandreas.hansson@arm.com Config3Reg config3 = Config3; 8252326SN/A PageGrainReg pageGrain = PageGrain; 8262326SN/A int SP = 0; 8272326SN/A if (bits(config3, config3.sp) == 1 && 8281060SN/A bits(pageGrain, pageGrain.esp) == 1) { 8299180Sandreas.hansson@arm.com SP = 1; 8309180Sandreas.hansson@arm.com } 8311060SN/A ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 8322326SN/A }}); 8339184Sandreas.hansson@arm.com 0x06: tlbwr({{ 8342348SN/A //Create PTE 8352348SN/A MipsISA::PTE newEntry; 8362326SN/A //Write PTE 8372292SN/A newEntry.Mask = (Addr)(PageMask >> 11); 8382292SN/A newEntry.VPN = (Addr)(EntryHi >> 11); 8392326SN/A /* PageGrain _ ESP Config3 _ SP */ 8402292SN/A if (bits(PageGrain, 28) == 0 || 8411060SN/A bits(Config3, 4) == 0) { 8421060SN/A // If 1KB pages are *NOT* enabled, lowest bits of 8437720Sgblack@eecs.umich.edu // the mask are 0b11 for TLB writes 8442292SN/A newEntry.Mask |= 0x3; 8457720Sgblack@eecs.umich.edu // Reset bits 0 and 1 if 1KB pages are not enabled 8462292SN/A newEntry.VPN &= 0xFFFFFFFC; 8471060SN/A } 8482292SN/A newEntry.asid = (uint8_t)(EntryHi & 0xFF); 8491061SN/A 8502292SN/A newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 8512292SN/A newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 8522292SN/A newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 8532292SN/A newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 8542292SN/A newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 8551060SN/A newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 8561060SN/A newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 8572064SN/A newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 8582292SN/A newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 8592064SN/A /* Now, compute the AddrShiftAmount and OffsetMask - 8608471SGiacomo.Gabrielli@arm.com TLB optimizations */ 8619046SAli.Saidi@ARM.com /* Addr Shift Amount for 1KB or larger pages */ 8628471SGiacomo.Gabrielli@arm.com if ((newEntry.Mask & 0xFFFF) == 3){ 8638471SGiacomo.Gabrielli@arm.com newEntry.AddrShiftAmount = 12; 8642292SN/A } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 8652292SN/A newEntry.AddrShiftAmount = 10; 8662292SN/A } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 8672292SN/A newEntry.AddrShiftAmount = 14; 8682301SN/A } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 8692731Sktlim@umich.edu newEntry.AddrShiftAmount = 16; 8702292SN/A } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 8712301SN/A newEntry.AddrShiftAmount = 18; 8722292SN/A } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 8732292SN/A newEntry.AddrShiftAmount = 20; 8742292SN/A } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 8752326SN/A newEntry.AddrShiftAmount = 22; 8762292SN/A } else if ((newEntry.Mask & 0xF000) == 0x3000) { 8772326SN/A newEntry.AddrShiftAmount = 24; 8782326SN/A } else if ((newEntry.Mask & 0xC000) == 0xC000) { 8792292SN/A newEntry.AddrShiftAmount = 26; 8801060SN/A } else if ((newEntry.Mask & 0x30000) == 0x30000) { 8811060SN/A newEntry.AddrShiftAmount = 28; 8821062SN/A } else { 8832326SN/A fatal("Invalid Mask Pattern Detected!\n"); 8842326SN/A } 8852307SN/A newEntry.OffsetMask = 8862348SN/A (1 << newEntry.AddrShiftAmount) - 1; 8878071SAli.Saidi@ARM.com 8888071SAli.Saidi@ARM.com auto ptr = dynamic_cast<MipsISA::TLB *>( 8898071SAli.Saidi@ARM.com xc->tcBase()->getITBPtr()); 89010333Smitch.hayenga@arm.com Config3Reg config3 = Config3; 8912292SN/A PageGrainReg pageGrain = PageGrain; 8922292SN/A int SP = 0; 8932292SN/A if (bits(config3, config3.sp) == 1 && 8942292SN/A bits(pageGrain, pageGrain.esp) == 1) { 8951060SN/A SP = 1; 8961060SN/A } 8971061SN/A ptr->insertAt(newEntry, Random, SP); 8981060SN/A }}); 8991061SN/A 9001060SN/A 0x08: tlbp({{ 9012292SN/A Config3Reg config3 = Config3; 9022292SN/A PageGrainReg pageGrain = PageGrain; 9031062SN/A EntryHiReg entryHi = EntryHi; 9042292SN/A int tlbIndex; 9051060SN/A Addr vpn; 9061061SN/A if (pageGrain.esp == 1 && config3.sp ==1) { 9071060SN/A vpn = EntryHi >> 11; 9086221Snate@binkert.org } else { 9092292SN/A // Mask off lower 2 bits 9104033Sktlim@umich.edu vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 9114033Sktlim@umich.edu } 9121061SN/A tlbIndex = dynamic_cast<MipsISA::TLB *>( 9131060SN/A xc->tcBase()->getITBPtr())-> 9141062SN/A probeEntry(vpn, entryHi.asid); 9151062SN/A // Check TLB for entry matching EntryHi 9161062SN/A if (tlbIndex != -1) { 9172292SN/A Index = tlbIndex; 9181062SN/A } else { 9191060SN/A // else, set Index = 1 << 31 9202292SN/A Index = (1 << 31); 9212292SN/A } 9221061SN/A }}); 9231060SN/A } 9241060SN/A format CP0Unimpl { 9251061SN/A 0x20: wait(); 9261061SN/A } 9276221Snate@binkert.org default: CP0Unimpl::unknown(); 9282292SN/A } 9292292SN/A } 9302292SN/A 9312292SN/A //Table A-13 MIPS32 COP1 Encoding of rs Field 9322292SN/A 0x1: decode RS_MSB { 9332292SN/A 0x0: decode RS_HI { 9342292SN/A 0x0: decode RS_LO { 9352292SN/A format CP1Control { 9362292SN/A 0x0: mfc1 ({{ Rt = Fs_uw; }}); 9372292SN/A 9382292SN/A 0x2: cfc1({{ 9392292SN/A switch (FS) { 9402292SN/A case 0: 9412292SN/A Rt = FIR; 9422292SN/A break; 9432292SN/A case 25: 9442301SN/A Rt = (FCSR & 0xFE000000) >> 24 | 9451684SN/A (FCSR & 0x00800000) >> 23; 9461684SN/A break; 9472301SN/A case 26: 9482301SN/A Rt = (FCSR & 0x0003F07C); 9497897Shestness@cs.utexas.edu break; 9507897Shestness@cs.utexas.edu case 28: 9517897Shestness@cs.utexas.edu Rt = (FCSR & 0x00000F80) | 9527897Shestness@cs.utexas.edu (FCSR & 0x01000000) >> 21 | 9537897Shestness@cs.utexas.edu (FCSR & 0x00000003); 9547897Shestness@cs.utexas.edu break; 9557897Shestness@cs.utexas.edu case 31: 9562292SN/A Rt = FCSR; 9572292SN/A break; 9582292SN/A default: 9591684SN/A warn("FP Control Value (%d) Not Valid"); 9601684SN/A } 9612292SN/A }}); 9622326SN/A 9632326SN/A 0x3: mfhc1({{ Rt = Fs_ud<63:32>; }}); 9642326SN/A 9652326SN/A 0x4: mtc1({{ Fs_uw = Rt; }}); 9661684SN/A 9672292SN/A 0x6: ctc1({{ 9682292SN/A switch (FS) { 9692292SN/A case 25: 9702292SN/A FCSR = (Rt<7:1> << 25) | // move 31-25 9712292SN/A (FCSR & 0x01000000) | // bit 24 9721684SN/A (FCSR & 0x004FFFFF); // bit 22-0 9731684SN/A break; 9741684SN/A case 26: 9751684SN/A FCSR = (FCSR & 0xFFFC0000) | // move 31-18 9761684SN/A Rt<17:12> << 12 | // bit 17-12 9771684SN/A (FCSR & 0x00000F80) << 7 | // bit 11-7 9781684SN/A Rt<6:2> << 2 | // bit 6-2 9791684SN/A (FCSR & 0x00000002); // bit 1-0 9801684SN/A break; 9811684SN/A case 28: 9821684SN/A FCSR = (FCSR & 0xFE000000) | // move 31-25 9831684SN/A Rt<2:2> << 24 | // bit 24 9841684SN/A (FCSR & 0x00FFF000) << 23 | // bit 23-12 9857599Sminkyu.jeong@arm.com Rt<11:7> << 7 | // bit 24 9867599Sminkyu.jeong@arm.com (FCSR & 0x000007E) | 9871684SN/A Rt<1:0>; // bit 22-0 9881684SN/A break; 9891684SN/A case 31: 9902292SN/A FCSR = Rt; 9911684SN/A break; 9921684SN/A 9932326SN/A default: 9942326SN/A panic("FP Control Value (%d) " 9952326SN/A "Not Available. Ignoring Access " 9961684SN/A "to Floating Control Status " 9972326SN/A "Register", FS); 9987599Sminkyu.jeong@arm.com } 9997720Sgblack@eecs.umich.edu }}); 10001684SN/A 10011684SN/A 0x7: mthc1({{ 10022326SN/A uint64_t fs_hi = Rt; 10032326SN/A uint64_t fs_lo = Fs_ud & 0x0FFFFFFFF; 10042326SN/A Fs_ud = (fs_hi << 32) | fs_lo; 10052326SN/A }}); 10061684SN/A 10072326SN/A } 10081684SN/A format CP1Unimpl { 10092326SN/A 0x1: dmfc1(); 10101684SN/A 0x5: dmtc1(); 10112301SN/A } 10121684SN/A } 10131684SN/A 10142326SN/A 0x1: decode RS_LO { 10152326SN/A 0x0: decode ND { 10162326SN/A format Branch { 10172326SN/A 0x0: decode TF { 10181684SN/A 0x0: bc1f({{ 10191684SN/A cond = getCondCode(FCSR, BRANCH_CC) == 0; 10201684SN/A }}); 10211684SN/A 0x1: bc1t({{ 10222301SN/A cond = getCondCode(FCSR, BRANCH_CC) == 1; 10232064SN/A }}); 10242064SN/A } 10252064SN/A 0x1: decode TF { 10262064SN/A 0x0: bc1fl({{ 10272292SN/A cond = getCondCode(FCSR, BRANCH_CC) == 0; 10282064SN/A }}, Likely); 10292292SN/A 0x1: bc1tl({{ 10302292SN/A cond = getCondCode(FCSR, BRANCH_CC) == 1; 10312292SN/A }}, Likely); 10322292SN/A } 10332326SN/A } 10342326SN/A } 10352326SN/A format CP1Unimpl { 10362326SN/A 0x1: bc1any2(); 10372326SN/A 0x2: bc1any4(); 10382326SN/A default: unknown(); 10392326SN/A } 10402326SN/A } 10412326SN/A } 10422326SN/A 10432292SN/A 0x1: decode RS_HI { 10447720Sgblack@eecs.umich.edu 0x2: decode RS_LO { 10457720Sgblack@eecs.umich.edu //Table A-14 MIPS32 COP1 Encoding of Function Field When 10462064SN/A //rs=S (( single-precision floating point)) 10472064SN/A 0x0: decode FUNCTION_HI { 10482064SN/A 0x0: decode FUNCTION_LO { 10492064SN/A format FloatOp { 10502292SN/A 0x0: add_s({{ Fd_sf = Fs_sf + Ft_sf; }}); 10512064SN/A 0x1: sub_s({{ Fd_sf = Fs_sf - Ft_sf; }}); 10524033Sktlim@umich.edu 0x2: mul_s({{ Fd_sf = Fs_sf * Ft_sf; }}); 10537944SGiacomo.Gabrielli@arm.com 0x3: div_s({{ Fd_sf = Fs_sf / Ft_sf; }}); 10547944SGiacomo.Gabrielli@arm.com 0x4: sqrt_s({{ Fd_sf = sqrt(Fs_sf); }}); 10559046SAli.Saidi@ARM.com 0x5: abs_s({{ Fd_sf = fabs(Fs_sf); }}); 10569046SAli.Saidi@ARM.com 0x7: neg_s({{ Fd_sf = -Fs_sf; }}); 10577944SGiacomo.Gabrielli@arm.com } 10584033Sktlim@umich.edu 0x6: BasicOp::mov_s({{ Fd_sf = Fs_sf; }}); 10592292SN/A } 10602064SN/A 0x1: decode FUNCTION_LO { 10612064SN/A format FloatConvertOp { 10622064SN/A 0x0: round_l_s({{ val = Fs_sf; }}, 10632064SN/A ToLong, Round); 10642292SN/A 0x1: trunc_l_s({{ val = Fs_sf; }}, 10652064SN/A ToLong, Trunc); 106610333Smitch.hayenga@arm.com 0x2: ceil_l_s({{ val = Fs_sf;}}, 10672292SN/A ToLong, Ceil); 10682292SN/A 0x3: floor_l_s({{ val = Fs_sf; }}, 10692292SN/A ToLong, Floor); 10702292SN/A 0x4: round_w_s({{ val = Fs_sf; }}, 10712292SN/A ToWord, Round); 10722292SN/A 0x5: trunc_w_s({{ val = Fs_sf; }}, 10736221Snate@binkert.org ToWord, Trunc); 10742292SN/A 0x6: ceil_w_s({{ val = Fs_sf; }}, 10757720Sgblack@eecs.umich.edu ToWord, Ceil); 10767720Sgblack@eecs.umich.edu 0x7: floor_w_s({{ val = Fs_sf; }}, 10772292SN/A ToWord, Floor); 10782292SN/A } 10792292SN/A } 10809046SAli.Saidi@ARM.com 10812292SN/A 0x2: decode FUNCTION_LO { 10822292SN/A 0x1: decode MOVCF { 10832292SN/A format BasicOp { 10841684SN/A 0x0: movf_s({{ 10851684SN/A Fd = (getCondCode(FCSR,CC) == 0) ? 10861684SN/A Fs : Fd; 10871684SN/A }}); 10887944SGiacomo.Gabrielli@arm.com 0x1: movt_s({{ 10897944SGiacomo.Gabrielli@arm.com Fd = (getCondCode(FCSR,CC) == 1) ? 10907944SGiacomo.Gabrielli@arm.com Fs : Fd; 10917944SGiacomo.Gabrielli@arm.com }}); 10927944SGiacomo.Gabrielli@arm.com } 10937944SGiacomo.Gabrielli@arm.com } 109410333Smitch.hayenga@arm.com 109510333Smitch.hayenga@arm.com format BasicOp { 109610333Smitch.hayenga@arm.com 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 109710333Smitch.hayenga@arm.com 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 109810333Smitch.hayenga@arm.com } 109910333Smitch.hayenga@arm.com 110010333Smitch.hayenga@arm.com format FloatOp { 110110333Smitch.hayenga@arm.com 0x5: recip_s({{ Fd = 1 / Fs; }}); 110210333Smitch.hayenga@arm.com 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); 110310333Smitch.hayenga@arm.com } 110410333Smitch.hayenga@arm.com format CP1Unimpl { 110510333Smitch.hayenga@arm.com default: unknown(); 110610333Smitch.hayenga@arm.com } 110710333Smitch.hayenga@arm.com } 110810333Smitch.hayenga@arm.com 0x3: CP1Unimpl::unknown(); 110910333Smitch.hayenga@arm.com 111010333Smitch.hayenga@arm.com 0x4: decode FUNCTION_LO { 111110333Smitch.hayenga@arm.com format FloatConvertOp { 111210333Smitch.hayenga@arm.com 0x1: cvt_d_s({{ val = Fs_sf; }}, ToDouble); 111310333Smitch.hayenga@arm.com 0x4: cvt_w_s({{ val = Fs_sf; }}, ToWord); 111410333Smitch.hayenga@arm.com 0x5: cvt_l_s({{ val = Fs_sf; }}, ToLong); 11157944SGiacomo.Gabrielli@arm.com } 11167944SGiacomo.Gabrielli@arm.com 11177944SGiacomo.Gabrielli@arm.com 0x6: FloatOp::cvt_ps_s({{ 11187944SGiacomo.Gabrielli@arm.com Fd_ud = (uint64_t)Fs_uw << 32 | 11197944SGiacomo.Gabrielli@arm.com (uint64_t)Ft_uw; 11209046SAli.Saidi@ARM.com }}); 112110333Smitch.hayenga@arm.com format CP1Unimpl { 11227944SGiacomo.Gabrielli@arm.com default: unknown(); 112310333Smitch.hayenga@arm.com } 11247944SGiacomo.Gabrielli@arm.com } 11257944SGiacomo.Gabrielli@arm.com 0x5: CP1Unimpl::unknown(); 112610333Smitch.hayenga@arm.com 112710333Smitch.hayenga@arm.com 0x6: decode FUNCTION_LO { 112810333Smitch.hayenga@arm.com format FloatCompareOp { 112910333Smitch.hayenga@arm.com 0x0: c_f_s({{ cond = 0; }}, 113010333Smitch.hayenga@arm.com SinglePrecision, UnorderedFalse); 113110333Smitch.hayenga@arm.com 0x1: c_un_s({{ cond = 0; }}, 113210333Smitch.hayenga@arm.com SinglePrecision, UnorderedTrue); 113310333Smitch.hayenga@arm.com 0x2: c_eq_s({{ cond = (Fs_sf == Ft_sf); }}, 113410333Smitch.hayenga@arm.com UnorderedFalse); 113510333Smitch.hayenga@arm.com 0x3: c_ueq_s({{ cond = (Fs_sf == Ft_sf); }}, 113610333Smitch.hayenga@arm.com UnorderedTrue); 113710333Smitch.hayenga@arm.com 0x4: c_olt_s({{ cond = (Fs_sf < Ft_sf); }}, 113810333Smitch.hayenga@arm.com UnorderedFalse); 113910333Smitch.hayenga@arm.com 0x5: c_ult_s({{ cond = (Fs_sf < Ft_sf); }}, 11407944SGiacomo.Gabrielli@arm.com UnorderedTrue); 11417944SGiacomo.Gabrielli@arm.com 0x6: c_ole_s({{ cond = (Fs_sf <= Ft_sf); }}, 11427944SGiacomo.Gabrielli@arm.com UnorderedFalse); 11437944SGiacomo.Gabrielli@arm.com 0x7: c_ule_s({{ cond = (Fs_sf <= Ft_sf); }}, 11441061SN/A UnorderedTrue); 11451061SN/A } 11461061SN/A } 11477897Shestness@cs.utexas.edu 11482292SN/A 0x7: decode FUNCTION_LO { 11491061SN/A format FloatCompareOp { 11501061SN/A 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 11511061SN/A UnorderedFalse, QnanException); 11521060SN/A 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 11536221Snate@binkert.org UnorderedTrue, QnanException); 11541060SN/A 0x2: c_seq_s({{ cond = (Fs_sf == Ft_sf); }}, 11552292SN/A UnorderedFalse, QnanException); 11562292SN/A 0x3: c_ngl_s({{ cond = (Fs_sf == Ft_sf); }}, 11571060SN/A UnorderedTrue, QnanException); 11581060SN/A 0x4: c_lt_s({{ cond = (Fs_sf < Ft_sf); }}, 11591060SN/A UnorderedFalse, QnanException); 11602292SN/A 0x5: c_nge_s({{ cond = (Fs_sf < Ft_sf); }}, 11611060SN/A UnorderedTrue, QnanException); 11621681SN/A 0x6: c_le_s({{ cond = (Fs_sf <= Ft_sf); }}, 11632292SN/A UnorderedFalse, QnanException); 11642292SN/A 0x7: c_ngt_s({{ cond = (Fs_sf <= Ft_sf); }}, 11651681SN/A UnorderedTrue, QnanException); 11661061SN/A } 11671061SN/A } 11682292SN/A } 11691060SN/A 11701060SN/A //Table A-15 MIPS32 COP1 Encoding of Function Field When 11711061SN/A //rs=D 11721061SN/A 0x1: decode FUNCTION_HI { 11736221Snate@binkert.org 0x0: decode FUNCTION_LO { 11741061SN/A format FloatOp { 11752326SN/A 0x0: add_d({{ Fd_df = Fs_df + Ft_df; }}); 11762326SN/A 0x1: sub_d({{ Fd_df = Fs_df - Ft_df; }}); 11772326SN/A 0x2: mul_d({{ Fd_df = Fs_df * Ft_df; }}); 11781061SN/A 0x3: div_d({{ Fd_df = Fs_df / Ft_df; }}); 11792292SN/A 0x4: sqrt_d({{ Fd_df = sqrt(Fs_df); }}); 11802292SN/A 0x5: abs_d({{ Fd_df = fabs(Fs_df); }}); 11811061SN/A 0x7: neg_d({{ Fd_df = -1 * Fs_df; }}); 11821061SN/A } 11831061SN/A 0x6: BasicOp::mov_d({{ Fd_df = Fs_df; }}); 11842326SN/A } 11852326SN/A 11862292SN/A 0x1: decode FUNCTION_LO { 11872326SN/A format FloatConvertOp { 11887897Shestness@cs.utexas.edu 0x0: round_l_d({{ val = Fs_df; }}, 11891061SN/A ToLong, Round); 11901061SN/A 0x1: trunc_l_d({{ val = Fs_df; }}, 11911061SN/A ToLong, Trunc); 11922292SN/A 0x2: ceil_l_d({{ val = Fs_df; }}, 11932292SN/A ToLong, Ceil); 11942326SN/A 0x3: floor_l_d({{ val = Fs_df; }}, 11952292SN/A ToLong, Floor); 11962292SN/A 0x4: round_w_d({{ val = Fs_df; }}, 11972292SN/A ToWord, Round); 11982292SN/A 0x5: trunc_w_d({{ val = Fs_df; }}, 11992292SN/A ToWord, Trunc); 12009046SAli.Saidi@ARM.com 0x6: ceil_w_d({{ val = Fs_df; }}, 12011062SN/A ToWord, Ceil); 12027720Sgblack@eecs.umich.edu 0x7: floor_w_d({{ val = Fs_df; }}, 12037720Sgblack@eecs.umich.edu ToWord, Floor); 12042367SN/A } 120510032SGiacomo.Gabrielli@arm.com } 120610032SGiacomo.Gabrielli@arm.com 120710032SGiacomo.Gabrielli@arm.com 0x2: decode FUNCTION_LO { 120810032SGiacomo.Gabrielli@arm.com 0x1: decode MOVCF { 120910032SGiacomo.Gabrielli@arm.com format BasicOp { 12101061SN/A 0x0: movf_d({{ 121110032SGiacomo.Gabrielli@arm.com Fd_df = (getCondCode(FCSR,CC) == 0) ? 121210032SGiacomo.Gabrielli@arm.com Fs_df : Fd_df; 121310032SGiacomo.Gabrielli@arm.com }}); 121410032SGiacomo.Gabrielli@arm.com 0x1: movt_d({{ 121510032SGiacomo.Gabrielli@arm.com Fd_df = (getCondCode(FCSR,CC) == 1) ? 12161061SN/A Fs_df : Fd_df; 12171061SN/A }}); 12181681SN/A } 12191061SN/A } 12201061SN/A 12211061SN/A format BasicOp { 12221061SN/A 0x2: movz_d({{ 12231061SN/A Fd_df = (Rt == 0) ? Fs_df : Fd_df; 12242326SN/A }}); 12252326SN/A 0x3: movn_d({{ 12262326SN/A Fd_df = (Rt != 0) ? Fs_df : Fd_df; 12272326SN/A }}); 12282326SN/A } 12292326SN/A 12302326SN/A format FloatOp { 12312326SN/A 0x5: recip_d({{ Fd_df = 1 / Fs_df; }}); 12322292SN/A 0x6: rsqrt_d({{ Fd_df = 1 / sqrt(Fs_df); }}); 12331061SN/A } 12341061SN/A format CP1Unimpl { 12352326SN/A default: unknown(); 12361061SN/A } 12371062SN/A 12382292SN/A } 12391062SN/A 0x4: decode FUNCTION_LO { 12401061SN/A format FloatConvertOp { 12414033Sktlim@umich.edu 0x0: cvt_s_d({{ val = Fs_df; }}, ToSingle); 12424033Sktlim@umich.edu 0x4: cvt_w_d({{ val = Fs_df; }}, ToWord); 12432292SN/A 0x5: cvt_l_d({{ val = Fs_df; }}, ToLong); 12442292SN/A } 12458275SAli.Saidi@ARM.com default: CP1Unimpl::unknown(); 124610017Sandreas.hansson@arm.com } 124710017Sandreas.hansson@arm.com 124810017Sandreas.hansson@arm.com 0x6: decode FUNCTION_LO { 12494033Sktlim@umich.edu format FloatCompareOp { 125010017Sandreas.hansson@arm.com 0x0: c_f_d({{ cond = 0; }}, 125110017Sandreas.hansson@arm.com DoublePrecision, UnorderedFalse); 125210017Sandreas.hansson@arm.com 0x1: c_un_d({{ cond = 0; }}, 125310017Sandreas.hansson@arm.com DoublePrecision, UnorderedTrue); 125410017Sandreas.hansson@arm.com 0x2: c_eq_d({{ cond = (Fs_df == Ft_df); }}, 12554033Sktlim@umich.edu UnorderedFalse); 12561062SN/A 0x3: c_ueq_d({{ cond = (Fs_df == Ft_df); }}, 12574033Sktlim@umich.edu UnorderedTrue); 12581681SN/A 0x4: c_olt_d({{ cond = (Fs_df < Ft_df); }}, 12594033Sktlim@umich.edu UnorderedFalse); 12601062SN/A 0x5: c_ult_d({{ cond = (Fs_df < Ft_df); }}, 12614033Sktlim@umich.edu UnorderedTrue); 12624033Sktlim@umich.edu 0x6: c_ole_d({{ cond = (Fs_df <= Ft_df); }}, 12631061SN/A UnorderedFalse); 12641061SN/A 0x7: c_ule_d({{ cond = (Fs_df <= Ft_df); }}, 12651061SN/A UnorderedTrue); 12661061SN/A } 12671061SN/A } 12681061SN/A 12691061SN/A 0x7: decode FUNCTION_LO { 12702292SN/A format FloatCompareOp { 12712292SN/A 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 12721681SN/A UnorderedFalse, QnanException); 12731681SN/A 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 12742731Sktlim@umich.edu UnorderedTrue, QnanException); 12752292SN/A 0x2: c_seq_d({{ cond = (Fs_df == Ft_df); }}, 12762292SN/A UnorderedFalse, QnanException); 12772292SN/A 0x3: c_ngl_d({{ cond = (Fs_df == Ft_df); }}, 12781681SN/A UnorderedTrue, QnanException); 12791681SN/A 0x4: c_lt_d({{ cond = (Fs_df < Ft_df); }}, 12801061SN/A UnorderedFalse, QnanException); 12811061SN/A 0x5: c_nge_d({{ cond = (Fs_df < Ft_df); }}, 12822326SN/A UnorderedTrue, QnanException); 12831062SN/A 0x6: c_le_d({{ cond = (Fs_df <= Ft_df); }}, 12841061SN/A UnorderedFalse, QnanException); 12851060SN/A 0x7: c_ngt_d({{ cond = (Fs_df <= Ft_df); }}, 12861060SN/A UnorderedTrue, QnanException); 12871061SN/A } 12881060SN/A } 12891061SN/A default: CP1Unimpl::unknown(); 12901060SN/A } 12911060SN/A 0x2: CP1Unimpl::unknown(); 12921060SN/A 0x3: CP1Unimpl::unknown(); 12931060SN/A 0x7: CP1Unimpl::unknown(); 12941060SN/A 12951060SN/A //Table A-16 MIPS32 COP1 Encoding of Function 12961060SN/A //Field When rs=W 12971060SN/A 0x4: decode FUNCTION { 12981060SN/A format FloatConvertOp { 12991060SN/A 0x20: cvt_s_w({{ val = Fs_sw; }}, ToSingle); 13001060SN/A 0x21: cvt_d_w({{ val = Fs_sw; }}, ToDouble); 13011060SN/A 0x26: CP1Unimpl::cvt_ps_w(); 13021060SN/A } 13031060SN/A default: CP1Unimpl::unknown(); 13041060SN/A } 13051060SN/A 13061060SN/A //Table A-16 MIPS32 COP1 Encoding of Function Field 13071060SN/A //When rs=L1 13081061SN/A //Note: "1. Format type L is legal only if 64-bit 13091061SN/A //floating point operations are enabled." 131010231Ssteve.reinhardt@amd.com 0x5: decode FUNCTION { 13117720Sgblack@eecs.umich.edu format FloatConvertOp { 13121060SN/A 0x20: cvt_s_l({{ val = Fs_sd; }}, ToSingle); 13137720Sgblack@eecs.umich.edu 0x21: cvt_d_l({{ val = Fs_sd; }}, ToDouble); 13141060SN/A 0x26: CP1Unimpl::cvt_ps_l(); 13152326SN/A } 13161060SN/A default: CP1Unimpl::unknown(); 13171060SN/A } 13181060SN/A 13191060SN/A //Table A-17 MIPS64 COP1 Encoding of Function Field 13201060SN/A //When rs=PS1 13217720Sgblack@eecs.umich.edu //Note: "1. Format type PS is legal only if 64-bit 13221060SN/A //floating point operations are enabled. " 13237720Sgblack@eecs.umich.edu 0x6: decode FUNCTION_HI { 13241060SN/A 0x0: decode FUNCTION_LO { 13252326SN/A format Float64Op { 13261060SN/A 0x0: add_ps({{ 13271060SN/A Fd1_sf = Fs1_sf + Ft2_sf; 13281060SN/A Fd2_sf = Fs2_sf + Ft2_sf; 13291060SN/A }}); 13301060SN/A 0x1: sub_ps({{ 13311060SN/A Fd1_sf = Fs1_sf - Ft2_sf; 13321060SN/A Fd2_sf = Fs2_sf - Ft2_sf; 13331061SN/A }}); 13341060SN/A 0x2: mul_ps({{ 13352326SN/A Fd1_sf = Fs1_sf * Ft2_sf; 13361060SN/A Fd2_sf = Fs2_sf * Ft2_sf; 13372326SN/A }}); 13382326SN/A 0x5: abs_ps({{ 13392326SN/A Fd1_sf = fabs(Fs1_sf); 13402326SN/A Fd2_sf = fabs(Fs2_sf); 13411060SN/A }}); 13421060SN/A 0x6: mov_ps({{ 13431060SN/A Fd1_sf = Fs1_sf; 13441060SN/A Fd2_sf = Fs2_sf; 13451060SN/A }}); 13461060SN/A 0x7: neg_ps({{ 13471061SN/A Fd1_sf = -(Fs1_sf); 13481061SN/A Fd2_sf = -(Fs2_sf); 13491061SN/A }}); 13501061SN/A default: CP1Unimpl::unknown(); 13511061SN/A } 13521061SN/A } 13531061SN/A 0x1: CP1Unimpl::unknown(); 13541061SN/A 0x2: decode FUNCTION_LO { 13551060SN/A 0x1: decode MOVCF { 13561060SN/A format Float64Op { 13572326SN/A 0x0: movf_ps({{ 13582326SN/A Fd1 = (getCondCode(FCSR, CC) == 0) ? 13592292SN/A Fs1 : Fd1; 13602064SN/A Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 13611062SN/A Fs2 : Fd2; 13622326SN/A }}); 13631062SN/A 0x1: movt_ps({{ 13641060SN/A Fd2 = (getCondCode(FCSR, CC) == 1) ? 13651060SN/A Fs1 : Fd1; 13661060SN/A Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 13671060SN/A Fs2 : Fd2; 13681060SN/A }}); 13691061SN/A } 13701060SN/A } 13711061SN/A 13721060SN/A format Float64Op { 13732326SN/A 0x2: movz_ps({{ 13741060SN/A Fd1 = (getCondCode(FCSR, CC) == 0) ? 13751060SN/A Fs1 : Fd1; 13761061SN/A Fd2 = (getCondCode(FCSR, CC) == 0) ? 13771060SN/A Fs2 : Fd2; 13782292SN/A }}); 13791061SN/A 0x3: movn_ps({{ 13802292SN/A Fd1 = (getCondCode(FCSR, CC) == 1) ? 13811061SN/A Fs1 : Fd1; 13821062SN/A Fd2 = (getCondCode(FCSR, CC) == 1) ? 13831062SN/A Fs2 : Fd2; 13842292SN/A }}); 13851062SN/A } 13862292SN/A default: CP1Unimpl::unknown(); 13872292SN/A } 13881062SN/A 0x3: CP1Unimpl::unknown(); 13892292SN/A 0x4: decode FUNCTION_LO { 13901061SN/A 0x0: FloatOp::cvt_s_pu({{ Fd_sf = Fs2_sf; }}); 13912292SN/A default: CP1Unimpl::unknown(); 13927720Sgblack@eecs.umich.edu } 13937720Sgblack@eecs.umich.edu 13941061SN/A 0x5: decode FUNCTION_LO { 13952292SN/A 0x0: FloatOp::cvt_s_pl({{ Fd_sf = Fs1_sf; }}); 13961061SN/A format Float64Op { 13972326SN/A 0x4: pll({{ 13982326SN/A Fd_ud = (uint64_t)Fs1_uw << 32 | Ft1_uw; 13992326SN/A }}); 14002326SN/A 0x5: plu({{ 14012326SN/A Fd_ud = (uint64_t)Fs1_uw << 32 | Ft2_uw; 14022326SN/A }}); 14032326SN/A 0x6: pul({{ 14042326SN/A Fd_ud = (uint64_t)Fs2_uw << 32 | Ft1_uw; 14051060SN/A }}); 14061060SN/A 0x7: puu({{ 14071060SN/A Fd_ud = (uint64_t)Fs2_uw << 32 | Ft2_uw; 14081060SN/A }}); 14091061SN/A } 14101061SN/A default: CP1Unimpl::unknown(); 14111061SN/A } 14121061SN/A 14132698Sktlim@umich.edu 0x6: decode FUNCTION_LO { 14142292SN/A format FloatPSCompareOp { 14152292SN/A 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 14162292SN/A UnorderedFalse); 14172698Sktlim@umich.edu 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 14181061SN/A UnorderedTrue); 14191061SN/A 0x2: c_eq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 14206221Snate@binkert.org {{ cond2 = (Fs2_sf == Ft2_sf); }}, 14216221Snate@binkert.org UnorderedFalse); 14221681SN/A 0x3: c_ueq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 14236221Snate@binkert.org {{ cond2 = (Fs2_sf == Ft2_sf); }}, 14242292SN/A UnorderedTrue); 14252292SN/A 0x4: c_olt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 14262292SN/A {{ cond2 = (Fs2_sf < Ft2_sf); }}, 14272292SN/A UnorderedFalse); 14282292SN/A 0x5: c_ult_ps({{ cond1 = (Fs_sf < Ft_sf); }}, 14292292SN/A {{ cond2 = (Fs2_sf < Ft2_sf); }}, 14302292SN/A UnorderedTrue); 14312292SN/A 0x6: c_ole_ps({{ cond1 = (Fs_sf <= Ft_sf); }}, 14322292SN/A {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 14332292SN/A UnorderedFalse); 14342292SN/A 0x7: c_ule_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 14352292SN/A {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 14361061SN/A UnorderedTrue); 14371061SN/A } 14381061SN/A } 14391061SN/A 14402292SN/A 0x7: decode FUNCTION_LO { 14412292SN/A format FloatPSCompareOp { 14422292SN/A 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 14431681SN/A UnorderedFalse, QnanException); 14441681SN/A 0x1: c_ngle_ps({{ cond1 = 0; }}, 14451681SN/A {{ cond2 = 0; }}, 14461681SN/A UnorderedTrue, QnanException); 14471061SN/A 0x2: c_seq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 14481061SN/A {{ cond2 = (Fs2_sf == Ft2_sf); }}, 14492292SN/A UnorderedFalse, QnanException); 14502292SN/A 0x3: c_ngl_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 14511061SN/A {{ cond2 = (Fs2_sf == Ft2_sf); }}, 14522292SN/A UnorderedTrue, QnanException); 14532292SN/A 0x4: c_lt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 14541061SN/A {{ cond2 = (Fs2_sf < Ft2_sf); }}, 14551061SN/A UnorderedFalse, QnanException); 14561061SN/A 0x5: c_nge_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 14572292SN/A {{ cond2 = (Fs2_sf < Ft2_sf); }}, 14582292SN/A UnorderedTrue, QnanException); 14591061SN/A 0x6: c_le_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 14601061SN/A {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 14611061SN/A UnorderedFalse, QnanException); 14622292SN/A 0x7: c_ngt_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 14637720Sgblack@eecs.umich.edu {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 14642292SN/A UnorderedTrue, QnanException); 14651061SN/A } 14661061SN/A } 14671061SN/A } 14681061SN/A } 14691061SN/A default: CP1Unimpl::unknown(); 14702292SN/A } 14712292SN/A } 14722292SN/A 14732292SN/A //Table A-19 MIPS32 COP2 Encoding of rs Field 14742292SN/A 0x2: decode RS_MSB { 14752292SN/A format CP2Unimpl { 14762292SN/A 0x0: decode RS_HI { 14772292SN/A 0x0: decode RS_LO { 14782292SN/A 0x0: mfc2(); 14792292SN/A 0x2: cfc2(); 14802292SN/A 0x3: mfhc2(); 14812292SN/A 0x4: mtc2(); 14822292SN/A 0x6: ctc2(); 14832292SN/A 0x7: mftc2(); 14842292SN/A default: unknown(); 14851061SN/A } 14862292SN/A 14872292SN/A 0x1: decode ND { 14882292SN/A 0x0: decode TF { 14892292SN/A 0x0: bc2f(); 14902292SN/A 0x1: bc2t(); 14912292SN/A default: unknown(); 14926221Snate@binkert.org } 14932292SN/A 14942292SN/A 0x1: decode TF { 14956221Snate@binkert.org 0x0: bc2fl(); 14962292SN/A 0x1: bc2tl(); 14976221Snate@binkert.org default: unknown(); 14986221Snate@binkert.org } 14992292SN/A default: unknown(); 15002292SN/A 15012292SN/A } 15022292SN/A default: unknown(); 15032292SN/A } 15049046SAli.Saidi@ARM.com default: unknown(); 15052326SN/A } 15062326SN/A } 15072292SN/A 15082292SN/A //Table A-20 MIPS64 COP1X Encoding of Function Field 1 15092292SN/A //Note: "COP1X instructions are legal only if 64-bit floating point 15102292SN/A //operations are enabled." 15112292SN/A 0x3: decode FUNCTION_HI { 15127720Sgblack@eecs.umich.edu 0x0: decode FUNCTION_LO { 15132292SN/A format LoadIndexedMemory { 15147720Sgblack@eecs.umich.edu 0x0: lwxc1({{ Fd_uw = Mem; }}); 15152292SN/A 0x1: ldxc1({{ Fd_ud = Mem_ud; }}); 15162292SN/A 0x5: luxc1({{ Fd_ud = Mem_ud; }}, 15172292SN/A {{ EA = (Rs + Rt) & ~7; }}); 15182292SN/A } 15192292SN/A } 15202292SN/A 15219046SAli.Saidi@ARM.com 0x1: decode FUNCTION_LO { 15222292SN/A format StoreIndexedMemory { 15232292SN/A 0x0: swxc1({{ Mem = Fs_uw; }}); 15242292SN/A 0x1: sdxc1({{ Mem_ud = Fs_ud; }}); 15252292SN/A 0x5: suxc1({{ Mem_ud = Fs_ud; }}, 15262292SN/A {{ EA = (Rs + Rt) & ~7; }}); 15272292SN/A } 15282292SN/A 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 15292292SN/A } 15302348SN/A 15312348SN/A 0x3: decode FUNCTION_LO { 15322348SN/A 0x6: Float64Op::alnv_ps({{ 15332348SN/A if (Rs<2:0> == 0) { 15342348SN/A Fd_ud = Fs_ud; 15352348SN/A } else if (Rs<2:0> == 4) { 15362348SN/A if (GuestByteOrder == BigEndianByteOrder) 15372348SN/A Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>; 15382348SN/A else 15392348SN/A Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>; 15402348SN/A } else { 15412348SN/A Fd_ud = Fd_ud; 15422348SN/A } 15432348SN/A }}); 15442348SN/A } 15452348SN/A 15469046SAli.Saidi@ARM.com format FloatAccOp { 15472348SN/A 0x4: decode FUNCTION_LO { 15482348SN/A 0x0: madd_s({{ Fd_sf = (Fs_sf * Ft_sf) + Fr_sf; }}); 15492348SN/A 0x1: madd_d({{ Fd_df = (Fs_df * Ft_df) + Fr_df; }}); 15502348SN/A 0x6: madd_ps({{ 15512348SN/A Fd1_sf = (Fs1_df * Ft1_df) + Fr1_df; 15522348SN/A Fd2_sf = (Fs2_df * Ft2_df) + Fr2_df; 15532348SN/A }}); 15547720Sgblack@eecs.umich.edu } 15552348SN/A 15567720Sgblack@eecs.umich.edu 0x5: decode FUNCTION_LO { 15572348SN/A 0x0: msub_s({{ Fd_sf = (Fs_sf * Ft_sf) - Fr_sf; }}); 15582348SN/A 0x1: msub_d({{ Fd_df = (Fs_df * Ft_df) - Fr_df; }}); 15592348SN/A 0x6: msub_ps({{ 15602348SN/A Fd1_sf = (Fs1_df * Ft1_df) - Fr1_df; 15612348SN/A Fd2_sf = (Fs2_df * Ft2_df) - Fr2_df; 15622348SN/A }}); 15639046SAli.Saidi@ARM.com } 15642348SN/A 15652348SN/A 0x6: decode FUNCTION_LO { 15662348SN/A 0x0: nmadd_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) - Fr_sf; }}); 15672348SN/A 0x1: nmadd_d({{ Fd_df = (-1 * Fs_df * Ft_df) - Fr_df; }}); 15682348SN/A 0x6: nmadd_ps({{ 15692348SN/A Fd1_sf = -((Fs1_df * Ft1_df) + Fr1_df); 15702348SN/A Fd2_sf = -((Fs2_df * Ft2_df) + Fr2_df); 15712292SN/A }}); 15729944Smatt.horsnell@ARM.com } 15739944Smatt.horsnell@ARM.com 1574 0x7: decode FUNCTION_LO { 1575 0x0: nmsub_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) + Fr_sf; }}); 1576 0x1: nmsub_d({{ Fd_df = (-1 * Fs_df * Ft_df) + Fr_df; }}); 1577 0x6: nmsub_ps({{ 1578 Fd1_sf = -((Fs1_df * Ft1_df) - Fr1_df); 1579 Fd2_sf = -((Fs2_df * Ft2_df) - Fr2_df); 1580 }}); 1581 } 1582 } 1583 } 1584 1585 format Branch { 1586 0x4: beql({{ cond = (Rs_sw == Rt_sw); }}, Likely); 1587 0x5: bnel({{ cond = (Rs_sw != Rt_sw); }}, Likely); 1588 0x6: blezl({{ cond = (Rs_sw <= 0); }}, Likely); 1589 0x7: bgtzl({{ cond = (Rs_sw > 0); }}, Likely); 1590 } 1591 } 1592 1593 0x3: decode OPCODE_LO { 1594 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1595 0x4: decode FUNCTION_HI { 1596 0x0: decode FUNCTION_LO { 1597 0x2: IntOp::mul({{ 1598 int64_t temp1 = Rs_sd * Rt_sd; 1599 Rd = temp1<31:0>; 1600 }}, IntMultOp); 1601 1602 format HiLoRdSelValOp { 1603 0x0: madd({{ 1604 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1605 (Rs_sd * Rt_sd); 1606 }}, IntMultOp); 1607 0x1: maddu({{ 1608 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1609 (Rs_ud * Rt_ud); 1610 }}, IntMultOp); 1611 0x4: msub({{ 1612 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1613 (Rs_sd * Rt_sd); 1614 }}, IntMultOp); 1615 0x5: msubu({{ 1616 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1617 (Rs_ud * Rt_ud); 1618 }}, IntMultOp); 1619 } 1620 } 1621 1622 0x4: decode FUNCTION_LO { 1623 format BasicOp { 1624 0x0: clz({{ 1625 int cnt = 32; 1626 for (int idx = 31; idx >= 0; idx--) { 1627 if (Rs<idx:idx> == 1) { 1628 cnt = 31 - idx; 1629 break; 1630 } 1631 } 1632 Rd = cnt; 1633 }}); 1634 0x1: clo({{ 1635 int cnt = 32; 1636 for (int idx = 31; idx >= 0; idx--) { 1637 if (Rs<idx:idx> == 0) { 1638 cnt = 31 - idx; 1639 break; 1640 } 1641 } 1642 Rd = cnt; 1643 }}); 1644 } 1645 } 1646 1647 0x7: decode FUNCTION_LO { 1648 0x7: FailUnimpl::sdbbp(); 1649 } 1650 } 1651 1652 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1653 //of the Architecture 1654 0x7: decode FUNCTION_HI { 1655 0x0: decode FUNCTION_LO { 1656 format BasicOp { 1657 0x0: ext({{ Rt = bits(Rs, MSB + LSB, LSB); }}); 1658 0x4: ins({{ 1659 Rt = bits(Rt, 31, MSB + 1) << (MSB + 1) | 1660 bits(Rs, MSB - LSB, 0) << LSB | 1661 bits(Rt, LSB - 1, 0); 1662 }}); 1663 } 1664 } 1665 1666 0x1: decode FUNCTION_LO { 1667 format MT_Control { 1668 0x0: fork({{ 1669 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1670 }}, UserMode); 1671 0x1: yield({{ 1672 Rd = yieldThread(xc->tcBase(), fault, Rs_sw, 1673 YQMask); 1674 }}, UserMode); 1675 } 1676 1677 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1678 0x2: decode OP_HI { 1679 0x0: decode OP_LO { 1680 format LoadIndexedMemory { 1681 0x0: lwx({{ Rd = Mem; }}); 1682 0x4: lhx({{ Rd = Mem_sh; }}); 1683 0x6: lbux({{ Rd = Mem_ub; }}); 1684 } 1685 } 1686 } 1687 0x4: DspIntOp::insv({{ 1688 int pos = dspctl<5:0>; 1689 int size = dspctl<12:7> - 1; 1690 Rt = insertBits(Rt, pos + size, pos, Rs<size:0>); 1691 }}); 1692 } 1693 1694 0x2: decode FUNCTION_LO { 1695 1696 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1697 //(DSP ASE MANUAL) 1698 0x0: decode OP_HI { 1699 0x0: decode OP_LO { 1700 format DspIntOp { 1701 0x0: addu_qb({{ 1702 Rd = dspAdd(Rs, Rt, SIMD_FMT_QB, 1703 NOSATURATE, UNSIGNED, &dspctl); 1704 }}); 1705 0x1: subu_qb({{ 1706 Rd = dspSub(Rs, Rt, SIMD_FMT_QB, 1707 NOSATURATE, UNSIGNED, &dspctl); 1708 }}); 1709 0x4: addu_s_qb({{ 1710 Rd = dspAdd(Rs, Rt, SIMD_FMT_QB, 1711 SATURATE, UNSIGNED, &dspctl); 1712 }}); 1713 0x5: subu_s_qb({{ 1714 Rd = dspSub(Rs, Rt, SIMD_FMT_QB, 1715 SATURATE, UNSIGNED, &dspctl); 1716 }}); 1717 0x6: muleu_s_ph_qbl({{ 1718 Rd = dspMuleu(Rs, Rt, MODE_L, &dspctl); 1719 }}, IntMultOp); 1720 0x7: muleu_s_ph_qbr({{ 1721 Rd = dspMuleu(Rs, Rt, MODE_R, &dspctl); 1722 }}, IntMultOp); 1723 } 1724 } 1725 0x1: decode OP_LO { 1726 format DspIntOp { 1727 0x0: addu_ph({{ 1728 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH, 1729 NOSATURATE, UNSIGNED, &dspctl); 1730 }}); 1731 0x1: subu_ph({{ 1732 Rd = dspSub(Rs, Rt, SIMD_FMT_PH, 1733 NOSATURATE, UNSIGNED, &dspctl); 1734 }}); 1735 0x2: addq_ph({{ 1736 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH, 1737 NOSATURATE, SIGNED, &dspctl); 1738 }}); 1739 0x3: subq_ph({{ 1740 Rd = dspSub(Rs, Rt, SIMD_FMT_PH, 1741 NOSATURATE, SIGNED, &dspctl); 1742 }}); 1743 0x4: addu_s_ph({{ 1744 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH, 1745 SATURATE, UNSIGNED, &dspctl); 1746 }}); 1747 0x5: subu_s_ph({{ 1748 Rd = dspSub(Rs, Rt, SIMD_FMT_PH, 1749 SATURATE, UNSIGNED, &dspctl); 1750 }}); 1751 0x6: addq_s_ph({{ 1752 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH, 1753 SATURATE, SIGNED, &dspctl); 1754 }}); 1755 0x7: subq_s_ph({{ 1756 Rd = dspSub(Rs, Rt, SIMD_FMT_PH, 1757 SATURATE, SIGNED, &dspctl); 1758 }}); 1759 } 1760 } 1761 0x2: decode OP_LO { 1762 format DspIntOp { 1763 0x0: addsc({{ 1764 int64_t dresult; 1765 dresult = Rs_ud + Rt_ud; 1766 Rd = dresult<31:0>; 1767 dspctl = insertBits(dspctl, 13, 13, 1768 dresult<32:32>); 1769 }}); 1770 0x1: addwc({{ 1771 int64_t dresult; 1772 dresult = Rs_sd + Rt_sd + dspctl<13:13>; 1773 Rd = dresult<31:0>; 1774 if (dresult<32:32> != dresult<31:31>) 1775 dspctl = insertBits(dspctl, 20, 20, 1); 1776 }}); 1777 0x2: modsub({{ 1778 Rd = (Rs_sw == 0) ? Rt_sw<23:8> : 1779 Rs_sw - Rt_sw<7:0>; 1780 }}); 1781 0x4: raddu_w_qb({{ 1782 Rd = Rs<31:24> + Rs<23:16> + 1783 Rs<15:8> + Rs<7:0>; 1784 }}); 1785 0x6: addq_s_w({{ 1786 Rd = dspAdd(Rs_sw, Rt_sw, SIMD_FMT_W, 1787 SATURATE, SIGNED, &dspctl); 1788 }}); 1789 0x7: subq_s_w({{ 1790 Rd = dspSub(Rs_sw, Rt_sw, SIMD_FMT_W, 1791 SATURATE, SIGNED, &dspctl); 1792 }}); 1793 } 1794 } 1795 0x3: decode OP_LO { 1796 format DspIntOp { 1797 0x4: muleq_s_w_phl({{ 1798 Rd = dspMuleq(Rs_sw, Rt_sw, 1799 MODE_L, &dspctl); 1800 }}, IntMultOp); 1801 0x5: muleq_s_w_phr({{ 1802 Rd = dspMuleq(Rs_sw, Rt_sw, 1803 MODE_R, &dspctl); 1804 }}, IntMultOp); 1805 0x6: mulq_s_ph({{ 1806 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1807 SATURATE, NOROUND, &dspctl); 1808 }}, IntMultOp); 1809 0x7: mulq_rs_ph({{ 1810 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1811 SATURATE, ROUND, &dspctl); 1812 }}, IntMultOp); 1813 } 1814 } 1815 } 1816 1817 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1818 //(DSP ASE MANUAL) 1819 0x1: decode OP_HI { 1820 0x0: decode OP_LO { 1821 format DspIntOp { 1822 0x0: cmpu_eq_qb({{ 1823 dspCmp(Rs, Rt, SIMD_FMT_QB, 1824 UNSIGNED, CMP_EQ, &dspctl); 1825 }}); 1826 0x1: cmpu_lt_qb({{ 1827 dspCmp(Rs, Rt, SIMD_FMT_QB, 1828 UNSIGNED, CMP_LT, &dspctl); 1829 }}); 1830 0x2: cmpu_le_qb({{ 1831 dspCmp(Rs, Rt, SIMD_FMT_QB, 1832 UNSIGNED, CMP_LE, &dspctl); 1833 }}); 1834 0x3: pick_qb({{ 1835 Rd = dspPick(Rs, Rt, SIMD_FMT_QB, &dspctl); 1836 }}); 1837 0x4: cmpgu_eq_qb({{ 1838 Rd = dspCmpg(Rs, Rt, SIMD_FMT_QB, 1839 UNSIGNED, CMP_EQ ); 1840 }}); 1841 0x5: cmpgu_lt_qb({{ 1842 Rd = dspCmpg(Rs, Rt, SIMD_FMT_QB, 1843 UNSIGNED, CMP_LT); 1844 }}); 1845 0x6: cmpgu_le_qb({{ 1846 Rd = dspCmpg(Rs, Rt, SIMD_FMT_QB, 1847 UNSIGNED, CMP_LE); 1848 }}); 1849 } 1850 } 1851 0x1: decode OP_LO { 1852 format DspIntOp { 1853 0x0: cmp_eq_ph({{ 1854 dspCmp(Rs, Rt, SIMD_FMT_PH, 1855 SIGNED, CMP_EQ, &dspctl); 1856 }}); 1857 0x1: cmp_lt_ph({{ 1858 dspCmp(Rs, Rt, SIMD_FMT_PH, 1859 SIGNED, CMP_LT, &dspctl); 1860 }}); 1861 0x2: cmp_le_ph({{ 1862 dspCmp(Rs, Rt, SIMD_FMT_PH, 1863 SIGNED, CMP_LE, &dspctl); 1864 }}); 1865 0x3: pick_ph({{ 1866 Rd = dspPick(Rs, Rt, SIMD_FMT_PH, &dspctl); 1867 }}); 1868 0x4: precrq_qb_ph({{ 1869 Rd = Rs<31:24> << 24 | Rs<15:8> << 16 | 1870 Rt<31:24> << 8 | Rt<15:8>; 1871 }}); 1872 0x5: precr_qb_ph({{ 1873 Rd = Rs<23:16> << 24 | Rs<7:0> << 16 | 1874 Rt<23:16> << 8 | Rt<7:0>; 1875 }}); 1876 0x6: packrl_ph({{ 1877 Rd = dspPack(Rs, Rt, SIMD_FMT_PH); 1878 }}); 1879 0x7: precrqu_s_qb_ph({{ 1880 Rd = dspPrecrqu(Rs, Rt, &dspctl); 1881 }}); 1882 } 1883 } 1884 0x2: decode OP_LO { 1885 format DspIntOp { 1886 0x4: precrq_ph_w({{ 1887 Rd = Rs<31:16> << 16 | Rt<31:16>; 1888 }}); 1889 0x5: precrq_rs_ph_w({{ 1890 Rd = dspPrecrq(Rs, Rt, SIMD_FMT_W, &dspctl); 1891 }}); 1892 } 1893 } 1894 0x3: decode OP_LO { 1895 format DspIntOp { 1896 0x0: cmpgdu_eq_qb({{ 1897 Rd = dspCmpgd(Rs, Rt, SIMD_FMT_QB, 1898 UNSIGNED, CMP_EQ, &dspctl); 1899 }}); 1900 0x1: cmpgdu_lt_qb({{ 1901 Rd = dspCmpgd(Rs, Rt, SIMD_FMT_QB, 1902 UNSIGNED, CMP_LT, &dspctl); 1903 }}); 1904 0x2: cmpgdu_le_qb({{ 1905 Rd = dspCmpgd(Rs, Rt, SIMD_FMT_QB, 1906 UNSIGNED, CMP_LE, &dspctl); 1907 }}); 1908 0x6: precr_sra_ph_w({{ 1909 Rt = dspPrecrSra(Rt, Rs, RD, 1910 SIMD_FMT_W, NOROUND); 1911 }}); 1912 0x7: precr_sra_r_ph_w({{ 1913 Rt = dspPrecrSra(Rt, Rs, RD, 1914 SIMD_FMT_W, ROUND); 1915 }}); 1916 } 1917 } 1918 } 1919 1920 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1921 //(DSP ASE MANUAL) 1922 0x2: decode OP_HI { 1923 0x0: decode OP_LO { 1924 format DspIntOp { 1925 0x1: absq_s_qb({{ 1926 Rd = dspAbs(Rt_sw, SIMD_FMT_QB, &dspctl); 1927 }}); 1928 0x2: repl_qb({{ 1929 Rd = RS_RT<7:0> << 24 | RS_RT<7:0> << 16 | 1930 RS_RT<7:0> << 8 | RS_RT<7:0>; 1931 }}); 1932 0x3: replv_qb({{ 1933 Rd = Rt<7:0> << 24 | Rt<7:0> << 16 | 1934 Rt<7:0> << 8 | Rt<7:0>; 1935 }}); 1936 0x4: precequ_ph_qbl({{ 1937 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED, 1938 SIMD_FMT_PH, SIGNED, MODE_L); 1939 }}); 1940 0x5: precequ_ph_qbr({{ 1941 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED, 1942 SIMD_FMT_PH, SIGNED, MODE_R); 1943 }}); 1944 0x6: precequ_ph_qbla({{ 1945 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED, 1946 SIMD_FMT_PH, SIGNED, MODE_LA); 1947 }}); 1948 0x7: precequ_ph_qbra({{ 1949 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED, 1950 SIMD_FMT_PH, SIGNED, MODE_RA); 1951 }}); 1952 } 1953 } 1954 0x1: decode OP_LO { 1955 format DspIntOp { 1956 0x1: absq_s_ph({{ 1957 Rd = dspAbs(Rt_sw, SIMD_FMT_PH, &dspctl); 1958 }}); 1959 0x2: repl_ph({{ 1960 Rd = (sext<10>(RS_RT))<15:0> << 16 | 1961 (sext<10>(RS_RT))<15:0>; 1962 }}); 1963 0x3: replv_ph({{ 1964 Rd = Rt<15:0> << 16 | Rt<15:0>; 1965 }}); 1966 0x4: preceq_w_phl({{ 1967 Rd = dspPrece(Rt, SIMD_FMT_PH, SIGNED, 1968 SIMD_FMT_W, SIGNED, MODE_L); 1969 }}); 1970 0x5: preceq_w_phr({{ 1971 Rd = dspPrece(Rt, SIMD_FMT_PH, SIGNED, 1972 SIMD_FMT_W, SIGNED, MODE_R); 1973 }}); 1974 } 1975 } 1976 0x2: decode OP_LO { 1977 format DspIntOp { 1978 0x1: absq_s_w({{ 1979 Rd = dspAbs(Rt_sw, SIMD_FMT_W, &dspctl); 1980 }}); 1981 } 1982 } 1983 0x3: decode OP_LO { 1984 0x3: IntOp::bitrev({{ 1985 Rd = bitrev(Rt<15:0>); 1986 }}); 1987 format DspIntOp { 1988 0x4: preceu_ph_qbl({{ 1989 Rd = dspPrece(Rt, SIMD_FMT_QB, 1990 UNSIGNED, SIMD_FMT_PH, 1991 UNSIGNED, MODE_L); 1992 }}); 1993 0x5: preceu_ph_qbr({{ 1994 Rd = dspPrece(Rt, SIMD_FMT_QB, 1995 UNSIGNED, SIMD_FMT_PH, 1996 UNSIGNED, MODE_R ); 1997 }}); 1998 0x6: preceu_ph_qbla({{ 1999 Rd = dspPrece(Rt, SIMD_FMT_QB, 2000 UNSIGNED, SIMD_FMT_PH, 2001 UNSIGNED, MODE_LA ); 2002 }}); 2003 0x7: preceu_ph_qbra({{ 2004 Rd = dspPrece(Rt, SIMD_FMT_QB, 2005 UNSIGNED, SIMD_FMT_PH, 2006 UNSIGNED, MODE_RA); 2007 }}); 2008 } 2009 } 2010 } 2011 2012 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 2013 //(DSP ASE MANUAL) 2014 0x3: decode OP_HI { 2015 0x0: decode OP_LO { 2016 format DspIntOp { 2017 0x0: shll_qb({{ 2018 Rd = dspShll(Rt_sw, RS, SIMD_FMT_QB, 2019 NOSATURATE, UNSIGNED, &dspctl); 2020 }}); 2021 0x1: shrl_qb({{ 2022 Rd = dspShrl(Rt_sw, RS, SIMD_FMT_QB, 2023 UNSIGNED); 2024 }}); 2025 0x2: shllv_qb({{ 2026 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_QB, 2027 NOSATURATE, UNSIGNED, &dspctl); 2028 }}); 2029 0x3: shrlv_qb({{ 2030 Rd = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_QB, 2031 UNSIGNED); 2032 }}); 2033 0x4: shra_qb({{ 2034 Rd = dspShra(Rt_sw, RS, SIMD_FMT_QB, 2035 NOROUND, SIGNED, &dspctl); 2036 }}); 2037 0x5: shra_r_qb({{ 2038 Rd = dspShra(Rt_sw, RS, SIMD_FMT_QB, 2039 ROUND, SIGNED, &dspctl); 2040 }}); 2041 0x6: shrav_qb({{ 2042 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2043 NOROUND, SIGNED, &dspctl); 2044 }}); 2045 0x7: shrav_r_qb({{ 2046 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2047 ROUND, SIGNED, &dspctl); 2048 }}); 2049 } 2050 } 2051 0x1: decode OP_LO { 2052 format DspIntOp { 2053 0x0: shll_ph({{ 2054 Rd = dspShll(Rt, RS, SIMD_FMT_PH, 2055 NOSATURATE, SIGNED, &dspctl); 2056 }}); 2057 0x1: shra_ph({{ 2058 Rd = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2059 NOROUND, SIGNED, &dspctl); 2060 }}); 2061 0x2: shllv_ph({{ 2062 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2063 NOSATURATE, SIGNED, &dspctl); 2064 }}); 2065 0x3: shrav_ph({{ 2066 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2067 NOROUND, SIGNED, &dspctl); 2068 }}); 2069 0x4: shll_s_ph({{ 2070 Rd = dspShll(Rt_sw, RS, SIMD_FMT_PH, 2071 SATURATE, SIGNED, &dspctl); 2072 }}); 2073 0x5: shra_r_ph({{ 2074 Rd = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2075 ROUND, SIGNED, &dspctl); 2076 }}); 2077 0x6: shllv_s_ph({{ 2078 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2079 SATURATE, SIGNED, &dspctl); 2080 }}); 2081 0x7: shrav_r_ph({{ 2082 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2083 ROUND, SIGNED, &dspctl); 2084 }}); 2085 } 2086 } 2087 0x2: decode OP_LO { 2088 format DspIntOp { 2089 0x4: shll_s_w({{ 2090 Rd = dspShll(Rt_sw, RS, SIMD_FMT_W, 2091 SATURATE, SIGNED, &dspctl); 2092 }}); 2093 0x5: shra_r_w({{ 2094 Rd = dspShra(Rt_sw, RS, SIMD_FMT_W, 2095 ROUND, SIGNED, &dspctl); 2096 }}); 2097 0x6: shllv_s_w({{ 2098 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_W, 2099 SATURATE, SIGNED, &dspctl); 2100 }}); 2101 0x7: shrav_r_w({{ 2102 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_W, 2103 ROUND, SIGNED, &dspctl); 2104 }}); 2105 } 2106 } 2107 0x3: decode OP_LO { 2108 format DspIntOp { 2109 0x1: shrl_ph({{ 2110 Rd = dspShrl(Rt_sw, RS, SIMD_FMT_PH, 2111 UNSIGNED); 2112 }}); 2113 0x3: shrlv_ph({{ 2114 Rd = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_PH, 2115 UNSIGNED); 2116 }}); 2117 } 2118 } 2119 } 2120 } 2121 2122 0x3: decode FUNCTION_LO { 2123 2124 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2125 //(DSP ASE Rev2 Manual) 2126 0x0: decode OP_HI { 2127 0x0: decode OP_LO { 2128 format DspIntOp { 2129 0x0: adduh_qb({{ 2130 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2131 NOROUND, UNSIGNED); 2132 }}); 2133 0x1: subuh_qb({{ 2134 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2135 NOROUND, UNSIGNED); 2136 }}); 2137 0x2: adduh_r_qb({{ 2138 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2139 ROUND, UNSIGNED); 2140 }}); 2141 0x3: subuh_r_qb({{ 2142 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2143 ROUND, UNSIGNED); 2144 }}); 2145 } 2146 } 2147 0x1: decode OP_LO { 2148 format DspIntOp { 2149 0x0: addqh_ph({{ 2150 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2151 NOROUND, SIGNED); 2152 }}); 2153 0x1: subqh_ph({{ 2154 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2155 NOROUND, SIGNED); 2156 }}); 2157 0x2: addqh_r_ph({{ 2158 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2159 ROUND, SIGNED); 2160 }}); 2161 0x3: subqh_r_ph({{ 2162 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2163 ROUND, SIGNED); 2164 }}); 2165 0x4: mul_ph({{ 2166 Rd = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2167 NOSATURATE, &dspctl); 2168 }}, IntMultOp); 2169 0x6: mul_s_ph({{ 2170 Rd = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2171 SATURATE, &dspctl); 2172 }}, IntMultOp); 2173 } 2174 } 2175 0x2: decode OP_LO { 2176 format DspIntOp { 2177 0x0: addqh_w({{ 2178 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2179 NOROUND, SIGNED); 2180 }}); 2181 0x1: subqh_w({{ 2182 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2183 NOROUND, SIGNED); 2184 }}); 2185 0x2: addqh_r_w({{ 2186 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2187 ROUND, SIGNED); 2188 }}); 2189 0x3: subqh_r_w({{ 2190 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2191 ROUND, SIGNED); 2192 }}); 2193 0x6: mulq_s_w({{ 2194 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2195 SATURATE, NOROUND, &dspctl); 2196 }}, IntMultOp); 2197 0x7: mulq_rs_w({{ 2198 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2199 SATURATE, ROUND, &dspctl); 2200 }}, IntMultOp); 2201 } 2202 } 2203 } 2204 } 2205 2206 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2207 0x4: decode SA { 2208 format BasicOp { 2209 0x02: wsbh({{ 2210 Rd = Rt<23:16> << 24 | Rt<31:24> << 16 | 2211 Rt<7:0> << 8 | Rt<15:8>; 2212 }}); 2213 0x10: seb({{ Rd = Rt_sb; }}); 2214 0x18: seh({{ Rd = Rt_sh; }}); 2215 } 2216 } 2217 2218 0x6: decode FUNCTION_LO { 2219 2220 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2221 //(DSP ASE MANUAL) 2222 0x0: decode OP_HI { 2223 0x0: decode OP_LO { 2224 format DspHiLoOp { 2225 0x0: dpa_w_ph({{ 2226 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2227 SIMD_FMT_PH, SIGNED, MODE_L); 2228 }}, IntMultOp); 2229 0x1: dps_w_ph({{ 2230 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2231 SIMD_FMT_PH, SIGNED, MODE_L); 2232 }}, IntMultOp); 2233 0x2: mulsa_w_ph({{ 2234 dspac = dspMulsa(dspac, Rs_sw, Rt_sw, 2235 ACDST, SIMD_FMT_PH ); 2236 }}, IntMultOp); 2237 0x3: dpau_h_qbl({{ 2238 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2239 SIMD_FMT_QB, UNSIGNED, MODE_L); 2240 }}, IntMultOp); 2241 0x4: dpaq_s_w_ph({{ 2242 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2243 ACDST, SIMD_FMT_PH, 2244 SIMD_FMT_W, NOSATURATE, 2245 MODE_L, &dspctl); 2246 }}, IntMultOp); 2247 0x5: dpsq_s_w_ph({{ 2248 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2249 ACDST, SIMD_FMT_PH, 2250 SIMD_FMT_W, NOSATURATE, 2251 MODE_L, &dspctl); 2252 }}, IntMultOp); 2253 0x6: mulsaq_s_w_ph({{ 2254 dspac = dspMulsaq(dspac, Rs_sw, Rt_sw, 2255 ACDST, SIMD_FMT_PH, 2256 &dspctl); 2257 }}, IntMultOp); 2258 0x7: dpau_h_qbr({{ 2259 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2260 SIMD_FMT_QB, UNSIGNED, MODE_R); 2261 }}, IntMultOp); 2262 } 2263 } 2264 0x1: decode OP_LO { 2265 format DspHiLoOp { 2266 0x0: dpax_w_ph({{ 2267 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2268 SIMD_FMT_PH, SIGNED, MODE_X); 2269 }}, IntMultOp); 2270 0x1: dpsx_w_ph({{ 2271 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2272 SIMD_FMT_PH, SIGNED, MODE_X); 2273 }}, IntMultOp); 2274 0x3: dpsu_h_qbl({{ 2275 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2276 SIMD_FMT_QB, UNSIGNED, MODE_L); 2277 }}, IntMultOp); 2278 0x4: dpaq_sa_l_w({{ 2279 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2280 ACDST, SIMD_FMT_W, 2281 SIMD_FMT_L, SATURATE, 2282 MODE_L, &dspctl); 2283 }}, IntMultOp); 2284 0x5: dpsq_sa_l_w({{ 2285 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2286 ACDST, SIMD_FMT_W, 2287 SIMD_FMT_L, SATURATE, 2288 MODE_L, &dspctl); 2289 }}, IntMultOp); 2290 0x7: dpsu_h_qbr({{ 2291 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2292 SIMD_FMT_QB, UNSIGNED, MODE_R); 2293 }}, IntMultOp); 2294 } 2295 } 2296 0x2: decode OP_LO { 2297 format DspHiLoOp { 2298 0x0: maq_sa_w_phl({{ 2299 dspac = dspMaq(dspac, Rs, Rt, 2300 ACDST, SIMD_FMT_PH, 2301 MODE_L, SATURATE, &dspctl); 2302 }}, IntMultOp); 2303 0x2: maq_sa_w_phr({{ 2304 dspac = dspMaq(dspac, Rs, Rt, 2305 ACDST, SIMD_FMT_PH, 2306 MODE_R, SATURATE, &dspctl); 2307 }}, IntMultOp); 2308 0x4: maq_s_w_phl({{ 2309 dspac = dspMaq(dspac, Rs, Rt, 2310 ACDST, SIMD_FMT_PH, 2311 MODE_L, NOSATURATE, &dspctl); 2312 }}, IntMultOp); 2313 0x6: maq_s_w_phr({{ 2314 dspac = dspMaq(dspac, Rs, Rt, 2315 ACDST, SIMD_FMT_PH, 2316 MODE_R, NOSATURATE, &dspctl); 2317 }}, IntMultOp); 2318 } 2319 } 2320 0x3: decode OP_LO { 2321 format DspHiLoOp { 2322 0x0: dpaqx_s_w_ph({{ 2323 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2324 ACDST, SIMD_FMT_PH, 2325 SIMD_FMT_W, NOSATURATE, 2326 MODE_X, &dspctl); 2327 }}, IntMultOp); 2328 0x1: dpsqx_s_w_ph({{ 2329 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2330 ACDST, SIMD_FMT_PH, 2331 SIMD_FMT_W, NOSATURATE, 2332 MODE_X, &dspctl); 2333 }}, IntMultOp); 2334 0x2: dpaqx_sa_w_ph({{ 2335 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2336 ACDST, SIMD_FMT_PH, 2337 SIMD_FMT_W, SATURATE, 2338 MODE_X, &dspctl); 2339 }}, IntMultOp); 2340 0x3: dpsqx_sa_w_ph({{ 2341 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2342 ACDST, SIMD_FMT_PH, 2343 SIMD_FMT_W, SATURATE, 2344 MODE_X, &dspctl); 2345 }}, IntMultOp); 2346 } 2347 } 2348 } 2349 2350 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2351 0x1: decode OP_HI { 2352 0x0: decode OP_LO { 2353 format IntOp { 2354 0x0: append({{ 2355 Rt = (Rt << RD) | bits(Rs, RD - 1, 0); 2356 }}); 2357 0x1: prepend({{ 2358 Rt = (Rt >> RD) | 2359 (bits(Rs, RD - 1, 0) << (32 - RD)); 2360 }}); 2361 } 2362 } 2363 0x2: decode OP_LO { 2364 format IntOp { 2365 0x0: balign({{ 2366 Rt = (Rt << (8 * BP)) | (Rs >> (8 * (4 - BP))); 2367 }}); 2368 } 2369 } 2370 } 2371 2372 } 2373 0x7: decode FUNCTION_LO { 2374 2375 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2376 //(DSP ASE MANUAL) 2377 0x0: decode OP_HI { 2378 0x0: decode OP_LO { 2379 format DspHiLoOp { 2380 0x0: extr_w({{ 2381 Rt = dspExtr(dspac, SIMD_FMT_W, RS, 2382 NOROUND, NOSATURATE, &dspctl); 2383 }}); 2384 0x1: extrv_w({{ 2385 Rt = dspExtr(dspac, SIMD_FMT_W, Rs, 2386 NOROUND, NOSATURATE, &dspctl); 2387 }}); 2388 0x2: extp({{ 2389 Rt = dspExtp(dspac, RS, &dspctl); 2390 }}); 2391 0x3: extpv({{ 2392 Rt = dspExtp(dspac, Rs, &dspctl); 2393 }}); 2394 0x4: extr_r_w({{ 2395 Rt = dspExtr(dspac, SIMD_FMT_W, RS, 2396 ROUND, NOSATURATE, &dspctl); 2397 }}); 2398 0x5: extrv_r_w({{ 2399 Rt = dspExtr(dspac, SIMD_FMT_W, Rs, 2400 ROUND, NOSATURATE, &dspctl); 2401 }}); 2402 0x6: extr_rs_w({{ 2403 Rt = dspExtr(dspac, SIMD_FMT_W, RS, 2404 ROUND, SATURATE, &dspctl); 2405 }}); 2406 0x7: extrv_rs_w({{ 2407 Rt = dspExtr(dspac, SIMD_FMT_W, Rs, 2408 ROUND, SATURATE, &dspctl); 2409 }}); 2410 } 2411 } 2412 0x1: decode OP_LO { 2413 format DspHiLoOp { 2414 0x2: extpdp({{ 2415 Rt = dspExtpd(dspac, RS, &dspctl); 2416 }}); 2417 0x3: extpdpv({{ 2418 Rt = dspExtpd(dspac, Rs, &dspctl); 2419 }}); 2420 0x6: extr_s_h({{ 2421 Rt = dspExtr(dspac, SIMD_FMT_PH, RS, 2422 NOROUND, SATURATE, &dspctl); 2423 }}); 2424 0x7: extrv_s_h({{ 2425 Rt = dspExtr(dspac, SIMD_FMT_PH, Rs, 2426 NOROUND, SATURATE, &dspctl); 2427 }}); 2428 } 2429 } 2430 0x2: decode OP_LO { 2431 format DspIntOp { 2432 0x2: rddsp({{ 2433 Rd = readDSPControl(&dspctl, RDDSPMASK); 2434 }}); 2435 0x3: wrdsp({{ 2436 writeDSPControl(&dspctl, Rs, WRDSPMASK); 2437 }}); 2438 } 2439 } 2440 0x3: decode OP_LO { 2441 format DspHiLoOp { 2442 0x2: shilo({{ 2443 if ((int64_t)sext<6>(HILOSA) < 0) { 2444 dspac = (uint64_t)dspac << 2445 -sext<6>(HILOSA); 2446 } else { 2447 dspac = (uint64_t)dspac >> 2448 sext<6>(HILOSA); 2449 } 2450 }}); 2451 0x3: shilov({{ 2452 if ((int64_t)sext<6>(Rs_sw<5:0>) < 0) { 2453 dspac = (uint64_t)dspac << 2454 -sext<6>(Rs_sw<5:0>); 2455 } else { 2456 dspac = (uint64_t)dspac >> 2457 sext<6>(Rs_sw<5:0>); 2458 } 2459 }}); 2460 0x7: mthlip({{ 2461 dspac = dspac << 32; 2462 dspac |= Rs; 2463 dspctl = insertBits(dspctl, 5, 0, 2464 dspctl<5:0> + 32); 2465 }}); 2466 } 2467 } 2468 } 2469 0x3: decode OP default FailUnimpl::rdhwr() { 2470 0x0: decode FullSystemInt { 2471 0: decode RD { 2472 29: BasicOp::rdhwr_se({{ Rt = TpValue; }}); 2473 } 2474 } 2475 } 2476 } 2477 } 2478 } 2479 2480 0x4: decode OPCODE_LO { 2481 format LoadMemory { 2482 0x0: lb({{ Rt = Mem_sb; }}); 2483 0x1: lh({{ Rt = Mem_sh; }}); 2484 0x3: lw({{ Rt = Mem_sw; }}); 2485 0x4: lbu({{ Rt = Mem_ub;}}); 2486 0x5: lhu({{ Rt = Mem_uh; }}); 2487 } 2488 2489 format LoadUnalignedMemory { 2490 0x2: lwl({{ 2491 uint32_t mem_shift = 24 - (8 * byte_offset); 2492 Rt = mem_word << mem_shift | (Rt & mask(mem_shift)); 2493 }}); 2494 0x6: lwr({{ 2495 uint32_t mem_shift = 8 * byte_offset; 2496 Rt = (Rt & (mask(mem_shift) << (32 - mem_shift))) | 2497 (mem_word >> mem_shift); 2498 }}); 2499 } 2500 } 2501 2502 0x5: decode OPCODE_LO { 2503 format StoreMemory { 2504 0x0: sb({{ Mem_ub = Rt<7:0>; }}); 2505 0x1: sh({{ Mem_uh = Rt<15:0>; }}); 2506 0x3: sw({{ Mem = Rt<31:0>; }}); 2507 } 2508 2509 format StoreUnalignedMemory { 2510 0x2: swl({{ 2511 uint32_t reg_shift = 24 - (8 * byte_offset); 2512 uint32_t mem_shift = 32 - reg_shift; 2513 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2514 (Rt >> reg_shift); 2515 }}); 2516 0x6: swr({{ 2517 uint32_t reg_shift = 8 * byte_offset; 2518 mem_word = Rt << reg_shift | 2519 (mem_word & (mask(reg_shift))); 2520 }}); 2521 } 2522 format CP0Control { 2523 0x7: cache({{ 2524 //Addr CacheEA = Rs + OFFSET; 2525 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2526 }}); 2527 } 2528 } 2529 2530 0x6: decode OPCODE_LO { 2531 format LoadMemory { 2532 0x0: ll({{ Rt = Mem; }}, mem_flags=LLSC); 2533 0x1: lwc1({{ Ft_uw = Mem; }}); 2534 0x5: ldc1({{ Ft_ud = Mem_ud; }}); 2535 } 2536 0x2: CP2Unimpl::lwc2(); 2537 0x6: CP2Unimpl::ldc2(); 2538 0x3: Prefetch::pref(); 2539 } 2540 2541 2542 0x7: decode OPCODE_LO { 2543 0x0: StoreCond::sc({{ Mem = Rt; }}, 2544 {{ uint64_t tmp = write_result; 2545 Rt = (tmp == 0 || tmp == 1) ? tmp : Rt; 2546 }}, mem_flags=LLSC, 2547 inst_flags = IsStoreConditional); 2548 format StoreMemory { 2549 0x1: swc1({{ Mem = Ft_uw; }}); 2550 0x5: sdc1({{ Mem_ud = Ft_ud; }}); 2551 } 2552 0x2: CP2Unimpl::swc2(); 2553 0x6: CP2Unimpl::sdc2(); 2554 } 2555} 2556 2557 2558