decoder.isa revision 10474
11689SN/A// -*- mode:c++ -*- 210333Smitch.hayenga@arm.com 39920Syasuko.eckert@amd.com// Copyright (c) 2007 MIPS Technologies, Inc. 47944SGiacomo.Gabrielli@arm.com// All rights reserved. 57944SGiacomo.Gabrielli@arm.com// 67944SGiacomo.Gabrielli@arm.com// Redistribution and use in source and binary forms, with or without 77944SGiacomo.Gabrielli@arm.com// modification, are permitted provided that the following conditions are 87944SGiacomo.Gabrielli@arm.com// met: redistributions of source code must retain the above copyright 97944SGiacomo.Gabrielli@arm.com// notice, this list of conditions and the following disclaimer; 107944SGiacomo.Gabrielli@arm.com// redistributions in binary form must reproduce the above copyright 117944SGiacomo.Gabrielli@arm.com// notice, this list of conditions and the following disclaimer in the 127944SGiacomo.Gabrielli@arm.com// documentation and/or other materials provided with the distribution; 137944SGiacomo.Gabrielli@arm.com// neither the name of the copyright holders nor the names of its 147944SGiacomo.Gabrielli@arm.com// contributors may be used to endorse or promote products derived from 152326SN/A// this software without specific prior written permission. 161689SN/A// 171689SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 281689SN/A// 291689SN/A// Authors: Korey Sewell 301689SN/A// Brett Miller 311689SN/A// Jaidev Patwardhan 321689SN/A 331689SN/A//////////////////////////////////////////////////////////////////// 341689SN/A// 351689SN/A// The actual MIPS32 ISA decoder 361689SN/A// ----------------------------- 371689SN/A// The following instructions are specified in the MIPS32 ISA 381689SN/A// Specification. Decoding closely follows the style specified 391689SN/A// in the MIPS32 ISA specification document starting with Table 402665Ssaidi@eecs.umich.edu// A-2 (document available @ http://www.mips.com) 412665Ssaidi@eecs.umich.edu// 422831Sksewell@umich.edudecode OPCODE_HI default Unknown::unknown() { 431689SN/A //Table A-2 441689SN/A 0x0: decode OPCODE_LO { 459944Smatt.horsnell@ARM.com 0x0: decode FUNCTION_HI { 469944Smatt.horsnell@ARM.com 0x0: decode FUNCTION_LO { 479944Smatt.horsnell@ARM.com 0x1: decode MOVCI { 482064SN/A format BasicOp { 491060SN/A 0: movf({{ 501060SN/A Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; 512292SN/A }}); 521717SN/A 1: movt({{ 538232Snate@binkert.org Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; 544762Snate@binkert.org }}); 556221Snate@binkert.org } 564762Snate@binkert.org } 571060SN/A 588737Skoansin.tan@gmail.com format BasicOp { 598737Skoansin.tan@gmail.com //Table A-3 Note: "Specific encodings of the rd, rs, and 608737Skoansin.tan@gmail.com //rt fields are used to distinguish SLL, SSNOP, and EHB 615529Snate@binkert.org //functions 621061SN/A 0x0: decode RS { 632292SN/A 0x0: decode RT_RD { 645606Snate@binkert.org 0x0: decode SA default Nop::nop() { 658581Ssteve.reinhardt@amd.com 0x1: ssnop({{;}}); 668581Ssteve.reinhardt@amd.com 0x3: ehb({{;}}); 671060SN/A } 682292SN/A default: sll({{ Rd = Rt_uw << SA; }}); 692292SN/A } 702292SN/A } 712292SN/A 722292SN/A 0x2: decode RS_SRL { 732292SN/A 0x0:decode SRL { 742326SN/A 0: srl({{ Rd = Rt_uw >> SA; }}); 752292SN/A 762292SN/A //Hardcoded assuming 32-bit ISA, 772292SN/A //probably need parameter here 782292SN/A 1: rotr({{ 792292SN/A Rd = (Rt_uw << (32 - SA)) | (Rt_uw >> SA); 802292SN/A }}); 815336Shines@cs.fsu.edu } 822292SN/A } 834873Sstever@eecs.umich.edu 842292SN/A 0x3: decode RS { 852292SN/A 0x0: sra({{ 862292SN/A uint32_t temp = Rt >> SA; 874329Sktlim@umich.edu if ( (Rt & 0x80000000) > 0 ) { 885529Snate@binkert.org uint32_t mask = 0x80000000; 894329Sktlim@umich.edu for(int i=0; i < SA; i++) { 904329Sktlim@umich.edu temp |= mask; 914329Sktlim@umich.edu mask = mask >> 1; 922292SN/A } 932292SN/A } 942292SN/A Rd = temp; 952292SN/A }}); 962292SN/A } 972292SN/A 985529Snate@binkert.org 0x4: sllv({{ Rd = Rt_uw << Rs<4:0>; }}); 991060SN/A 1009920Syasuko.eckert@amd.com 0x6: decode SRLV { 1019920Syasuko.eckert@amd.com 0: srlv({{ Rd = Rt_uw >> Rs<4:0>; }}); 1029920Syasuko.eckert@amd.com 1031060SN/A //Hardcoded assuming 32-bit ISA, 1041060SN/A //probably need parameter here 1051060SN/A 1: rotrv({{ 1062326SN/A Rd = (Rt_uw << (32 - Rs<4:0>)) | 1071060SN/A (Rt_uw >> Rs<4:0>); 1081060SN/A }}); 1091060SN/A } 1101060SN/A 1112292SN/A 0x7: srav({{ 1126221Snate@binkert.org int shift_amt = Rs<4:0>; 1136221Snate@binkert.org 1146221Snate@binkert.org uint32_t temp = Rt >> shift_amt; 1151060SN/A 1161060SN/A if ((Rt & 0x80000000) > 0) { 1172307SN/A uint32_t mask = 0x80000000; 1182292SN/A for (int i = 0; i < shift_amt; i++) { 1192980Sgblack@eecs.umich.edu temp |= mask; 1202292SN/A mask = mask >> 1; 1212292SN/A } 1222292SN/A } 1232292SN/A Rd = temp; 1242292SN/A }}); 1252292SN/A } 1262292SN/A } 1272292SN/A 1282292SN/A 0x1: decode FUNCTION_LO { 1292292SN/A //Table A-3 Note: "Specific encodings of the hint field are 1306221Snate@binkert.org //used to distinguish JR from JR.HB and JALR from JALR.HB" 1316221Snate@binkert.org format Jump { 1322292SN/A 0x0: decode HINT { 1332292SN/A 0x1: jr_hb({{ 1342292SN/A Config1Reg config1 = Config1; 1352292SN/A if (config1.ca == 0) { 1362292SN/A NNPC = Rs; 1372292SN/A } else { 1382292SN/A panic("MIPS16e not supported\n"); 1392292SN/A } 1402292SN/A }}, IsReturn, ClearHazards); 1416221Snate@binkert.org default: jr({{ 1426221Snate@binkert.org Config1Reg config1 = Config1; 1432292SN/A if (config1.ca == 0) { 1442292SN/A NNPC = Rs; 1452831Sksewell@umich.edu } else { 1462292SN/A panic("MIPS16e not supported\n"); 1472292SN/A } 1482292SN/A }}, IsReturn); 1492292SN/A } 1502292SN/A 1512292SN/A 0x1: decode HINT { 1522292SN/A 0x1: jalr_hb({{ 1532292SN/A Rd = NNPC; 1542292SN/A NNPC = Rs; 1556221Snate@binkert.org }}, IsCall, ClearHazards); 1566221Snate@binkert.org default: jalr({{ 1572292SN/A Rd = NNPC; 1582292SN/A NNPC = Rs; 1592831Sksewell@umich.edu }}, IsCall); 1602292SN/A } 1612292SN/A } 1622292SN/A 1632292SN/A format BasicOp { 1642292SN/A 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 1652292SN/A 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 1662292SN/A 0x4: decode FullSystemInt { 1672292SN/A 0: syscall_se({{ xc->syscall(R2); }}, 1682292SN/A IsSerializeAfter, IsNonSpeculative); 1692292SN/A default: syscall({{ fault = std::make_shared<SystemCallFault>(); }}); 1702326SN/A } 1712348SN/A 0x7: sync({{ ; }}, IsMemBarrier); 1722326SN/A 0x5: break({{fault = std::make_shared<BreakpointFault>();}}); 1732326SN/A } 1742348SN/A 1752292SN/A } 1762292SN/A 1772292SN/A 0x2: decode FUNCTION_LO { 1782292SN/A 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, 1792292SN/A IntMultOp, IsIprAccess); 1802292SN/A 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); 1812292SN/A 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, 1821060SN/A IntMultOp, IsIprAccess); 1831060SN/A 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); 1841061SN/A } 1851060SN/A 1861062SN/A 0x3: decode FUNCTION_LO { 1871062SN/A format HiLoRdSelValOp { 1882301SN/A 0x0: mult({{ val = Rs_sd * Rt_sd; }}, IntMultOp); 1891062SN/A 0x1: multu({{ val = Rs_ud * Rt_ud; }}, IntMultOp); 1901062SN/A } 1911062SN/A 1921062SN/A format HiLoOp { 1931062SN/A 0x2: div({{ 1941062SN/A if (Rt_sd != 0) { 1951062SN/A HI0 = Rs_sd % Rt_sd; 1961062SN/A LO0 = Rs_sd / Rt_sd; 1971062SN/A } 1981062SN/A }}, IntDivOp); 1992301SN/A 2002301SN/A 0x3: divu({{ 2012301SN/A if (Rt_ud != 0) { 2022301SN/A HI0 = Rs_ud % Rt_ud; 2031062SN/A LO0 = Rs_ud / Rt_ud; 2041062SN/A } 2051062SN/A }}, IntDivOp); 2061062SN/A } 2071062SN/A } 2081062SN/A 2091062SN/A 0x4: decode HINT { 2101062SN/A 0x0: decode FUNCTION_LO { 2111062SN/A format IntOp { 2121062SN/A 0x0: add({{ 2131062SN/A IntReg result; 2141062SN/A Rd = result = Rs + Rt; 2151062SN/A if (FullSystem && 2161062SN/A findOverflow(32, result, Rs, Rt)) { 2171062SN/A fault = std::make_shared<IntegerOverflowFault>(); 2181062SN/A } 2191062SN/A }}); 2201062SN/A 0x1: addu({{ Rd_sw = Rs_sw + Rt_sw;}}); 2211062SN/A 0x2: sub({{ 2221062SN/A IntReg result; 2231062SN/A Rd = result = Rs - Rt; 2241062SN/A if (FullSystem && 2251062SN/A findOverflow(32, result, Rs, ~Rt)) { 2261062SN/A fault = std::make_shared<IntegerOverflowFault>(); 2271062SN/A } 2281062SN/A }}); 2291062SN/A 0x3: subu({{ Rd_sw = Rs_sw - Rt_sw; }}); 2301062SN/A 0x4: and({{ Rd = Rs & Rt; }}); 2311062SN/A 0x5: or({{ Rd = Rs | Rt; }}); 2321062SN/A 0x6: xor({{ Rd = Rs ^ Rt; }}); 2331062SN/A 0x7: nor({{ Rd = ~(Rs | Rt); }}); 2341062SN/A } 2351062SN/A } 2361062SN/A } 2371062SN/A 2381062SN/A 0x5: decode HINT { 2391062SN/A 0x0: decode FUNCTION_LO { 2401062SN/A format IntOp{ 2411062SN/A 0x2: slt({{ Rd_sw = (Rs_sw < Rt_sw) ? 1 : 0 }}); 2421062SN/A 0x3: sltu({{ Rd_uw = (Rs_uw < Rt_uw) ? 1 : 0 }}); 2431062SN/A } 2441062SN/A } 2451062SN/A } 2461062SN/A 2471062SN/A 0x6: decode FUNCTION_LO { 2481062SN/A format Trap { 2491062SN/A 0x0: tge({{ cond = (Rs_sw >= Rt_sw); }}); 2502361SN/A 0x1: tgeu({{ cond = (Rs_uw >= Rt_uw); }}); 2512326SN/A 0x2: tlt({{ cond = (Rs_sw < Rt_sw); }}); 2522301SN/A 0x3: tltu({{ cond = (Rs_uw < Rt_uw); }}); 2532301SN/A 0x4: teq({{ cond = (Rs_sw == Rt_sw); }}); 2542301SN/A 0x6: tne({{ cond = (Rs_sw != Rt_sw); }}); 2552301SN/A } 2562301SN/A } 2572301SN/A } 2582326SN/A 2592301SN/A 0x1: decode REGIMM_HI { 2602361SN/A 0x0: decode REGIMM_LO { 2612326SN/A format Branch { 2622307SN/A 0x0: bltz({{ cond = (Rs_sw < 0); }}); 2638240Snate@binkert.org 0x1: bgez({{ cond = (Rs_sw >= 0); }}); 2642301SN/A 0x2: bltzl({{ cond = (Rs_sw < 0); }}, Likely); 2652307SN/A 0x3: bgezl({{ cond = (Rs_sw >= 0); }}, Likely); 2662301SN/A } 2672301SN/A } 2682301SN/A 2692301SN/A 0x1: decode REGIMM_LO { 2708240Snate@binkert.org format TrapImm { 2712301SN/A 0x0: tgei( {{ cond = (Rs_sw >= (int16_t)INTIMM); }}); 2722301SN/A 0x1: tgeiu({{ 2732301SN/A cond = (Rs_uw >= (uint32_t)(int32_t)(int16_t)INTIMM); 2742301SN/A }}); 2752301SN/A 0x2: tlti( {{ cond = (Rs_sw < (int16_t)INTIMM); }}); 2762301SN/A 0x3: tltiu({{ 2772301SN/A cond = (Rs_uw < (uint32_t)(int32_t)(int16_t)INTIMM); 2782326SN/A }}); 2794762Snate@binkert.org 0x4: teqi( {{ cond = (Rs_sw == (int16_t)INTIMM); }}); 2808240Snate@binkert.org 0x6: tnei( {{ cond = (Rs_sw != (int16_t)INTIMM); }}); 2812301SN/A } 2822301SN/A } 2832301SN/A 2844762Snate@binkert.org 0x2: decode REGIMM_LO { 2852301SN/A format Branch { 2862301SN/A 0x0: bltzal({{ cond = (Rs_sw < 0); }}, Link); 2872301SN/A 0x1: decode RS { 2882301SN/A 0x0: bal ({{ cond = 1; }}, IsCall, Link); 2892361SN/A default: bgezal({{ cond = (Rs_sw >= 0); }}, Link); 2902326SN/A } 2912301SN/A 0x2: bltzall({{ cond = (Rs_sw < 0); }}, Link, Likely); 2928240Snate@binkert.org 0x3: bgezall({{ cond = (Rs_sw >= 0); }}, Link, Likely); 2932301SN/A } 2942301SN/A } 2952301SN/A 2962301SN/A 0x3: decode REGIMM_LO { 2972301SN/A // from Table 5-4 MIPS32 REGIMM Encoding of rt Field 2982980Sgblack@eecs.umich.edu // (DSP ASE MANUAL) 2992301SN/A 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 3002326SN/A format WarnUnimpl { 3012301SN/A 0x7: synci(); 3022361SN/A } 3032326SN/A } 3048240Snate@binkert.org } 3052301SN/A 3062301SN/A format Jump { 3072301SN/A 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}); 3082326SN/A 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, 3092727Sktlim@umich.edu IsCall, Link); 3102326SN/A } 3112301SN/A 3128240Snate@binkert.org format Branch { 3132301SN/A 0x4: decode RS_RT { 3142301SN/A 0x0: b({{ cond = 1; }}); 3152301SN/A default: beq({{ cond = (Rs_sw == Rt_sw); }}); 3162301SN/A } 3174762Snate@binkert.org 0x5: bne({{ cond = (Rs_sw != Rt_sw); }}); 3182301SN/A 0x6: blez({{ cond = (Rs_sw <= 0); }}); 3192301SN/A 0x7: bgtz({{ cond = (Rs_sw > 0); }}); 3202326SN/A } 3212301SN/A } 3228240Snate@binkert.org 3232301SN/A 0x1: decode OPCODE_LO { 3242301SN/A format IntImmOp { 3252301SN/A 0x0: addi({{ 3262301SN/A IntReg result; 3272326SN/A Rt = result = Rs + imm; 3288240Snate@binkert.org if (FullSystem && 3292301SN/A findOverflow(32, result, Rs, imm)) { 3302301SN/A fault = std::make_shared<IntegerOverflowFault>(); 3312301SN/A } 3322326SN/A }}); 3332301SN/A 0x1: addiu({{ Rt_sw = Rs_sw + imm; }}); 3346221Snate@binkert.org 0x2: slti({{ Rt_sw = (Rs_sw < imm) ? 1 : 0 }}); 3352292SN/A 0x3: sltiu({{ Rt_uw = (Rs_uw < (uint32_t)sextImm) ? 1 : 0;}}); 3366221Snate@binkert.org 0x4: andi({{ Rt_sw = Rs_sw & zextImm; }}); 3372292SN/A 0x5: ori({{ Rt_sw = Rs_sw | zextImm; }}); 3387897Shestness@cs.utexas.edu 0x6: xori({{ Rt_sw = Rs_sw ^ zextImm; }}); 3397897Shestness@cs.utexas.edu 3407897Shestness@cs.utexas.edu 0x7: decode RS { 3417897Shestness@cs.utexas.edu 0x0: lui({{ Rt = imm << 16; }}); 3427897Shestness@cs.utexas.edu } 3437897Shestness@cs.utexas.edu } 3447897Shestness@cs.utexas.edu } 3457897Shestness@cs.utexas.edu 3467897Shestness@cs.utexas.edu 0x2: decode OPCODE_LO { 3477897Shestness@cs.utexas.edu //Table A-11 MIPS32 COP0 Encoding of rs Field 3487897Shestness@cs.utexas.edu 0x0: decode RS_MSB { 3497897Shestness@cs.utexas.edu 0x0: decode RS { 3507897Shestness@cs.utexas.edu format CP0Control { 3517897Shestness@cs.utexas.edu 0x0: mfc0({{ 3527897Shestness@cs.utexas.edu Config3Reg config3 = Config3; 3537897Shestness@cs.utexas.edu PageGrainReg pageGrain = PageGrain; 3547897Shestness@cs.utexas.edu Rt = CP0_RD_SEL; 3557897Shestness@cs.utexas.edu /* Hack for PageMask */ 3567897Shestness@cs.utexas.edu if (RD == 5) { 3577897Shestness@cs.utexas.edu // PageMask 3587897Shestness@cs.utexas.edu if (config3.sp == 0 || pageGrain.esp == 0) 3597897Shestness@cs.utexas.edu Rt &= 0xFFFFE7FF; 3607897Shestness@cs.utexas.edu } 3617897Shestness@cs.utexas.edu }}); 3627897Shestness@cs.utexas.edu 0x4: mtc0({{ 3637897Shestness@cs.utexas.edu CP0_RD_SEL = Rt; 3647897Shestness@cs.utexas.edu CauseReg cause = Cause; 3657897Shestness@cs.utexas.edu IntCtlReg intCtl = IntCtl; 3667897Shestness@cs.utexas.edu if (RD == 11) { 3677897Shestness@cs.utexas.edu // Compare 3687897Shestness@cs.utexas.edu if (cause.ti == 1) { 3697897Shestness@cs.utexas.edu cause.ti = 0; 3707897Shestness@cs.utexas.edu int offset = 10; // corresponding to cause.ip0 3717897Shestness@cs.utexas.edu offset += intCtl.ipti - 2; 3727897Shestness@cs.utexas.edu replaceBits(cause, offset, offset, 0); 3737897Shestness@cs.utexas.edu } 3747897Shestness@cs.utexas.edu } 3757897Shestness@cs.utexas.edu Cause = cause; 3767897Shestness@cs.utexas.edu }}); 3777897Shestness@cs.utexas.edu } 3787897Shestness@cs.utexas.edu format CP0Unimpl { 3791062SN/A 0x1: dmfc0(); 3801062SN/A 0x5: dmtc0(); 3811062SN/A default: unknown(); 3821062SN/A } 3832307SN/A format MT_MFTR { 3841060SN/A // Decode MIPS MT MFTR instruction into sub-instructions 3852307SN/A 0x8: decode MT_U { 3866221Snate@binkert.org 0x0: mftc0({{ 3876221Snate@binkert.org data = xc->readRegOtherThread((RT << 3 | SEL) + 3886221Snate@binkert.org Misc_Reg_Base); 3892307SN/A }}); 3901060SN/A 0x1: decode SEL { 3912307SN/A 0x0: mftgpr({{ 3922307SN/A data = xc->readRegOtherThread(RT); 3932307SN/A }}); 3942307SN/A 0x1: decode RT { 3952307SN/A 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }}); 3962307SN/A 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }}); 3972307SN/A 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }}); 3982307SN/A 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }}); 3992307SN/A 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }}); 4002307SN/A 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }}); 4012307SN/A 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }}); 4022307SN/A 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }}); 4036221Snate@binkert.org 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }}); 4046221Snate@binkert.org 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }}); 4052307SN/A 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }}); 4062307SN/A 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }}); 4072307SN/A 0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }}); 4082307SN/A default: CP0Unimpl::unknown(); 4092307SN/A } 4102307SN/A 0x2: decode MT_H { 4112307SN/A 0x0: mftc1({{ data = xc->readRegOtherThread(RT + 4122307SN/A FP_Reg_Base); 4132307SN/A }}); 4142307SN/A 0x1: mfthc1({{ data = xc->readRegOtherThread(RT + 4157944SGiacomo.Gabrielli@arm.com FP_Reg_Base); 41610333Smitch.hayenga@arm.com }}); 41710333Smitch.hayenga@arm.com } 41810511Smitch.hayenga@arm.com 0x3: cftc1({{ 4191060SN/A uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR + 4201060SN/A FP_Reg_Base); 4211061SN/A switch (RT) { 4221060SN/A case 0: 4236221Snate@binkert.org data = xc->readRegOtherThread(FLOATREG_FIR + 4241060SN/A Misc_Reg_Base); 4252292SN/A break; 4262064SN/A case 25: 4272064SN/A data = (fcsr_val & 0xFE000000 >> 24) | 4282064SN/A (fcsr_val & 0x00800000 >> 23); 4292064SN/A break; 4302292SN/A case 26: 4312064SN/A data = fcsr_val & 0x0003F07C; 4324318Sktlim@umich.edu break; 4331060SN/A case 28: 4341060SN/A data = (fcsr_val & 0x00000F80) | 4351061SN/A (fcsr_val & 0x01000000 >> 21) | 4361060SN/A (fcsr_val & 0x00000003); 4371060SN/A break; 4381060SN/A case 31: 4391060SN/A data = fcsr_val; 4401060SN/A break; 4411060SN/A default: 4421060SN/A fatal("FP Control Value (%d) Not Valid"); 4431060SN/A } 4441684SN/A }}); 44510510Smitch.hayenga@arm.com default: CP0Unimpl::unknown(); 44610510Smitch.hayenga@arm.com } 44710510Smitch.hayenga@arm.com } 44810511Smitch.hayenga@arm.com } 44910511Smitch.hayenga@arm.com 45010511Smitch.hayenga@arm.com format MT_MTTR { 45110510Smitch.hayenga@arm.com // Decode MIPS MT MTTR instruction into sub-instructions 45210510Smitch.hayenga@arm.com 0xC: decode MT_U { 45310510Smitch.hayenga@arm.com 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Misc_Reg_Base, 45410510Smitch.hayenga@arm.com Rt); 45510510Smitch.hayenga@arm.com }}); 45610510Smitch.hayenga@arm.com 0x1: decode SEL { 45710510Smitch.hayenga@arm.com 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }}); 4582307SN/A 0x1: decode RT { 4599444SAndreas.Sandberg@ARM.com 0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt); 4602307SN/A }}); 4619444SAndreas.Sandberg@ARM.com 0x1: mtthi_dsp0({{ xc->setRegOtherThread(INTREG_DSP_HI0, 4629444SAndreas.Sandberg@ARM.com Rt); 4639444SAndreas.Sandberg@ARM.com }}); 4649444SAndreas.Sandberg@ARM.com 0x2: mttacx_dsp0({{ xc->setRegOtherThread(INTREG_DSP_ACX0, 4652307SN/A Rt); 4662307SN/A }}); 4672307SN/A 0x4: mttlo_dsp1({{ xc->setRegOtherThread(INTREG_DSP_LO1, 4682307SN/A Rt); 4692307SN/A }}); 4702307SN/A 0x5: mtthi_dsp1({{ xc->setRegOtherThread(INTREG_DSP_HI1, 4719444SAndreas.Sandberg@ARM.com Rt); 4722307SN/A }}); 4732307SN/A 0x6: mttacx_dsp1({{ xc->setRegOtherThread(INTREG_DSP_ACX1, 4742307SN/A Rt); 4752292SN/A }}); 4766221Snate@binkert.org 0x8: mttlo_dsp2({{ xc->setRegOtherThread(INTREG_DSP_LO2, 4772292SN/A Rt); 4782292SN/A }}); 4792292SN/A 0x9: mtthi_dsp2({{ xc->setRegOtherThread(INTREG_DSP_HI2, 4802292SN/A Rt); 4812292SN/A }}); 4822292SN/A 0x10: mttacx_dsp2({{ xc->setRegOtherThread(INTREG_DSP_ACX2, 4832292SN/A Rt); 4842292SN/A }}); 4852292SN/A 0x12: mttlo_dsp3({{ xc->setRegOtherThread(INTREG_DSP_LO3, 4862292SN/A Rt); 4872292SN/A }}); 4882292SN/A 0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3, 4892292SN/A Rt); 4902292SN/A }}); 4913867Sbinkertn@umich.edu 0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt); 4922292SN/A }}); 4936221Snate@binkert.org 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }}); 4946221Snate@binkert.org default: CP0Unimpl::unknown(); 4952292SN/A 4963867Sbinkertn@umich.edu } 4976221Snate@binkert.org 0x2: mttc1({{ 4983867Sbinkertn@umich.edu uint64_t data = xc->readRegOtherThread(RD + 4992292SN/A FP_Reg_Base); 5003867Sbinkertn@umich.edu data = insertBits(data, MT_H ? 63 : 31, 5012292SN/A MT_H ? 32 : 0, Rt); 5023867Sbinkertn@umich.edu xc->setRegOtherThread(RD + FP_Reg_Base, 5032292SN/A data); 5042292SN/A }}); 5052292SN/A 0x3: cttc1({{ 5062292SN/A uint32_t data; 5072292SN/A switch (RD) { 5082292SN/A case 25: 5091684SN/A data = (Rt_uw<7:1> << 25) | // move 31-25 5101684SN/A (FCSR & 0x01000000) | // bit 24 5111684SN/A (FCSR & 0x004FFFFF); // bit 22-0 5121684SN/A break; 5131684SN/A case 26: 5141684SN/A data = (FCSR & 0xFFFC0000) | // move 31-18 5152292SN/A Rt_uw<17:12> << 12 | // bit 17-12 5162292SN/A (FCSR & 0x00000F80) << 7 | // bit 11-7 5176221Snate@binkert.org Rt_uw<6:2> << 2 | // bit 6-2 5182292SN/A (FCSR & 0x00000002); // bit 1...0 5192292SN/A break; 5202292SN/A case 28: 5212292SN/A data = (FCSR & 0xFE000000) | // move 31-25 5221060SN/A Rt_uw<2:2> << 24 | // bit 24 5231060SN/A (FCSR & 0x00FFF000) << 23 | // bit 23-12 5241061SN/A Rt_uw<11:7> << 7 | // bit 24 5251060SN/A (FCSR & 0x000007E) | 5261060SN/A Rt_uw<1:0>; // bit 22-0 5271060SN/A break; 5281060SN/A case 31: 5291060SN/A data = Rt_uw; 5301060SN/A break; 5311060SN/A default: 5321060SN/A panic("FP Control Value (%d) " 5331060SN/A "Not Available. Ignoring " 5341060SN/A "Access to Floating Control " 5351061SN/A "S""tatus Register", FS); 5362292SN/A } 5376221Snate@binkert.org xc->setRegOtherThread(FLOATREG_FCSR + FP_Reg_Base, data); 5382292SN/A }}); 5392292SN/A default: CP0Unimpl::unknown(); 5402292SN/A } 5412292SN/A } 5422292SN/A } 5432292SN/A 0xB: decode RD { 5442292SN/A format MT_Control { 5452292SN/A 0x0: decode POS { 5462292SN/A 0x0: decode SEL { 5472292SN/A 0x1: decode SC { 5482292SN/A 0x0: dvpe({{ 5492292SN/A MVPControlReg mvpControl = MVPControl; 5502292SN/A VPEConf0Reg vpeConf0 = VPEConf0; 5512292SN/A Rt = MVPControl; 5522292SN/A if (vpeConf0.mvp == 1) 5532292SN/A mvpControl.evp = 0; 5542292SN/A MVPControl = mvpControl; 5552292SN/A }}); 5562292SN/A 0x1: evpe({{ 5572292SN/A MVPControlReg mvpControl = MVPControl; 5582292SN/A VPEConf0Reg vpeConf0 = VPEConf0; 5592292SN/A Rt = MVPControl; 5602292SN/A if (vpeConf0.mvp == 1) 5612292SN/A mvpControl.evp = 1; 5622292SN/A MVPControl = mvpControl; 5632292SN/A }}); 5641060SN/A default:CP0Unimpl::unknown(); 5651061SN/A } 5661060SN/A default:CP0Unimpl::unknown(); 5677897Shestness@cs.utexas.edu } 5681060SN/A default:CP0Unimpl::unknown(); 5691060SN/A } 5701060SN/A 0x1: decode POS { 5717720Sgblack@eecs.umich.edu 0xF: decode SEL { 5727720Sgblack@eecs.umich.edu 0x1: decode SC { 5731060SN/A 0x0: dmt({{ 5741060SN/A VPEControlReg vpeControl = VPEControl; 5751060SN/A Rt = vpeControl; 5762292SN/A vpeControl.te = 0; 5771060SN/A VPEControl = vpeControl; 5782064SN/A }}); 5791060SN/A 0x1: emt({{ 5802292SN/A VPEControlReg vpeControl = VPEControl; 5811060SN/A Rt = vpeControl; 5821060SN/A vpeControl.te = 1; 5831060SN/A VPEControl = vpeControl; 5841060SN/A }}); 5851060SN/A default:CP0Unimpl::unknown(); 5861060SN/A } 5871060SN/A default:CP0Unimpl::unknown(); 5882326SN/A } 5891060SN/A default:CP0Unimpl::unknown(); 5901061SN/A } 5912292SN/A } 5921062SN/A 0xC: decode POS { 5931062SN/A 0x0: decode SC { 5941061SN/A 0x0: CP0Control::di({{ 5951061SN/A StatusReg status = Status; 5961062SN/A ConfigReg config = Config; 5971060SN/A // Rev 2.0 or beyond? 5982292SN/A if (config.ar >= 1) { 5992292SN/A Rt = status; 6001060SN/A status.ie = 0; 6011060SN/A } else { 6021060SN/A // Enable this else branch once we 6031061SN/A // actually set values for Config on init 6041061SN/A fault = std::make_shared<ReservedInstructionFault>(); 6052292SN/A } 6061061SN/A Status = status; 6071061SN/A }}); 6081061SN/A 0x1: CP0Control::ei({{ 6097897Shestness@cs.utexas.edu StatusReg status = Status; 6101061SN/A ConfigReg config = Config; 6112292SN/A if (config.ar >= 1) { 6121061SN/A Rt = status; 6132292SN/A status.ie = 1; 6141061SN/A } else { 6157720Sgblack@eecs.umich.edu fault = std::make_shared<ReservedInstructionFault>(); 6162326SN/A } 6177720Sgblack@eecs.umich.edu }}); 6182064SN/A default:CP0Unimpl::unknown(); 6191061SN/A } 6201061SN/A } 6212292SN/A default: CP0Unimpl::unknown(); 6221061SN/A } 6232064SN/A format CP0Control { 6241061SN/A 0xA: rdpgpr({{ 6252292SN/A ConfigReg config = Config; 6261061SN/A if (config.ar >= 1) { 6271061SN/A // Rev 2 of the architecture 6281061SN/A panic("Shadow Sets Not Fully Implemented.\n"); 6292326SN/A } else { 6301061SN/A fault = std::make_shared<ReservedInstructionFault>(); 6311061SN/A } 6321061SN/A }}); 6332292SN/A 0xE: wrpgpr({{ 6342292SN/A ConfigReg config = Config; 6351061SN/A if (config.ar >= 1) { 6361062SN/A // Rev 2 of the architecture 6371062SN/A panic("Shadow Sets Not Fully Implemented.\n"); 6382292SN/A } else { 6392292SN/A fault = std::make_shared<ReservedInstructionFault>(); 6402292SN/A } 6412292SN/A }}); 6421061SN/A } 6431061SN/A } 6441061SN/A 6451060SN/A //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 6462292SN/A 0x1: decode FUNCTION { 6471060SN/A format CP0Control { 6482292SN/A 0x18: eret({{ 6491060SN/A StatusReg status = Status; 6502292SN/A ConfigReg config = Config; 6512292SN/A SRSCtlReg srsCtl = SRSCtl; 6521060SN/A DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 6532064SN/A if (status.erl == 1) { 6542333SN/A status.erl = 0; 6552333SN/A NPC = ErrorEPC; 6562333SN/A // Need to adjust NNPC, otherwise things break 6572333SN/A NNPC = ErrorEPC + sizeof(MachInst); 6582333SN/A } else { 6592333SN/A NPC = EPC; 6607897Shestness@cs.utexas.edu // Need to adjust NNPC, otherwise things break 6617897Shestness@cs.utexas.edu NNPC = EPC + sizeof(MachInst); 6627897Shestness@cs.utexas.edu status.exl = 0; 6637897Shestness@cs.utexas.edu if (config.ar >=1 && 6647897Shestness@cs.utexas.edu srsCtl.hss > 0 && 6652333SN/A status.bev == 0) { 6662333SN/A srsCtl.css = srsCtl.pss; 6671060SN/A //xc->setShadowSet(srsCtl.pss); 6682333SN/A } 6692064SN/A } 6702292SN/A LLFlag = 0; 6712292SN/A Status = status; 6722292SN/A SRSCtl = srsCtl; 6732292SN/A }}, IsReturn, IsSerializing, IsERET); 6742292SN/A 6752292SN/A 0x1F: deret({{ 6762292SN/A DebugReg debug = Debug; 6772292SN/A if (debug.dm == 1) { 6782292SN/A debug.dm = 1; 6792292SN/A debug.iexi = 0; 6802292SN/A NPC = DEPC; 6812292SN/A } else { 6822292SN/A NPC = NPC; 6832292SN/A // Undefined; 6842292SN/A } 6852292SN/A Debug = debug; 6862292SN/A }}, IsReturn, IsSerializing, IsERET); 6872292SN/A } 6882292SN/A format CP0TLB { 6891060SN/A 0x01: tlbr({{ 6901060SN/A MipsISA::PTE *PTEntry = 6912292SN/A xc->tcBase()->getITBPtr()-> 6922292SN/A getEntry(Index & 0x7FFFFFFF); 6932292SN/A if (PTEntry == NULL) { 6941060SN/A fatal("Invalid PTE Entry received on " 6952292SN/A "a TLBR instruction\n"); 6962292SN/A } 6972292SN/A /* Setup PageMask */ 6982292SN/A // If 1KB pages are not enabled, a read of PageMask 6992292SN/A // must return 0b00 in bits 12, 11 7002292SN/A PageMask = (PTEntry->Mask << 11); 7012292SN/A /* Setup EntryHi */ 7022292SN/A EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 7032292SN/A /* Setup Entry Lo0 */ 7042292SN/A EntryLo0 = ((PTEntry->PFN0 << 6) | 7052292SN/A (PTEntry->C0 << 3) | 7062292SN/A (PTEntry->D0 << 2) | 7072292SN/A (PTEntry->V0 << 1) | 7082292SN/A PTEntry->G); 7092292SN/A /* Setup Entry Lo1 */ 7102292SN/A EntryLo1 = ((PTEntry->PFN1 << 6) | 7112292SN/A (PTEntry->C1 << 3) | 7122292SN/A (PTEntry->D1 << 2) | 7132292SN/A (PTEntry->V1 << 1) | 7142292SN/A PTEntry->G); 7152292SN/A }}); // Need to hook up to TLB 7161060SN/A 7171060SN/A 0x02: tlbwi({{ 7182292SN/A //Create PTE 7191060SN/A MipsISA::PTE newEntry; 7201060SN/A //Write PTE 7212292SN/A newEntry.Mask = (Addr)(PageMask >> 11); 7222292SN/A newEntry.VPN = (Addr)(EntryHi >> 11); 7232292SN/A /* PageGrain _ ESP Config3 _ SP */ 7242292SN/A if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) { 7252367SN/A // If 1KB pages are *NOT* enabled, lowest bits of 7269444SAndreas.Sandberg@ARM.com // the mask are 0b11 for TLB writes 7272292SN/A newEntry.Mask |= 0x3; 7282292SN/A // Reset bits 0 and 1 if 1KB pages are not enabled 72910511Smitch.hayenga@arm.com newEntry.VPN &= 0xFFFFFFFC; 7302292SN/A } 7312292SN/A newEntry.asid = (uint8_t)(EntryHi & 0xFF); 7322326SN/A 7332326SN/A newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 7342292SN/A newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 7352326SN/A newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 7362326SN/A newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 7372326SN/A newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 7385327Smengke97@hotmail.com newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 7392333SN/A newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 7402292SN/A newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 7412292SN/A newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 7421061SN/A /* Now, compute the AddrShiftAmount and OffsetMask - 7431061SN/A TLB optimizations */ 7441061SN/A /* Addr Shift Amount for 1KB or larger pages */ 7451061SN/A if ((newEntry.Mask & 0xFFFF) == 3) { 7461060SN/A newEntry.AddrShiftAmount = 12; 7471060SN/A } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 7481060SN/A newEntry.AddrShiftAmount = 10; 7492292SN/A } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 7502292SN/A newEntry.AddrShiftAmount = 14; 7511060SN/A } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 7521060SN/A newEntry.AddrShiftAmount = 16; 7531060SN/A } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 75410333Smitch.hayenga@arm.com newEntry.AddrShiftAmount = 18; 75510333Smitch.hayenga@arm.com } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 75610333Smitch.hayenga@arm.com newEntry.AddrShiftAmount = 20; 75710333Smitch.hayenga@arm.com } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 75810333Smitch.hayenga@arm.com newEntry.AddrShiftAmount = 22; 75910333Smitch.hayenga@arm.com } else if ((newEntry.Mask & 0xF000) == 0x3000) { 76010333Smitch.hayenga@arm.com newEntry.AddrShiftAmount = 24; 76110333Smitch.hayenga@arm.com } else if ((newEntry.Mask & 0xC000) == 0xC000) { 7627944SGiacomo.Gabrielli@arm.com newEntry.AddrShiftAmount = 26; 7637944SGiacomo.Gabrielli@arm.com } else if ((newEntry.Mask & 0x30000) == 0x30000) { 7642292SN/A newEntry.AddrShiftAmount = 28; 7652292SN/A } else { 7662292SN/A fatal("Invalid Mask Pattern Detected!\n"); 7672292SN/A } 7682292SN/A newEntry.OffsetMask = 7692292SN/A (1 << newEntry.AddrShiftAmount) - 1; 7702292SN/A 7712292SN/A MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 77210333Smitch.hayenga@arm.com Config3Reg config3 = Config3; 7732292SN/A PageGrainReg pageGrain = PageGrain; 7742292SN/A int SP = 0; 7751060SN/A if (bits(config3, config3.sp) == 1 && 77610333Smitch.hayenga@arm.com bits(pageGrain, pageGrain.esp) == 1) { 7772292SN/A SP = 1; 7781060SN/A } 7792292SN/A Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 7801060SN/A }}); 7812292SN/A 0x06: tlbwr({{ 7821060SN/A //Create PTE 7837897Shestness@cs.utexas.edu MipsISA::PTE newEntry; 7847897Shestness@cs.utexas.edu //Write PTE 7852292SN/A newEntry.Mask = (Addr)(PageMask >> 11); 7861060SN/A newEntry.VPN = (Addr)(EntryHi >> 11); 7872292SN/A /* PageGrain _ ESP Config3 _ SP */ 7882292SN/A if (bits(PageGrain, 28) == 0 || 7891060SN/A bits(Config3, 4) == 0) { 7902292SN/A // If 1KB pages are *NOT* enabled, lowest bits of 7912292SN/A // the mask are 0b11 for TLB writes 7922292SN/A newEntry.Mask |= 0x3; 7932292SN/A // Reset bits 0 and 1 if 1KB pages are not enabled 7942292SN/A newEntry.VPN &= 0xFFFFFFFC; 7951060SN/A } 7961060SN/A newEntry.asid = (uint8_t)(EntryHi & 0xFF); 7972292SN/A 7981060SN/A newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 7992292SN/A newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 8002292SN/A newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 8012292SN/A newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 8021060SN/A newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 8031060SN/A newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 8042326SN/A newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 8059184Sandreas.hansson@arm.com newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 8066221Snate@binkert.org newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 8071060SN/A /* Now, compute the AddrShiftAmount and OffsetMask - 8082326SN/A TLB optimizations */ 8092326SN/A /* Addr Shift Amount for 1KB or larger pages */ 8107897Shestness@cs.utexas.edu if ((newEntry.Mask & 0xFFFF) == 3){ 8112326SN/A newEntry.AddrShiftAmount = 12; 8122326SN/A } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 8131060SN/A newEntry.AddrShiftAmount = 10; 8141060SN/A } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 8151060SN/A newEntry.AddrShiftAmount = 14; 8162348SN/A } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 8172348SN/A newEntry.AddrShiftAmount = 16; 8182326SN/A } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 8199184Sandreas.hansson@arm.com newEntry.AddrShiftAmount = 18; 8202292SN/A } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 8212333SN/A newEntry.AddrShiftAmount = 20; 8221060SN/A } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 8232326SN/A newEntry.AddrShiftAmount = 22; 8242326SN/A } else if ((newEntry.Mask & 0xF000) == 0x3000) { 8252326SN/A newEntry.AddrShiftAmount = 24; 8262326SN/A } else if ((newEntry.Mask & 0xC000) == 0xC000) { 8272292SN/A newEntry.AddrShiftAmount = 26; 8289184Sandreas.hansson@arm.com } else if ((newEntry.Mask & 0x30000) == 0x30000) { 8292326SN/A newEntry.AddrShiftAmount = 28; 83010511Smitch.hayenga@arm.com } else { 8312326SN/A fatal("Invalid Mask Pattern Detected!\n"); 8322326SN/A } 8331060SN/A newEntry.OffsetMask = 8349180Sandreas.hansson@arm.com (1 << newEntry.AddrShiftAmount) - 1; 8359180Sandreas.hansson@arm.com 8361060SN/A MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 8372326SN/A Config3Reg config3 = Config3; 8389184Sandreas.hansson@arm.com PageGrainReg pageGrain = PageGrain; 8392348SN/A int SP = 0; 8402348SN/A if (bits(config3, config3.sp) == 1 && 8412326SN/A bits(pageGrain, pageGrain.esp) == 1) { 8422292SN/A SP = 1; 8432292SN/A } 8442326SN/A Ptr->insertAt(newEntry, Random, SP); 8452292SN/A }}); 8461060SN/A 8471060SN/A 0x08: tlbp({{ 8487720Sgblack@eecs.umich.edu Config3Reg config3 = Config3; 8492292SN/A PageGrainReg pageGrain = PageGrain; 8507720Sgblack@eecs.umich.edu EntryHiReg entryHi = EntryHi; 8512292SN/A int tlbIndex; 8521060SN/A Addr vpn; 8532292SN/A if (pageGrain.esp == 1 && config3.sp ==1) { 8541061SN/A vpn = EntryHi >> 11; 8552292SN/A } else { 8562292SN/A // Mask off lower 2 bits 8572292SN/A vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 8582292SN/A } 8592292SN/A tlbIndex = xc->tcBase()->getITBPtr()-> 8601060SN/A probeEntry(vpn, entryHi.asid); 8611060SN/A // Check TLB for entry matching EntryHi 8622064SN/A if (tlbIndex != -1) { 8632292SN/A Index = tlbIndex; 8642064SN/A } else { 8658471SGiacomo.Gabrielli@arm.com // else, set Index = 1 << 31 8669046SAli.Saidi@ARM.com Index = (1 << 31); 8678471SGiacomo.Gabrielli@arm.com } 8688471SGiacomo.Gabrielli@arm.com }}); 8692292SN/A } 8702292SN/A format CP0Unimpl { 8712292SN/A 0x20: wait(); 8722292SN/A } 8732301SN/A default: CP0Unimpl::unknown(); 8742731Sktlim@umich.edu } 8752292SN/A } 8762301SN/A 8772292SN/A //Table A-13 MIPS32 COP1 Encoding of rs Field 8782292SN/A 0x1: decode RS_MSB { 8792292SN/A 0x0: decode RS_HI { 8802326SN/A 0x0: decode RS_LO { 8812292SN/A format CP1Control { 8822326SN/A 0x0: mfc1 ({{ Rt_uw = Fs_uw; }}); 8832326SN/A 8842292SN/A 0x2: cfc1({{ 8851060SN/A switch (FS) { 8861060SN/A case 0: 8871062SN/A Rt = FIR; 8882326SN/A break; 8892326SN/A case 25: 8902307SN/A Rt = (FCSR & 0xFE000000) >> 24 | 8912348SN/A (FCSR & 0x00800000) >> 23; 8928071SAli.Saidi@ARM.com break; 8938071SAli.Saidi@ARM.com case 26: 8948071SAli.Saidi@ARM.com Rt = (FCSR & 0x0003F07C); 89510333Smitch.hayenga@arm.com break; 8962292SN/A case 28: 8972292SN/A Rt = (FCSR & 0x00000F80) | 8982292SN/A (FCSR & 0x01000000) >> 21 | 8992292SN/A (FCSR & 0x00000003); 9001060SN/A break; 9011060SN/A case 31: 9021061SN/A Rt = FCSR; 9031060SN/A break; 9041061SN/A default: 9051060SN/A warn("FP Control Value (%d) Not Valid"); 9062292SN/A } 9072292SN/A }}); 9081062SN/A 9092292SN/A 0x3: mfhc1({{ Rt_uw = Fs_ud<63:32>; }}); 9101060SN/A 9111061SN/A 0x4: mtc1({{ Fs_uw = Rt_uw; }}); 9121060SN/A 9136221Snate@binkert.org 0x6: ctc1({{ 9142292SN/A switch (FS) { 9154033Sktlim@umich.edu case 25: 9164033Sktlim@umich.edu FCSR = (Rt_uw<7:1> << 25) | // move 31-25 9171061SN/A (FCSR & 0x01000000) | // bit 24 9181060SN/A (FCSR & 0x004FFFFF); // bit 22-0 9191062SN/A break; 9201062SN/A case 26: 9211062SN/A FCSR = (FCSR & 0xFFFC0000) | // move 31-18 9222292SN/A Rt_uw<17:12> << 12 | // bit 17-12 9231062SN/A (FCSR & 0x00000F80) << 7 | // bit 11-7 9241060SN/A Rt_uw<6:2> << 2 | // bit 6-2 9252292SN/A (FCSR & 0x00000002); // bit 1-0 9262292SN/A break; 9271061SN/A case 28: 9281060SN/A FCSR = (FCSR & 0xFE000000) | // move 31-25 9291060SN/A Rt_uw<2:2> << 24 | // bit 24 9301061SN/A (FCSR & 0x00FFF000) << 23 | // bit 23-12 9311061SN/A Rt_uw<11:7> << 7 | // bit 24 9326221Snate@binkert.org (FCSR & 0x000007E) | 9332292SN/A Rt_uw<1:0>; // bit 22-0 9342292SN/A break; 9352292SN/A case 31: 9362292SN/A FCSR = Rt_uw; 9372292SN/A break; 9382292SN/A 9392292SN/A default: 9402292SN/A panic("FP Control Value (%d) " 9412292SN/A "Not Available. Ignoring Access " 9422292SN/A "to Floating Control Status " 9432292SN/A "Register", FS); 9442292SN/A } 9452292SN/A }}); 9462292SN/A 9472292SN/A 0x7: mthc1({{ 9482292SN/A uint64_t fs_hi = Rt_uw; 9492301SN/A uint64_t fs_lo = Fs_ud & 0x0FFFFFFFF; 9501684SN/A Fs_ud = (fs_hi << 32) | fs_lo; 9511684SN/A }}); 9522301SN/A 9532301SN/A } 9547897Shestness@cs.utexas.edu format CP1Unimpl { 9557897Shestness@cs.utexas.edu 0x1: dmfc1(); 9567897Shestness@cs.utexas.edu 0x5: dmtc1(); 9577897Shestness@cs.utexas.edu } 9587897Shestness@cs.utexas.edu } 9597897Shestness@cs.utexas.edu 9607897Shestness@cs.utexas.edu 0x1: decode RS_LO { 9612292SN/A 0x0: decode ND { 9622292SN/A format Branch { 9632292SN/A 0x0: decode TF { 9641684SN/A 0x0: bc1f({{ 9651684SN/A cond = getCondCode(FCSR, BRANCH_CC) == 0; 9662292SN/A }}); 9672326SN/A 0x1: bc1t({{ 9682326SN/A cond = getCondCode(FCSR, BRANCH_CC) == 1; 9692326SN/A }}); 9702326SN/A } 9711684SN/A 0x1: decode TF { 9722292SN/A 0x0: bc1fl({{ 9732292SN/A cond = getCondCode(FCSR, BRANCH_CC) == 0; 9742292SN/A }}, Likely); 9752292SN/A 0x1: bc1tl({{ 9762292SN/A cond = getCondCode(FCSR, BRANCH_CC) == 1; 9771684SN/A }}, Likely); 9781684SN/A } 9791684SN/A } 9801684SN/A } 9811684SN/A format CP1Unimpl { 9821684SN/A 0x1: bc1any2(); 9831684SN/A 0x2: bc1any4(); 9841684SN/A default: unknown(); 9851684SN/A } 9861684SN/A } 9871684SN/A } 9881684SN/A 9891684SN/A 0x1: decode RS_HI { 9907599Sminkyu.jeong@arm.com 0x2: decode RS_LO { 9917599Sminkyu.jeong@arm.com //Table A-14 MIPS32 COP1 Encoding of Function Field When 9921684SN/A //rs=S (( single-precision floating point)) 9931684SN/A 0x0: decode FUNCTION_HI { 9941684SN/A 0x0: decode FUNCTION_LO { 9952292SN/A format FloatOp { 9961684SN/A 0x0: add_s({{ Fd_sf = Fs_sf + Ft_sf; }}); 9971684SN/A 0x1: sub_s({{ Fd_sf = Fs_sf - Ft_sf; }}); 9982326SN/A 0x2: mul_s({{ Fd_sf = Fs_sf * Ft_sf; }}); 9992326SN/A 0x3: div_s({{ Fd_sf = Fs_sf / Ft_sf; }}); 10002326SN/A 0x4: sqrt_s({{ Fd_sf = sqrt(Fs_sf); }}); 10011684SN/A 0x5: abs_s({{ Fd_sf = fabs(Fs_sf); }}); 10022326SN/A 0x7: neg_s({{ Fd_sf = -Fs_sf; }}); 10037599Sminkyu.jeong@arm.com } 10047720Sgblack@eecs.umich.edu 0x6: BasicOp::mov_s({{ Fd_sf = Fs_sf; }}); 10051684SN/A } 10061684SN/A 0x1: decode FUNCTION_LO { 10072326SN/A format FloatConvertOp { 10082326SN/A 0x0: round_l_s({{ val = Fs_sf; }}, 10092326SN/A ToLong, Round); 10102326SN/A 0x1: trunc_l_s({{ val = Fs_sf; }}, 10111684SN/A ToLong, Trunc); 10122326SN/A 0x2: ceil_l_s({{ val = Fs_sf;}}, 10131684SN/A ToLong, Ceil); 10142326SN/A 0x3: floor_l_s({{ val = Fs_sf; }}, 10151684SN/A ToLong, Floor); 10162301SN/A 0x4: round_w_s({{ val = Fs_sf; }}, 10171684SN/A ToWord, Round); 10181684SN/A 0x5: trunc_w_s({{ val = Fs_sf; }}, 10192326SN/A ToWord, Trunc); 10202326SN/A 0x6: ceil_w_s({{ val = Fs_sf; }}, 10212326SN/A ToWord, Ceil); 10222326SN/A 0x7: floor_w_s({{ val = Fs_sf; }}, 10231684SN/A ToWord, Floor); 10241684SN/A } 10251684SN/A } 10261684SN/A 10272301SN/A 0x2: decode FUNCTION_LO { 10282064SN/A 0x1: decode MOVCF { 10292064SN/A format BasicOp { 10302064SN/A 0x0: movf_s({{ 10312064SN/A Fd = (getCondCode(FCSR,CC) == 0) ? 10322292SN/A Fs : Fd; 10332064SN/A }}); 10342292SN/A 0x1: movt_s({{ 10352292SN/A Fd = (getCondCode(FCSR,CC) == 1) ? 10362292SN/A Fs : Fd; 10372292SN/A }}); 10382326SN/A } 10392326SN/A } 10402326SN/A 10412326SN/A format BasicOp { 10422326SN/A 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 10432326SN/A 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 10442326SN/A } 10452326SN/A 10462326SN/A format FloatOp { 10472326SN/A 0x5: recip_s({{ Fd = 1 / Fs; }}); 10482292SN/A 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); 10497720Sgblack@eecs.umich.edu } 10507720Sgblack@eecs.umich.edu format CP1Unimpl { 10512064SN/A default: unknown(); 10522064SN/A } 10532064SN/A } 10542064SN/A 0x3: CP1Unimpl::unknown(); 10552292SN/A 10562064SN/A 0x4: decode FUNCTION_LO { 10574033Sktlim@umich.edu format FloatConvertOp { 10587944SGiacomo.Gabrielli@arm.com 0x1: cvt_d_s({{ val = Fs_sf; }}, ToDouble); 10597944SGiacomo.Gabrielli@arm.com 0x4: cvt_w_s({{ val = Fs_sf; }}, ToWord); 10609046SAli.Saidi@ARM.com 0x5: cvt_l_s({{ val = Fs_sf; }}, ToLong); 10619046SAli.Saidi@ARM.com } 10627944SGiacomo.Gabrielli@arm.com 10634033Sktlim@umich.edu 0x6: FloatOp::cvt_ps_s({{ 10642292SN/A Fd_ud = (uint64_t) Fs_uw << 32 | 10652064SN/A (uint64_t) Ft_uw; 10662064SN/A }}); 10672064SN/A format CP1Unimpl { 10682064SN/A default: unknown(); 10692292SN/A } 10702064SN/A } 107110333Smitch.hayenga@arm.com 0x5: CP1Unimpl::unknown(); 10722292SN/A 10732292SN/A 0x6: decode FUNCTION_LO { 10742292SN/A format FloatCompareOp { 10752292SN/A 0x0: c_f_s({{ cond = 0; }}, 10762292SN/A SinglePrecision, UnorderedFalse); 10772292SN/A 0x1: c_un_s({{ cond = 0; }}, 10786221Snate@binkert.org SinglePrecision, UnorderedTrue); 10792292SN/A 0x2: c_eq_s({{ cond = (Fs_sf == Ft_sf); }}, 10807720Sgblack@eecs.umich.edu UnorderedFalse); 10817720Sgblack@eecs.umich.edu 0x3: c_ueq_s({{ cond = (Fs_sf == Ft_sf); }}, 10822292SN/A UnorderedTrue); 10832292SN/A 0x4: c_olt_s({{ cond = (Fs_sf < Ft_sf); }}, 10842292SN/A UnorderedFalse); 10859046SAli.Saidi@ARM.com 0x5: c_ult_s({{ cond = (Fs_sf < Ft_sf); }}, 10862292SN/A UnorderedTrue); 10872292SN/A 0x6: c_ole_s({{ cond = (Fs_sf <= Ft_sf); }}, 10882292SN/A UnorderedFalse); 10891684SN/A 0x7: c_ule_s({{ cond = (Fs_sf <= Ft_sf); }}, 10901684SN/A UnorderedTrue); 10911684SN/A } 10921684SN/A } 10937944SGiacomo.Gabrielli@arm.com 10947944SGiacomo.Gabrielli@arm.com 0x7: decode FUNCTION_LO { 10957944SGiacomo.Gabrielli@arm.com format FloatCompareOp { 10967944SGiacomo.Gabrielli@arm.com 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 10977944SGiacomo.Gabrielli@arm.com UnorderedFalse, QnanException); 10987944SGiacomo.Gabrielli@arm.com 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 109910333Smitch.hayenga@arm.com UnorderedTrue, QnanException); 110010333Smitch.hayenga@arm.com 0x2: c_seq_s({{ cond = (Fs_sf == Ft_sf); }}, 110110333Smitch.hayenga@arm.com UnorderedFalse, QnanException); 110210333Smitch.hayenga@arm.com 0x3: c_ngl_s({{ cond = (Fs_sf == Ft_sf); }}, 110310333Smitch.hayenga@arm.com UnorderedTrue, QnanException); 110410333Smitch.hayenga@arm.com 0x4: c_lt_s({{ cond = (Fs_sf < Ft_sf); }}, 110510333Smitch.hayenga@arm.com UnorderedFalse, QnanException); 110610333Smitch.hayenga@arm.com 0x5: c_nge_s({{ cond = (Fs_sf < Ft_sf); }}, 110710333Smitch.hayenga@arm.com UnorderedTrue, QnanException); 110810333Smitch.hayenga@arm.com 0x6: c_le_s({{ cond = (Fs_sf <= Ft_sf); }}, 110910333Smitch.hayenga@arm.com UnorderedFalse, QnanException); 111010333Smitch.hayenga@arm.com 0x7: c_ngt_s({{ cond = (Fs_sf <= Ft_sf); }}, 111110333Smitch.hayenga@arm.com UnorderedTrue, QnanException); 111210333Smitch.hayenga@arm.com } 111310333Smitch.hayenga@arm.com } 111410333Smitch.hayenga@arm.com } 111510333Smitch.hayenga@arm.com 111610333Smitch.hayenga@arm.com //Table A-15 MIPS32 COP1 Encoding of Function Field When 111710333Smitch.hayenga@arm.com //rs=D 111810333Smitch.hayenga@arm.com 0x1: decode FUNCTION_HI { 111910333Smitch.hayenga@arm.com 0x0: decode FUNCTION_LO { 11207944SGiacomo.Gabrielli@arm.com format FloatOp { 11217944SGiacomo.Gabrielli@arm.com 0x0: add_d({{ Fd_df = Fs_df + Ft_df; }}); 11227944SGiacomo.Gabrielli@arm.com 0x1: sub_d({{ Fd_df = Fs_df - Ft_df; }}); 11237944SGiacomo.Gabrielli@arm.com 0x2: mul_d({{ Fd_df = Fs_df * Ft_df; }}); 11247944SGiacomo.Gabrielli@arm.com 0x3: div_d({{ Fd_df = Fs_df / Ft_df; }}); 11259046SAli.Saidi@ARM.com 0x4: sqrt_d({{ Fd_df = sqrt(Fs_df); }}); 112610333Smitch.hayenga@arm.com 0x5: abs_d({{ Fd_df = fabs(Fs_df); }}); 11277944SGiacomo.Gabrielli@arm.com 0x7: neg_d({{ Fd_df = -1 * Fs_df; }}); 112810333Smitch.hayenga@arm.com } 11297944SGiacomo.Gabrielli@arm.com 0x6: BasicOp::mov_d({{ Fd_df = Fs_df; }}); 11307944SGiacomo.Gabrielli@arm.com } 113110333Smitch.hayenga@arm.com 113210333Smitch.hayenga@arm.com 0x1: decode FUNCTION_LO { 113310333Smitch.hayenga@arm.com format FloatConvertOp { 113410333Smitch.hayenga@arm.com 0x0: round_l_d({{ val = Fs_df; }}, 113510333Smitch.hayenga@arm.com ToLong, Round); 113610333Smitch.hayenga@arm.com 0x1: trunc_l_d({{ val = Fs_df; }}, 113710333Smitch.hayenga@arm.com ToLong, Trunc); 113810333Smitch.hayenga@arm.com 0x2: ceil_l_d({{ val = Fs_df; }}, 113910333Smitch.hayenga@arm.com ToLong, Ceil); 114010333Smitch.hayenga@arm.com 0x3: floor_l_d({{ val = Fs_df; }}, 114110333Smitch.hayenga@arm.com ToLong, Floor); 114210333Smitch.hayenga@arm.com 0x4: round_w_d({{ val = Fs_df; }}, 114310333Smitch.hayenga@arm.com ToWord, Round); 114410333Smitch.hayenga@arm.com 0x5: trunc_w_d({{ val = Fs_df; }}, 11457944SGiacomo.Gabrielli@arm.com ToWord, Trunc); 11467944SGiacomo.Gabrielli@arm.com 0x6: ceil_w_d({{ val = Fs_df; }}, 11477944SGiacomo.Gabrielli@arm.com ToWord, Ceil); 11487944SGiacomo.Gabrielli@arm.com 0x7: floor_w_d({{ val = Fs_df; }}, 11491061SN/A ToWord, Floor); 11501061SN/A } 11511061SN/A } 11527897Shestness@cs.utexas.edu 11532292SN/A 0x2: decode FUNCTION_LO { 11541061SN/A 0x1: decode MOVCF { 11551061SN/A format BasicOp { 11561061SN/A 0x0: movf_d({{ 11571060SN/A Fd_df = (getCondCode(FCSR,CC) == 0) ? 11586221Snate@binkert.org Fs_df : Fd_df; 11591060SN/A }}); 11602292SN/A 0x1: movt_d({{ 11612292SN/A Fd_df = (getCondCode(FCSR,CC) == 1) ? 11621060SN/A Fs_df : Fd_df; 11631060SN/A }}); 11641060SN/A } 11652292SN/A } 11661060SN/A 11671681SN/A format BasicOp { 11682292SN/A 0x2: movz_d({{ 11692292SN/A Fd_df = (Rt == 0) ? Fs_df : Fd_df; 11701681SN/A }}); 11711061SN/A 0x3: movn_d({{ 11721061SN/A Fd_df = (Rt != 0) ? Fs_df : Fd_df; 11732292SN/A }}); 11741060SN/A } 11751060SN/A 11761061SN/A format FloatOp { 11771061SN/A 0x5: recip_d({{ Fd_df = 1 / Fs_df; }}); 11786221Snate@binkert.org 0x6: rsqrt_d({{ Fd_df = 1 / sqrt(Fs_df); }}); 11791061SN/A } 11802326SN/A format CP1Unimpl { 11812326SN/A default: unknown(); 11822326SN/A } 11831061SN/A 11842292SN/A } 11852292SN/A 0x4: decode FUNCTION_LO { 11861061SN/A format FloatConvertOp { 11871061SN/A 0x0: cvt_s_d({{ val = Fs_df; }}, ToSingle); 11881061SN/A 0x4: cvt_w_d({{ val = Fs_df; }}, ToWord); 11892326SN/A 0x5: cvt_l_d({{ val = Fs_df; }}, ToLong); 11902326SN/A } 11912292SN/A default: CP1Unimpl::unknown(); 11922326SN/A } 11937897Shestness@cs.utexas.edu 11941061SN/A 0x6: decode FUNCTION_LO { 11951061SN/A format FloatCompareOp { 11961061SN/A 0x0: c_f_d({{ cond = 0; }}, 11972292SN/A DoublePrecision, UnorderedFalse); 11982292SN/A 0x1: c_un_d({{ cond = 0; }}, 11992326SN/A DoublePrecision, UnorderedTrue); 12002292SN/A 0x2: c_eq_d({{ cond = (Fs_df == Ft_df); }}, 12012292SN/A UnorderedFalse); 12022292SN/A 0x3: c_ueq_d({{ cond = (Fs_df == Ft_df); }}, 12032292SN/A UnorderedTrue); 12042292SN/A 0x4: c_olt_d({{ cond = (Fs_df < Ft_df); }}, 12059046SAli.Saidi@ARM.com UnorderedFalse); 12061062SN/A 0x5: c_ult_d({{ cond = (Fs_df < Ft_df); }}, 12077720Sgblack@eecs.umich.edu UnorderedTrue); 12087720Sgblack@eecs.umich.edu 0x6: c_ole_d({{ cond = (Fs_df <= Ft_df); }}, 12092367SN/A UnorderedFalse); 121010032SGiacomo.Gabrielli@arm.com 0x7: c_ule_d({{ cond = (Fs_df <= Ft_df); }}, 121110032SGiacomo.Gabrielli@arm.com UnorderedTrue); 121210032SGiacomo.Gabrielli@arm.com } 121310032SGiacomo.Gabrielli@arm.com } 121410032SGiacomo.Gabrielli@arm.com 12151061SN/A 0x7: decode FUNCTION_LO { 121610032SGiacomo.Gabrielli@arm.com format FloatCompareOp { 121710032SGiacomo.Gabrielli@arm.com 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 121810032SGiacomo.Gabrielli@arm.com UnorderedFalse, QnanException); 121910032SGiacomo.Gabrielli@arm.com 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 122010032SGiacomo.Gabrielli@arm.com UnorderedTrue, QnanException); 12211061SN/A 0x2: c_seq_d({{ cond = (Fs_df == Ft_df); }}, 12221061SN/A UnorderedFalse, QnanException); 12231681SN/A 0x3: c_ngl_d({{ cond = (Fs_df == Ft_df); }}, 12241061SN/A UnorderedTrue, QnanException); 12251061SN/A 0x4: c_lt_d({{ cond = (Fs_df < Ft_df); }}, 12261061SN/A UnorderedFalse, QnanException); 12271061SN/A 0x5: c_nge_d({{ cond = (Fs_df < Ft_df); }}, 12281061SN/A UnorderedTrue, QnanException); 12292326SN/A 0x6: c_le_d({{ cond = (Fs_df <= Ft_df); }}, 12302326SN/A UnorderedFalse, QnanException); 12312326SN/A 0x7: c_ngt_d({{ cond = (Fs_df <= Ft_df); }}, 12322326SN/A UnorderedTrue, QnanException); 12332326SN/A } 12342326SN/A } 12352326SN/A default: CP1Unimpl::unknown(); 12362326SN/A } 12372292SN/A 0x2: CP1Unimpl::unknown(); 12381061SN/A 0x3: CP1Unimpl::unknown(); 12391061SN/A 0x7: CP1Unimpl::unknown(); 12402326SN/A 12411061SN/A //Table A-16 MIPS32 COP1 Encoding of Function 12421062SN/A //Field When rs=W 12432292SN/A 0x4: decode FUNCTION { 12441062SN/A format FloatConvertOp { 12451061SN/A 0x20: cvt_s_w({{ val = Fs_sw; }}, ToSingle); 12464033Sktlim@umich.edu 0x21: cvt_d_w({{ val = Fs_sw; }}, ToDouble); 12474033Sktlim@umich.edu 0x26: CP1Unimpl::cvt_ps_w(); 12482292SN/A } 12492292SN/A default: CP1Unimpl::unknown(); 12508275SAli.Saidi@ARM.com } 125110017Sandreas.hansson@arm.com 125210017Sandreas.hansson@arm.com //Table A-16 MIPS32 COP1 Encoding of Function Field 125310017Sandreas.hansson@arm.com //When rs=L1 12544033Sktlim@umich.edu //Note: "1. Format type L is legal only if 64-bit 125510017Sandreas.hansson@arm.com //floating point operations are enabled." 125610017Sandreas.hansson@arm.com 0x5: decode FUNCTION { 125710017Sandreas.hansson@arm.com format FloatConvertOp { 125810017Sandreas.hansson@arm.com 0x20: cvt_s_l({{ val = Fs_sd; }}, ToSingle); 125910017Sandreas.hansson@arm.com 0x21: cvt_d_l({{ val = Fs_sd; }}, ToDouble); 12604033Sktlim@umich.edu 0x26: CP1Unimpl::cvt_ps_l(); 12611062SN/A } 12624033Sktlim@umich.edu default: CP1Unimpl::unknown(); 12631681SN/A } 12644033Sktlim@umich.edu 12651062SN/A //Table A-17 MIPS64 COP1 Encoding of Function Field 12664033Sktlim@umich.edu //When rs=PS1 12674033Sktlim@umich.edu //Note: "1. Format type PS is legal only if 64-bit 12681061SN/A //floating point operations are enabled. " 12691061SN/A 0x6: decode FUNCTION_HI { 12701061SN/A 0x0: decode FUNCTION_LO { 12711061SN/A format Float64Op { 12721061SN/A 0x0: add_ps({{ 12731061SN/A Fd1_sf = Fs1_sf + Ft2_sf; 12741061SN/A Fd2_sf = Fs2_sf + Ft2_sf; 12752292SN/A }}); 12762292SN/A 0x1: sub_ps({{ 12771681SN/A Fd1_sf = Fs1_sf - Ft2_sf; 12781681SN/A Fd2_sf = Fs2_sf - Ft2_sf; 12792731Sktlim@umich.edu }}); 12802292SN/A 0x2: mul_ps({{ 12812292SN/A Fd1_sf = Fs1_sf * Ft2_sf; 12822292SN/A Fd2_sf = Fs2_sf * Ft2_sf; 12831681SN/A }}); 12841681SN/A 0x5: abs_ps({{ 12851061SN/A Fd1_sf = fabs(Fs1_sf); 12861061SN/A Fd2_sf = fabs(Fs2_sf); 12872326SN/A }}); 12881062SN/A 0x6: mov_ps({{ 12891061SN/A Fd1_sf = Fs1_sf; 12901060SN/A Fd2_sf = Fs2_sf; 12911060SN/A }}); 12921061SN/A 0x7: neg_ps({{ 12931060SN/A Fd1_sf = -(Fs1_sf); 12941061SN/A Fd2_sf = -(Fs2_sf); 12951060SN/A }}); 12961060SN/A default: CP1Unimpl::unknown(); 12971060SN/A } 12981060SN/A } 12991060SN/A 0x1: CP1Unimpl::unknown(); 13001060SN/A 0x2: decode FUNCTION_LO { 13011060SN/A 0x1: decode MOVCF { 13021060SN/A format Float64Op { 13031060SN/A 0x0: movf_ps({{ 13041060SN/A Fd1 = (getCondCode(FCSR, CC) == 0) ? 13051060SN/A Fs1 : Fd1; 13061060SN/A Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 13071060SN/A Fs2 : Fd2; 13081060SN/A }}); 13091060SN/A 0x1: movt_ps({{ 13101060SN/A Fd2 = (getCondCode(FCSR, CC) == 1) ? 13111060SN/A Fs1 : Fd1; 13121060SN/A Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 13131061SN/A Fs2 : Fd2; 13141061SN/A }}); 131510231Ssteve.reinhardt@amd.com } 13167720Sgblack@eecs.umich.edu } 13171060SN/A 13187720Sgblack@eecs.umich.edu format Float64Op { 13191060SN/A 0x2: movz_ps({{ 13202326SN/A Fd1 = (getCondCode(FCSR, CC) == 0) ? 13211060SN/A Fs1 : Fd1; 13221060SN/A Fd2 = (getCondCode(FCSR, CC) == 0) ? 13231060SN/A Fs2 : Fd2; 13241060SN/A }}); 13251060SN/A 0x3: movn_ps({{ 13267720Sgblack@eecs.umich.edu Fd1 = (getCondCode(FCSR, CC) == 1) ? 13271060SN/A Fs1 : Fd1; 13287720Sgblack@eecs.umich.edu Fd2 = (getCondCode(FCSR, CC) == 1) ? 13291060SN/A Fs2 : Fd2; 13302326SN/A }}); 13311060SN/A } 13321060SN/A default: CP1Unimpl::unknown(); 13331060SN/A } 13341060SN/A 0x3: CP1Unimpl::unknown(); 13351060SN/A 0x4: decode FUNCTION_LO { 13361060SN/A 0x0: FloatOp::cvt_s_pu({{ Fd_sf = Fs2_sf; }}); 13371060SN/A default: CP1Unimpl::unknown(); 13381061SN/A } 13391060SN/A 13402326SN/A 0x5: decode FUNCTION_LO { 13411060SN/A 0x0: FloatOp::cvt_s_pl({{ Fd_sf = Fs1_sf; }}); 13422326SN/A format Float64Op { 13432326SN/A 0x4: pll({{ 13442326SN/A Fd_ud = (uint64_t)Fs1_uw << 32 | Ft1_uw; 13452326SN/A }}); 13461060SN/A 0x5: plu({{ 13471060SN/A Fd_ud = (uint64_t)Fs1_uw << 32 | Ft2_uw; 13481060SN/A }}); 13491060SN/A 0x6: pul({{ 13501060SN/A Fd_ud = (uint64_t)Fs2_uw << 32 | Ft1_uw; 13511060SN/A }}); 13521061SN/A 0x7: puu({{ 13531061SN/A Fd_ud = (uint64_t)Fs2_uw << 32 | Ft2_uw; 13541061SN/A }}); 13551061SN/A } 13561061SN/A default: CP1Unimpl::unknown(); 13571061SN/A } 13581061SN/A 13591061SN/A 0x6: decode FUNCTION_LO { 13601060SN/A format FloatPSCompareOp { 13611060SN/A 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 13622326SN/A UnorderedFalse); 13632326SN/A 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 13642292SN/A UnorderedTrue); 13652064SN/A 0x2: c_eq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 13661062SN/A {{ cond2 = (Fs2_sf == Ft2_sf); }}, 13672326SN/A UnorderedFalse); 13681062SN/A 0x3: c_ueq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 13691060SN/A {{ cond2 = (Fs2_sf == Ft2_sf); }}, 13701060SN/A UnorderedTrue); 13711060SN/A 0x4: c_olt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 13721060SN/A {{ cond2 = (Fs2_sf < Ft2_sf); }}, 13731060SN/A UnorderedFalse); 13741061SN/A 0x5: c_ult_ps({{ cond1 = (Fs_sf < Ft_sf); }}, 13751060SN/A {{ cond2 = (Fs2_sf < Ft2_sf); }}, 13761061SN/A UnorderedTrue); 13771060SN/A 0x6: c_ole_ps({{ cond1 = (Fs_sf <= Ft_sf); }}, 13782326SN/A {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 13791060SN/A UnorderedFalse); 13801060SN/A 0x7: c_ule_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 13811061SN/A {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 13821060SN/A UnorderedTrue); 13832292SN/A } 13841061SN/A } 13852292SN/A 13861061SN/A 0x7: decode FUNCTION_LO { 13871062SN/A format FloatPSCompareOp { 13881062SN/A 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 13892292SN/A UnorderedFalse, QnanException); 13901062SN/A 0x1: c_ngle_ps({{ cond1 = 0; }}, 13912292SN/A {{ cond2 = 0; }}, 13922292SN/A UnorderedTrue, QnanException); 13931062SN/A 0x2: c_seq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 13942292SN/A {{ cond2 = (Fs2_sf == Ft2_sf); }}, 13951061SN/A UnorderedFalse, QnanException); 13962292SN/A 0x3: c_ngl_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 13977720Sgblack@eecs.umich.edu {{ cond2 = (Fs2_sf == Ft2_sf); }}, 13987720Sgblack@eecs.umich.edu UnorderedTrue, QnanException); 13991061SN/A 0x4: c_lt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 14002292SN/A {{ cond2 = (Fs2_sf < Ft2_sf); }}, 14011061SN/A UnorderedFalse, QnanException); 14022326SN/A 0x5: c_nge_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 14032326SN/A {{ cond2 = (Fs2_sf < Ft2_sf); }}, 14042326SN/A UnorderedTrue, QnanException); 14052326SN/A 0x6: c_le_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 14062326SN/A {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 14072326SN/A UnorderedFalse, QnanException); 14082326SN/A 0x7: c_ngt_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 14092326SN/A {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 14101060SN/A UnorderedTrue, QnanException); 14111060SN/A } 14121060SN/A } 14131060SN/A } 14141061SN/A } 14151061SN/A default: CP1Unimpl::unknown(); 14161061SN/A } 14171061SN/A } 14182698Sktlim@umich.edu 14192292SN/A //Table A-19 MIPS32 COP2 Encoding of rs Field 14202292SN/A 0x2: decode RS_MSB { 14212292SN/A format CP2Unimpl { 14222698Sktlim@umich.edu 0x0: decode RS_HI { 14231061SN/A 0x0: decode RS_LO { 14241061SN/A 0x0: mfc2(); 14256221Snate@binkert.org 0x2: cfc2(); 14266221Snate@binkert.org 0x3: mfhc2(); 14271681SN/A 0x4: mtc2(); 14286221Snate@binkert.org 0x6: ctc2(); 14292292SN/A 0x7: mftc2(); 14302292SN/A default: unknown(); 14312292SN/A } 14322292SN/A 14332292SN/A 0x1: decode ND { 14342292SN/A 0x0: decode TF { 14352292SN/A 0x0: bc2f(); 14362292SN/A 0x1: bc2t(); 14372292SN/A default: unknown(); 14382292SN/A } 14392292SN/A 14402292SN/A 0x1: decode TF { 14411061SN/A 0x0: bc2fl(); 14421061SN/A 0x1: bc2tl(); 14431061SN/A default: unknown(); 14441061SN/A } 14452292SN/A default: unknown(); 14462292SN/A 14472292SN/A } 14481681SN/A default: unknown(); 14491681SN/A } 14501681SN/A default: unknown(); 14511681SN/A } 14521061SN/A } 14531061SN/A 14542292SN/A //Table A-20 MIPS64 COP1X Encoding of Function Field 1 14552292SN/A //Note: "COP1X instructions are legal only if 64-bit floating point 14561061SN/A //operations are enabled." 14572292SN/A 0x3: decode FUNCTION_HI { 14582292SN/A 0x0: decode FUNCTION_LO { 14591061SN/A format LoadIndexedMemory { 14601061SN/A 0x0: lwxc1({{ Fd_uw = Mem_uw; }}); 14611061SN/A 0x1: ldxc1({{ Fd_ud = Mem_ud; }}); 14622292SN/A 0x5: luxc1({{ Fd_ud = Mem_ud; }}, 14632292SN/A {{ EA = (Rs + Rt) & ~7; }}); 14641061SN/A } 14651061SN/A } 14661061SN/A 14672292SN/A 0x1: decode FUNCTION_LO { 14687720Sgblack@eecs.umich.edu format StoreIndexedMemory { 14692292SN/A 0x0: swxc1({{ Mem_uw = Fs_uw; }}); 14701061SN/A 0x1: sdxc1({{ Mem_ud = Fs_ud; }}); 14711061SN/A 0x5: suxc1({{ Mem_ud = Fs_ud; }}, 14721061SN/A {{ EA = (Rs + Rt) & ~7; }}); 14731061SN/A } 14741061SN/A 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 14752292SN/A } 14762292SN/A 14772292SN/A 0x3: decode FUNCTION_LO { 14782292SN/A 0x6: Float64Op::alnv_ps({{ 14792292SN/A if (Rs<2:0> == 0) { 14802292SN/A Fd_ud = Fs_ud; 14812292SN/A } else if (Rs<2:0> == 4) { 14822292SN/A if (GuestByteOrder == BigEndianByteOrder) 14832292SN/A Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>; 14842292SN/A else 14852292SN/A Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>; 14862292SN/A } else { 14872292SN/A Fd_ud = Fd_ud; 14882292SN/A } 14892292SN/A }}); 14901061SN/A } 14912292SN/A 14922292SN/A format FloatAccOp { 14932292SN/A 0x4: decode FUNCTION_LO { 14942292SN/A 0x0: madd_s({{ Fd_sf = (Fs_sf * Ft_sf) + Fr_sf; }}); 14952292SN/A 0x1: madd_d({{ Fd_df = (Fs_df * Ft_df) + Fr_df; }}); 14962292SN/A 0x6: madd_ps({{ 14976221Snate@binkert.org Fd1_sf = (Fs1_df * Ft1_df) + Fr1_df; 14982292SN/A Fd2_sf = (Fs2_df * Ft2_df) + Fr2_df; 14992292SN/A }}); 15006221Snate@binkert.org } 15012292SN/A 15026221Snate@binkert.org 0x5: decode FUNCTION_LO { 15036221Snate@binkert.org 0x0: msub_s({{ Fd_sf = (Fs_sf * Ft_sf) - Fr_sf; }}); 15042292SN/A 0x1: msub_d({{ Fd_df = (Fs_df * Ft_df) - Fr_df; }}); 15052292SN/A 0x6: msub_ps({{ 15062292SN/A Fd1_sf = (Fs1_df * Ft1_df) - Fr1_df; 15072292SN/A Fd2_sf = (Fs2_df * Ft2_df) - Fr2_df; 15082292SN/A }}); 15099046SAli.Saidi@ARM.com } 15102326SN/A 15112326SN/A 0x6: decode FUNCTION_LO { 15122292SN/A 0x0: nmadd_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) - Fr_sf; }}); 15132292SN/A 0x1: nmadd_d({{ Fd_df = (-1 * Fs_df * Ft_df) - Fr_df; }}); 15142292SN/A 0x6: nmadd_ps({{ 15152292SN/A Fd1_sf = -((Fs1_df * Ft1_df) + Fr1_df); 15162292SN/A Fd2_sf = -((Fs2_df * Ft2_df) + Fr2_df); 15177720Sgblack@eecs.umich.edu }}); 15182292SN/A } 15197720Sgblack@eecs.umich.edu 15202292SN/A 0x7: decode FUNCTION_LO { 15212292SN/A 0x0: nmsub_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) + Fr_sf; }}); 15222292SN/A 0x1: nmsub_d({{ Fd_df = (-1 * Fs_df * Ft_df) + Fr_df; }}); 15232292SN/A 0x6: nmsub_ps({{ 15242292SN/A Fd1_sf = -((Fs1_df * Ft1_df) - Fr1_df); 15252292SN/A Fd2_sf = -((Fs2_df * Ft2_df) - Fr2_df); 15269046SAli.Saidi@ARM.com }}); 15272292SN/A } 15282292SN/A } 15292292SN/A } 15302292SN/A 15312292SN/A format Branch { 15322292SN/A 0x4: beql({{ cond = (Rs_sw == Rt_sw); }}, Likely); 15332292SN/A 0x5: bnel({{ cond = (Rs_sw != Rt_sw); }}, Likely); 15342292SN/A 0x6: blezl({{ cond = (Rs_sw <= 0); }}, Likely); 15352348SN/A 0x7: bgtzl({{ cond = (Rs_sw > 0); }}, Likely); 15362348SN/A } 15372348SN/A } 15382348SN/A 15392348SN/A 0x3: decode OPCODE_LO { 15402348SN/A //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 15412348SN/A 0x4: decode FUNCTION_HI { 15422348SN/A 0x0: decode FUNCTION_LO { 15432348SN/A 0x2: IntOp::mul({{ 15442348SN/A int64_t temp1 = Rs_sd * Rt_sd; 15452348SN/A Rd_sw = temp1<31:0>; 15462348SN/A }}, IntMultOp); 15472348SN/A 15482348SN/A format HiLoRdSelValOp { 15492348SN/A 0x0: madd({{ 15502348SN/A val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 15519046SAli.Saidi@ARM.com (Rs_sd * Rt_sd); 15522348SN/A }}, IntMultOp); 15532348SN/A 0x1: maddu({{ 15542348SN/A val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 15552348SN/A (Rs_ud * Rt_ud); 15562348SN/A }}, IntMultOp); 15572348SN/A 0x4: msub({{ 15582348SN/A val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 15597720Sgblack@eecs.umich.edu (Rs_sd * Rt_sd); 15602348SN/A }}, IntMultOp); 15617720Sgblack@eecs.umich.edu 0x5: msubu({{ 15622348SN/A val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 15632348SN/A (Rs_ud * Rt_ud); 15642348SN/A }}, IntMultOp); 15652348SN/A } 15662348SN/A } 15672348SN/A 15689046SAli.Saidi@ARM.com 0x4: decode FUNCTION_LO { 15692348SN/A format BasicOp { 15702348SN/A 0x0: clz({{ 15712348SN/A int cnt = 32; 15722348SN/A for (int idx = 31; idx >= 0; idx--) { 15732348SN/A if (Rs<idx:idx> == 1) { 15742348SN/A cnt = 31 - idx; 15752348SN/A break; 15762292SN/A } 15779944Smatt.horsnell@ARM.com } 15789944Smatt.horsnell@ARM.com Rd_uw = cnt; 1579 }}); 1580 0x1: clo({{ 1581 int cnt = 32; 1582 for (int idx = 31; idx >= 0; idx--) { 1583 if (Rs<idx:idx> == 0) { 1584 cnt = 31 - idx; 1585 break; 1586 } 1587 } 1588 Rd_uw = cnt; 1589 }}); 1590 } 1591 } 1592 1593 0x7: decode FUNCTION_LO { 1594 0x7: FailUnimpl::sdbbp(); 1595 } 1596 } 1597 1598 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1599 //of the Architecture 1600 0x7: decode FUNCTION_HI { 1601 0x0: decode FUNCTION_LO { 1602 format BasicOp { 1603 0x0: ext({{ Rt_uw = bits(Rs_uw, MSB+LSB, LSB); }}); 1604 0x4: ins({{ 1605 Rt_uw = bits(Rt_uw, 31, MSB+1) << (MSB+1) | 1606 bits(Rs_uw, MSB-LSB, 0) << LSB | 1607 bits(Rt_uw, LSB-1, 0); 1608 }}); 1609 } 1610 } 1611 1612 0x1: decode FUNCTION_LO { 1613 format MT_Control { 1614 0x0: fork({{ 1615 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1616 }}, UserMode); 1617 0x1: yield({{ 1618 Rd_sw = yieldThread(xc->tcBase(), fault, Rs_sw, 1619 YQMask); 1620 }}, UserMode); 1621 } 1622 1623 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1624 0x2: decode OP_HI { 1625 0x0: decode OP_LO { 1626 format LoadIndexedMemory { 1627 0x0: lwx({{ Rd_sw = Mem_sw; }}); 1628 0x4: lhx({{ Rd_sw = Mem_sh; }}); 1629 0x6: lbux({{ Rd_uw = Mem_ub; }}); 1630 } 1631 } 1632 } 1633 0x4: DspIntOp::insv({{ 1634 int pos = dspctl<5:0>; 1635 int size = dspctl<12:7> - 1; 1636 Rt_uw = insertBits(Rt_uw, pos+size, 1637 pos, Rs_uw<size:0>); 1638 }}); 1639 } 1640 1641 0x2: decode FUNCTION_LO { 1642 1643 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1644 //(DSP ASE MANUAL) 1645 0x0: decode OP_HI { 1646 0x0: decode OP_LO { 1647 format DspIntOp { 1648 0x0: addu_qb({{ 1649 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1650 NOSATURATE, UNSIGNED, &dspctl); 1651 }}); 1652 0x1: subu_qb({{ 1653 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1654 NOSATURATE, UNSIGNED, &dspctl); 1655 }}); 1656 0x4: addu_s_qb({{ 1657 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1658 SATURATE, UNSIGNED, &dspctl); 1659 }}); 1660 0x5: subu_s_qb({{ 1661 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1662 SATURATE, UNSIGNED, &dspctl); 1663 }}); 1664 0x6: muleu_s_ph_qbl({{ 1665 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1666 MODE_L, &dspctl); 1667 }}, IntMultOp); 1668 0x7: muleu_s_ph_qbr({{ 1669 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1670 MODE_R, &dspctl); 1671 }}, IntMultOp); 1672 } 1673 } 1674 0x1: decode OP_LO { 1675 format DspIntOp { 1676 0x0: addu_ph({{ 1677 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1678 NOSATURATE, UNSIGNED, &dspctl); 1679 }}); 1680 0x1: subu_ph({{ 1681 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1682 NOSATURATE, UNSIGNED, &dspctl); 1683 }}); 1684 0x2: addq_ph({{ 1685 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1686 NOSATURATE, SIGNED, &dspctl); 1687 }}); 1688 0x3: subq_ph({{ 1689 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1690 NOSATURATE, SIGNED, &dspctl); 1691 }}); 1692 0x4: addu_s_ph({{ 1693 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1694 SATURATE, UNSIGNED, &dspctl); 1695 }}); 1696 0x5: subu_s_ph({{ 1697 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1698 SATURATE, UNSIGNED, &dspctl); 1699 }}); 1700 0x6: addq_s_ph({{ 1701 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1702 SATURATE, SIGNED, &dspctl); 1703 }}); 1704 0x7: subq_s_ph({{ 1705 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1706 SATURATE, SIGNED, &dspctl); 1707 }}); 1708 } 1709 } 1710 0x2: decode OP_LO { 1711 format DspIntOp { 1712 0x0: addsc({{ 1713 int64_t dresult; 1714 dresult = Rs_ud + Rt_ud; 1715 Rd_sw = dresult<31:0>; 1716 dspctl = insertBits(dspctl, 13, 13, 1717 dresult<32:32>); 1718 }}); 1719 0x1: addwc({{ 1720 int64_t dresult; 1721 dresult = Rs_sd + Rt_sd + dspctl<13:13>; 1722 Rd_sw = dresult<31:0>; 1723 if (dresult<32:32> != dresult<31:31>) 1724 dspctl = insertBits(dspctl, 20, 20, 1); 1725 }}); 1726 0x2: modsub({{ 1727 Rd_sw = (Rs_sw == 0) ? Rt_sw<23:8> : 1728 Rs_sw - Rt_sw<7:0>; 1729 }}); 1730 0x4: raddu_w_qb({{ 1731 Rd_uw = Rs_uw<31:24> + Rs_uw<23:16> + 1732 Rs_uw<15:8> + Rs_uw<7:0>; 1733 }}); 1734 0x6: addq_s_w({{ 1735 Rd_sw = dspAdd(Rs_sw, Rt_sw, SIMD_FMT_W, 1736 SATURATE, SIGNED, &dspctl); 1737 }}); 1738 0x7: subq_s_w({{ 1739 Rd_sw = dspSub(Rs_sw, Rt_sw, SIMD_FMT_W, 1740 SATURATE, SIGNED, &dspctl); 1741 }}); 1742 } 1743 } 1744 0x3: decode OP_LO { 1745 format DspIntOp { 1746 0x4: muleq_s_w_phl({{ 1747 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1748 MODE_L, &dspctl); 1749 }}, IntMultOp); 1750 0x5: muleq_s_w_phr({{ 1751 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1752 MODE_R, &dspctl); 1753 }}, IntMultOp); 1754 0x6: mulq_s_ph({{ 1755 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1756 SATURATE, NOROUND, &dspctl); 1757 }}, IntMultOp); 1758 0x7: mulq_rs_ph({{ 1759 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1760 SATURATE, ROUND, &dspctl); 1761 }}, IntMultOp); 1762 } 1763 } 1764 } 1765 1766 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1767 //(DSP ASE MANUAL) 1768 0x1: decode OP_HI { 1769 0x0: decode OP_LO { 1770 format DspIntOp { 1771 0x0: cmpu_eq_qb({{ 1772 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1773 UNSIGNED, CMP_EQ, &dspctl); 1774 }}); 1775 0x1: cmpu_lt_qb({{ 1776 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1777 UNSIGNED, CMP_LT, &dspctl); 1778 }}); 1779 0x2: cmpu_le_qb({{ 1780 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1781 UNSIGNED, CMP_LE, &dspctl); 1782 }}); 1783 0x3: pick_qb({{ 1784 Rd_uw = dspPick(Rs_uw, Rt_uw, 1785 SIMD_FMT_QB, &dspctl); 1786 }}); 1787 0x4: cmpgu_eq_qb({{ 1788 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1789 UNSIGNED, CMP_EQ ); 1790 }}); 1791 0x5: cmpgu_lt_qb({{ 1792 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1793 UNSIGNED, CMP_LT); 1794 }}); 1795 0x6: cmpgu_le_qb({{ 1796 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1797 UNSIGNED, CMP_LE); 1798 }}); 1799 } 1800 } 1801 0x1: decode OP_LO { 1802 format DspIntOp { 1803 0x0: cmp_eq_ph({{ 1804 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1805 SIGNED, CMP_EQ, &dspctl); 1806 }}); 1807 0x1: cmp_lt_ph({{ 1808 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1809 SIGNED, CMP_LT, &dspctl); 1810 }}); 1811 0x2: cmp_le_ph({{ 1812 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1813 SIGNED, CMP_LE, &dspctl); 1814 }}); 1815 0x3: pick_ph({{ 1816 Rd_uw = dspPick(Rs_uw, Rt_uw, 1817 SIMD_FMT_PH, &dspctl); 1818 }}); 1819 0x4: precrq_qb_ph({{ 1820 Rd_uw = Rs_uw<31:24> << 24 | 1821 Rs_uw<15:8> << 16 | 1822 Rt_uw<31:24> << 8 | 1823 Rt_uw<15:8>; 1824 }}); 1825 0x5: precr_qb_ph({{ 1826 Rd_uw = Rs_uw<23:16> << 24 | 1827 Rs_uw<7:0> << 16 | 1828 Rt_uw<23:16> << 8 | 1829 Rt_uw<7:0>; 1830 }}); 1831 0x6: packrl_ph({{ 1832 Rd_uw = dspPack(Rs_uw, Rt_uw, SIMD_FMT_PH); 1833 }}); 1834 0x7: precrqu_s_qb_ph({{ 1835 Rd_uw = dspPrecrqu(Rs_uw, Rt_uw, &dspctl); 1836 }}); 1837 } 1838 } 1839 0x2: decode OP_LO { 1840 format DspIntOp { 1841 0x4: precrq_ph_w({{ 1842 Rd_uw = Rs_uw<31:16> << 16 | Rt_uw<31:16>; 1843 }}); 1844 0x5: precrq_rs_ph_w({{ 1845 Rd_uw = dspPrecrq(Rs_uw, Rt_uw, 1846 SIMD_FMT_W, &dspctl); 1847 }}); 1848 } 1849 } 1850 0x3: decode OP_LO { 1851 format DspIntOp { 1852 0x0: cmpgdu_eq_qb({{ 1853 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1854 UNSIGNED, CMP_EQ, &dspctl); 1855 }}); 1856 0x1: cmpgdu_lt_qb({{ 1857 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1858 UNSIGNED, CMP_LT, &dspctl); 1859 }}); 1860 0x2: cmpgdu_le_qb({{ 1861 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1862 UNSIGNED, CMP_LE, &dspctl); 1863 }}); 1864 0x6: precr_sra_ph_w({{ 1865 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1866 SIMD_FMT_W, NOROUND); 1867 }}); 1868 0x7: precr_sra_r_ph_w({{ 1869 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1870 SIMD_FMT_W, ROUND); 1871 }}); 1872 } 1873 } 1874 } 1875 1876 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1877 //(DSP ASE MANUAL) 1878 0x2: decode OP_HI { 1879 0x0: decode OP_LO { 1880 format DspIntOp { 1881 0x1: absq_s_qb({{ 1882 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_QB, &dspctl); 1883 }}); 1884 0x2: repl_qb({{ 1885 Rd_uw = RS_RT<7:0> << 24 | 1886 RS_RT<7:0> << 16 | 1887 RS_RT<7:0> << 8 | 1888 RS_RT<7:0>; 1889 }}); 1890 0x3: replv_qb({{ 1891 Rd_sw = Rt_uw<7:0> << 24 | 1892 Rt_uw<7:0> << 16 | 1893 Rt_uw<7:0> << 8 | 1894 Rt_uw<7:0>; 1895 }}); 1896 0x4: precequ_ph_qbl({{ 1897 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1898 SIMD_FMT_PH, SIGNED, MODE_L); 1899 }}); 1900 0x5: precequ_ph_qbr({{ 1901 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1902 SIMD_FMT_PH, SIGNED, MODE_R); 1903 }}); 1904 0x6: precequ_ph_qbla({{ 1905 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1906 SIMD_FMT_PH, SIGNED, MODE_LA); 1907 }}); 1908 0x7: precequ_ph_qbra({{ 1909 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1910 SIMD_FMT_PH, SIGNED, MODE_RA); 1911 }}); 1912 } 1913 } 1914 0x1: decode OP_LO { 1915 format DspIntOp { 1916 0x1: absq_s_ph({{ 1917 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_PH, &dspctl); 1918 }}); 1919 0x2: repl_ph({{ 1920 Rd_uw = (sext<10>(RS_RT))<15:0> << 16 | 1921 (sext<10>(RS_RT))<15:0>; 1922 }}); 1923 0x3: replv_ph({{ 1924 Rd_uw = Rt_uw<15:0> << 16 | 1925 Rt_uw<15:0>; 1926 }}); 1927 0x4: preceq_w_phl({{ 1928 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1929 SIMD_FMT_W, SIGNED, MODE_L); 1930 }}); 1931 0x5: preceq_w_phr({{ 1932 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1933 SIMD_FMT_W, SIGNED, MODE_R); 1934 }}); 1935 } 1936 } 1937 0x2: decode OP_LO { 1938 format DspIntOp { 1939 0x1: absq_s_w({{ 1940 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_W, &dspctl); 1941 }}); 1942 } 1943 } 1944 0x3: decode OP_LO { 1945 0x3: IntOp::bitrev({{ 1946 Rd_uw = bitrev( Rt_uw<15:0> ); 1947 }}); 1948 format DspIntOp { 1949 0x4: preceu_ph_qbl({{ 1950 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1951 UNSIGNED, SIMD_FMT_PH, 1952 UNSIGNED, MODE_L); 1953 }}); 1954 0x5: preceu_ph_qbr({{ 1955 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1956 UNSIGNED, SIMD_FMT_PH, 1957 UNSIGNED, MODE_R ); 1958 }}); 1959 0x6: preceu_ph_qbla({{ 1960 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1961 UNSIGNED, SIMD_FMT_PH, 1962 UNSIGNED, MODE_LA ); 1963 }}); 1964 0x7: preceu_ph_qbra({{ 1965 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1966 UNSIGNED, SIMD_FMT_PH, 1967 UNSIGNED, MODE_RA); 1968 }}); 1969 } 1970 } 1971 } 1972 1973 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 1974 //(DSP ASE MANUAL) 1975 0x3: decode OP_HI { 1976 0x0: decode OP_LO { 1977 format DspIntOp { 1978 0x0: shll_qb({{ 1979 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_QB, 1980 NOSATURATE, UNSIGNED, &dspctl); 1981 }}); 1982 0x1: shrl_qb({{ 1983 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_QB, 1984 UNSIGNED); 1985 }}); 1986 0x2: shllv_qb({{ 1987 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_QB, 1988 NOSATURATE, UNSIGNED, &dspctl); 1989 }}); 1990 0x3: shrlv_qb({{ 1991 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_QB, 1992 UNSIGNED); 1993 }}); 1994 0x4: shra_qb({{ 1995 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 1996 NOROUND, SIGNED, &dspctl); 1997 }}); 1998 0x5: shra_r_qb({{ 1999 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 2000 ROUND, SIGNED, &dspctl); 2001 }}); 2002 0x6: shrav_qb({{ 2003 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2004 NOROUND, SIGNED, &dspctl); 2005 }}); 2006 0x7: shrav_r_qb({{ 2007 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2008 ROUND, SIGNED, &dspctl); 2009 }}); 2010 } 2011 } 2012 0x1: decode OP_LO { 2013 format DspIntOp { 2014 0x0: shll_ph({{ 2015 Rd_uw = dspShll(Rt_uw, RS, SIMD_FMT_PH, 2016 NOSATURATE, SIGNED, &dspctl); 2017 }}); 2018 0x1: shra_ph({{ 2019 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2020 NOROUND, SIGNED, &dspctl); 2021 }}); 2022 0x2: shllv_ph({{ 2023 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2024 NOSATURATE, SIGNED, &dspctl); 2025 }}); 2026 0x3: shrav_ph({{ 2027 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2028 NOROUND, SIGNED, &dspctl); 2029 }}); 2030 0x4: shll_s_ph({{ 2031 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_PH, 2032 SATURATE, SIGNED, &dspctl); 2033 }}); 2034 0x5: shra_r_ph({{ 2035 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2036 ROUND, SIGNED, &dspctl); 2037 }}); 2038 0x6: shllv_s_ph({{ 2039 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2040 SATURATE, SIGNED, &dspctl); 2041 }}); 2042 0x7: shrav_r_ph({{ 2043 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2044 ROUND, SIGNED, &dspctl); 2045 }}); 2046 } 2047 } 2048 0x2: decode OP_LO { 2049 format DspIntOp { 2050 0x4: shll_s_w({{ 2051 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_W, 2052 SATURATE, SIGNED, &dspctl); 2053 }}); 2054 0x5: shra_r_w({{ 2055 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_W, 2056 ROUND, SIGNED, &dspctl); 2057 }}); 2058 0x6: shllv_s_w({{ 2059 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_W, 2060 SATURATE, SIGNED, &dspctl); 2061 }}); 2062 0x7: shrav_r_w({{ 2063 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_W, 2064 ROUND, SIGNED, &dspctl); 2065 }}); 2066 } 2067 } 2068 0x3: decode OP_LO { 2069 format DspIntOp { 2070 0x1: shrl_ph({{ 2071 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_PH, 2072 UNSIGNED); 2073 }}); 2074 0x3: shrlv_ph({{ 2075 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_PH, 2076 UNSIGNED); 2077 }}); 2078 } 2079 } 2080 } 2081 } 2082 2083 0x3: decode FUNCTION_LO { 2084 2085 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2086 //(DSP ASE Rev2 Manual) 2087 0x0: decode OP_HI { 2088 0x0: decode OP_LO { 2089 format DspIntOp { 2090 0x0: adduh_qb({{ 2091 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2092 NOROUND, UNSIGNED); 2093 }}); 2094 0x1: subuh_qb({{ 2095 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2096 NOROUND, UNSIGNED); 2097 }}); 2098 0x2: adduh_r_qb({{ 2099 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2100 ROUND, UNSIGNED); 2101 }}); 2102 0x3: subuh_r_qb({{ 2103 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2104 ROUND, UNSIGNED); 2105 }}); 2106 } 2107 } 2108 0x1: decode OP_LO { 2109 format DspIntOp { 2110 0x0: addqh_ph({{ 2111 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2112 NOROUND, SIGNED); 2113 }}); 2114 0x1: subqh_ph({{ 2115 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2116 NOROUND, SIGNED); 2117 }}); 2118 0x2: addqh_r_ph({{ 2119 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2120 ROUND, SIGNED); 2121 }}); 2122 0x3: subqh_r_ph({{ 2123 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2124 ROUND, SIGNED); 2125 }}); 2126 0x4: mul_ph({{ 2127 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2128 NOSATURATE, &dspctl); 2129 }}, IntMultOp); 2130 0x6: mul_s_ph({{ 2131 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2132 SATURATE, &dspctl); 2133 }}, IntMultOp); 2134 } 2135 } 2136 0x2: decode OP_LO { 2137 format DspIntOp { 2138 0x0: addqh_w({{ 2139 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2140 NOROUND, SIGNED); 2141 }}); 2142 0x1: subqh_w({{ 2143 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2144 NOROUND, SIGNED); 2145 }}); 2146 0x2: addqh_r_w({{ 2147 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2148 ROUND, SIGNED); 2149 }}); 2150 0x3: subqh_r_w({{ 2151 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2152 ROUND, SIGNED); 2153 }}); 2154 0x6: mulq_s_w({{ 2155 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2156 SATURATE, NOROUND, &dspctl); 2157 }}, IntMultOp); 2158 0x7: mulq_rs_w({{ 2159 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2160 SATURATE, ROUND, &dspctl); 2161 }}, IntMultOp); 2162 } 2163 } 2164 } 2165 } 2166 2167 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2168 0x4: decode SA { 2169 format BasicOp { 2170 0x02: wsbh({{ 2171 Rd_uw = Rt_uw<23:16> << 24 | 2172 Rt_uw<31:24> << 16 | 2173 Rt_uw<7:0> << 8 | 2174 Rt_uw<15:8>; 2175 }}); 2176 0x10: seb({{ Rd_sw = Rt_sb; }}); 2177 0x18: seh({{ Rd_sw = Rt_sh; }}); 2178 } 2179 } 2180 2181 0x6: decode FUNCTION_LO { 2182 2183 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2184 //(DSP ASE MANUAL) 2185 0x0: decode OP_HI { 2186 0x0: decode OP_LO { 2187 format DspHiLoOp { 2188 0x0: dpa_w_ph({{ 2189 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2190 SIMD_FMT_PH, SIGNED, MODE_L); 2191 }}, IntMultOp); 2192 0x1: dps_w_ph({{ 2193 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2194 SIMD_FMT_PH, SIGNED, MODE_L); 2195 }}, IntMultOp); 2196 0x2: mulsa_w_ph({{ 2197 dspac = dspMulsa(dspac, Rs_sw, Rt_sw, 2198 ACDST, SIMD_FMT_PH ); 2199 }}, IntMultOp); 2200 0x3: dpau_h_qbl({{ 2201 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2202 SIMD_FMT_QB, UNSIGNED, MODE_L); 2203 }}, IntMultOp); 2204 0x4: dpaq_s_w_ph({{ 2205 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2206 ACDST, SIMD_FMT_PH, 2207 SIMD_FMT_W, NOSATURATE, 2208 MODE_L, &dspctl); 2209 }}, IntMultOp); 2210 0x5: dpsq_s_w_ph({{ 2211 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2212 ACDST, SIMD_FMT_PH, 2213 SIMD_FMT_W, NOSATURATE, 2214 MODE_L, &dspctl); 2215 }}, IntMultOp); 2216 0x6: mulsaq_s_w_ph({{ 2217 dspac = dspMulsaq(dspac, Rs_sw, Rt_sw, 2218 ACDST, SIMD_FMT_PH, 2219 &dspctl); 2220 }}, IntMultOp); 2221 0x7: dpau_h_qbr({{ 2222 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2223 SIMD_FMT_QB, UNSIGNED, MODE_R); 2224 }}, IntMultOp); 2225 } 2226 } 2227 0x1: decode OP_LO { 2228 format DspHiLoOp { 2229 0x0: dpax_w_ph({{ 2230 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2231 SIMD_FMT_PH, SIGNED, MODE_X); 2232 }}, IntMultOp); 2233 0x1: dpsx_w_ph({{ 2234 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2235 SIMD_FMT_PH, SIGNED, MODE_X); 2236 }}, IntMultOp); 2237 0x3: dpsu_h_qbl({{ 2238 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2239 SIMD_FMT_QB, UNSIGNED, MODE_L); 2240 }}, IntMultOp); 2241 0x4: dpaq_sa_l_w({{ 2242 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2243 ACDST, SIMD_FMT_W, 2244 SIMD_FMT_L, SATURATE, 2245 MODE_L, &dspctl); 2246 }}, IntMultOp); 2247 0x5: dpsq_sa_l_w({{ 2248 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2249 ACDST, SIMD_FMT_W, 2250 SIMD_FMT_L, SATURATE, 2251 MODE_L, &dspctl); 2252 }}, IntMultOp); 2253 0x7: dpsu_h_qbr({{ 2254 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2255 SIMD_FMT_QB, UNSIGNED, MODE_R); 2256 }}, IntMultOp); 2257 } 2258 } 2259 0x2: decode OP_LO { 2260 format DspHiLoOp { 2261 0x0: maq_sa_w_phl({{ 2262 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2263 ACDST, SIMD_FMT_PH, 2264 MODE_L, SATURATE, &dspctl); 2265 }}, IntMultOp); 2266 0x2: maq_sa_w_phr({{ 2267 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2268 ACDST, SIMD_FMT_PH, 2269 MODE_R, SATURATE, &dspctl); 2270 }}, IntMultOp); 2271 0x4: maq_s_w_phl({{ 2272 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2273 ACDST, SIMD_FMT_PH, 2274 MODE_L, NOSATURATE, &dspctl); 2275 }}, IntMultOp); 2276 0x6: maq_s_w_phr({{ 2277 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2278 ACDST, SIMD_FMT_PH, 2279 MODE_R, NOSATURATE, &dspctl); 2280 }}, IntMultOp); 2281 } 2282 } 2283 0x3: decode OP_LO { 2284 format DspHiLoOp { 2285 0x0: dpaqx_s_w_ph({{ 2286 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2287 ACDST, SIMD_FMT_PH, 2288 SIMD_FMT_W, NOSATURATE, 2289 MODE_X, &dspctl); 2290 }}, IntMultOp); 2291 0x1: dpsqx_s_w_ph({{ 2292 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2293 ACDST, SIMD_FMT_PH, 2294 SIMD_FMT_W, NOSATURATE, 2295 MODE_X, &dspctl); 2296 }}, IntMultOp); 2297 0x2: dpaqx_sa_w_ph({{ 2298 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2299 ACDST, SIMD_FMT_PH, 2300 SIMD_FMT_W, SATURATE, 2301 MODE_X, &dspctl); 2302 }}, IntMultOp); 2303 0x3: dpsqx_sa_w_ph({{ 2304 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2305 ACDST, SIMD_FMT_PH, 2306 SIMD_FMT_W, SATURATE, 2307 MODE_X, &dspctl); 2308 }}, IntMultOp); 2309 } 2310 } 2311 } 2312 2313 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2314 0x1: decode OP_HI { 2315 0x0: decode OP_LO { 2316 format IntOp { 2317 0x0: append({{ 2318 Rt_uw = (Rt_uw << RD) | bits(Rs_uw, RD - 1, 0); 2319 }}); 2320 0x1: prepend({{ 2321 Rt_uw = (Rt_uw >> RD) | 2322 (bits(Rs_uw, RD - 1, 0) << (32 - RD)); 2323 }}); 2324 } 2325 } 2326 0x2: decode OP_LO { 2327 format IntOp { 2328 0x0: balign({{ 2329 Rt_uw = (Rt_uw << (8 * BP)) | 2330 (Rs_uw >> (8 * (4 - BP))); 2331 }}); 2332 } 2333 } 2334 } 2335 2336 } 2337 0x7: decode FUNCTION_LO { 2338 2339 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2340 //(DSP ASE MANUAL) 2341 0x0: decode OP_HI { 2342 0x0: decode OP_LO { 2343 format DspHiLoOp { 2344 0x0: extr_w({{ 2345 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2346 NOROUND, NOSATURATE, &dspctl); 2347 }}); 2348 0x1: extrv_w({{ 2349 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2350 NOROUND, NOSATURATE, &dspctl); 2351 }}); 2352 0x2: extp({{ 2353 Rt_uw = dspExtp(dspac, RS, &dspctl); 2354 }}); 2355 0x3: extpv({{ 2356 Rt_uw = dspExtp(dspac, Rs_uw, &dspctl); 2357 }}); 2358 0x4: extr_r_w({{ 2359 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2360 ROUND, NOSATURATE, &dspctl); 2361 }}); 2362 0x5: extrv_r_w({{ 2363 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2364 ROUND, NOSATURATE, &dspctl); 2365 }}); 2366 0x6: extr_rs_w({{ 2367 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2368 ROUND, SATURATE, &dspctl); 2369 }}); 2370 0x7: extrv_rs_w({{ 2371 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2372 ROUND, SATURATE, &dspctl); 2373 }}); 2374 } 2375 } 2376 0x1: decode OP_LO { 2377 format DspHiLoOp { 2378 0x2: extpdp({{ 2379 Rt_uw = dspExtpd(dspac, RS, &dspctl); 2380 }}); 2381 0x3: extpdpv({{ 2382 Rt_uw = dspExtpd(dspac, Rs_uw, &dspctl); 2383 }}); 2384 0x6: extr_s_h({{ 2385 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, RS, 2386 NOROUND, SATURATE, &dspctl); 2387 }}); 2388 0x7: extrv_s_h({{ 2389 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, Rs_uw, 2390 NOROUND, SATURATE, &dspctl); 2391 }}); 2392 } 2393 } 2394 0x2: decode OP_LO { 2395 format DspIntOp { 2396 0x2: rddsp({{ 2397 Rd_uw = readDSPControl(&dspctl, RDDSPMASK); 2398 }}); 2399 0x3: wrdsp({{ 2400 writeDSPControl(&dspctl, Rs_uw, WRDSPMASK); 2401 }}); 2402 } 2403 } 2404 0x3: decode OP_LO { 2405 format DspHiLoOp { 2406 0x2: shilo({{ 2407 if (sext<6>(HILOSA) < 0) { 2408 dspac = (uint64_t)dspac << 2409 -sext<6>(HILOSA); 2410 } else { 2411 dspac = (uint64_t)dspac >> 2412 sext<6>(HILOSA); 2413 } 2414 }}); 2415 0x3: shilov({{ 2416 if (sext<6>(Rs_sw<5:0>) < 0) { 2417 dspac = (uint64_t)dspac << 2418 -sext<6>(Rs_sw<5:0>); 2419 } else { 2420 dspac = (uint64_t)dspac >> 2421 sext<6>(Rs_sw<5:0>); 2422 } 2423 }}); 2424 0x7: mthlip({{ 2425 dspac = dspac << 32; 2426 dspac |= Rs_uw; 2427 dspctl = insertBits(dspctl, 5, 0, 2428 dspctl<5:0> + 32); 2429 }}); 2430 } 2431 } 2432 } 2433 0x3: decode OP default FailUnimpl::rdhwr() { 2434 0x0: decode FullSystemInt { 2435 0: decode RD { 2436 29: BasicOp::rdhwr_se({{ Rt = TpValue; }}); 2437 } 2438 } 2439 } 2440 } 2441 } 2442 } 2443 2444 0x4: decode OPCODE_LO { 2445 format LoadMemory { 2446 0x0: lb({{ Rt_sw = Mem_sb; }}); 2447 0x1: lh({{ Rt_sw = Mem_sh; }}); 2448 0x3: lw({{ Rt_sw = Mem_sw; }}); 2449 0x4: lbu({{ Rt_uw = Mem_ub;}}); 2450 0x5: lhu({{ Rt_uw = Mem_uh; }}); 2451 } 2452 2453 format LoadUnalignedMemory { 2454 0x2: lwl({{ 2455 uint32_t mem_shift = 24 - (8 * byte_offset); 2456 Rt_uw = mem_word << mem_shift | (Rt_uw & mask(mem_shift)); 2457 }}); 2458 0x6: lwr({{ 2459 uint32_t mem_shift = 8 * byte_offset; 2460 Rt_uw = (Rt_uw & (mask(mem_shift) << (32 - mem_shift))) | 2461 (mem_word >> mem_shift); 2462 }}); 2463 } 2464 } 2465 2466 0x5: decode OPCODE_LO { 2467 format StoreMemory { 2468 0x0: sb({{ Mem_ub = Rt<7:0>; }}); 2469 0x1: sh({{ Mem_uh = Rt<15:0>; }}); 2470 0x3: sw({{ Mem_uw = Rt<31:0>; }}); 2471 } 2472 2473 format StoreUnalignedMemory { 2474 0x2: swl({{ 2475 uint32_t reg_shift = 24 - (8 * byte_offset); 2476 uint32_t mem_shift = 32 - reg_shift; 2477 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2478 (Rt_uw >> reg_shift); 2479 }}); 2480 0x6: swr({{ 2481 uint32_t reg_shift = 8 * byte_offset; 2482 mem_word = Rt_uw << reg_shift | 2483 (mem_word & (mask(reg_shift))); 2484 }}); 2485 } 2486 format CP0Control { 2487 0x7: cache({{ 2488 //Addr CacheEA = Rs_uw + OFFSET; 2489 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2490 }}); 2491 } 2492 } 2493 2494 0x6: decode OPCODE_LO { 2495 format LoadMemory { 2496 0x0: ll({{ Rt_uw = Mem_uw; }}, mem_flags=LLSC); 2497 0x1: lwc1({{ Ft_uw = Mem_uw; }}); 2498 0x5: ldc1({{ Ft_ud = Mem_ud; }}); 2499 } 2500 0x2: CP2Unimpl::lwc2(); 2501 0x6: CP2Unimpl::ldc2(); 2502 0x3: Prefetch::pref(); 2503 } 2504 2505 2506 0x7: decode OPCODE_LO { 2507 0x0: StoreCond::sc({{ Mem_uw = Rt_uw; }}, 2508 {{ uint64_t tmp = write_result; 2509 Rt_uw = (tmp == 0 || tmp == 1) ? tmp : Rt_uw; 2510 }}, mem_flags=LLSC, 2511 inst_flags = IsStoreConditional); 2512 format StoreMemory { 2513 0x1: swc1({{ Mem_uw = Ft_uw; }}); 2514 0x5: sdc1({{ Mem_ud = Ft_ud; }}); 2515 } 2516 0x2: CP2Unimpl::swc2(); 2517 0x6: CP2Unimpl::sdc2(); 2518 } 2519} 2520 2521 2522