xref: /gem5/src/arch/mips/isa/bitfields.isa

// -*- mode:c++ -*-

////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
//

def bitfield OPCODE     <31:26>;
def bitfield OPCODE_HI  <31:29>;
def bitfield OPCODE_LO  <28:26>;

def bitfield REGIMM      <20:16>;
def bitfield REGIMM_HI   <20:19>;
def bitfield REGIMM_LO   <18:16>;

def bitfield FUNCTION      < 5: 0>;
def bitfield FUNCTION_HI   < 5: 3>;
def bitfield FUNCTION_LO   < 2: 0>;

def bitfield RS	      <25:21>;
def bitfield RS_MSB   <25:25>;
def bitfield RS_HI    <25:24>;
def bitfield RS_LO    <23:21>;
def bitfield RS_SRL   <25:22>;
def bitfield RS_RT    <25:16>;
def bitfield RT	      <20:16>;
def bitfield RT_HI    <20:19>;
def bitfield RT_LO    <18:16>;
def bitfield RT_RD    <20:11>;
def bitfield RD	      <15:11>;

def bitfield INTIMM	  <15: 0>;

// Floating-point operate format
def bitfield FMT      <25:21>;
def bitfield FR       <25:21>;
def bitfield FT	      <20:16>;
def bitfield FS	      <15:11>;
def bitfield FD	      <10:6>;

def bitfield ND       <17:17>;
def bitfield TF       <16:16>;
def bitfield MOVCI    <16:16>;
def bitfield MOVCF    <16:16>;
def bitfield SRL      <21:21>;
def bitfield SRLV     < 6: 6>;
def bitfield SA       <10: 6>;

// Floating Point Condition Codes
def bitfield CC <10:8>;
def bitfield BRANCH_CC <20:18>;

// CP0 Register Select
def bitfield SEL       < 2: 0>;

// Interrupts
def bitfield SC       < 5: 5>;

// Branch format
def bitfield OFFSET <15: 0>; // displacement

// Jmp format
def bitfield JMPTARG	<25: 0>;
def bitfield HINT	<10: 6>;

def bitfield SYSCALLCODE <25: 6>;
def bitfield TRAPCODE    <15:13>;

// EXT/INS instructions
def bitfield MSB	<15:11>;
def bitfield LSB	<10: 6>;

// M5 instructions
def bitfield M5FUNC <7:0>;