isa.hh revision 6313
1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_MIPS_ISA_HH__ 32#define __ARCH_MIPS_ISA_HH__ 33 34#include "arch/mips/regfile/misc_regfile.hh" 35#include "arch/mips/types.hh" 36 37class Checkpoint; 38class EventManager; 39 40namespace MipsISA 41{ 42 class ISA 43 { 44 protected: 45 MiscRegFile miscRegFile; 46 47 public: 48 49 void expandForMultithreading(ThreadID num_threads, unsigned num_vpes) 50 { 51 miscRegFile.expandForMultithreading(num_threads, num_vpes); 52 } 53 54 void reset(std::string core_name, ThreadID num_threads, 55 unsigned num_vpes, BaseCPU *_cpu) 56 { 57 miscRegFile.reset(core_name, num_threads, num_vpes, _cpu); 58 } 59 60 int instAsid() 61 { 62 return miscRegFile.getInstAsid(); 63 } 64 65 int dataAsid() 66 { 67 return miscRegFile.getDataAsid(); 68 } 69 70 void clear(); 71 72 MiscReg readMiscRegNoEffect(int miscReg); 73 MiscReg readMiscReg(int miscReg, ThreadContext *tc); 74 75 void setMiscRegNoEffect(int miscReg, const MiscReg val); 76 void setMiscReg(int miscReg, const MiscReg val, 77 ThreadContext *tc); 78 79 int 80 flattenIntIndex(int reg) 81 { 82 return reg; 83 } 84 85 int 86 flattenFloatIndex(int reg) 87 { 88 return reg; 89 } 90 91 void serialize(std::ostream &os); 92 void unserialize(Checkpoint *cp, const std::string §ion); 93 94 ISA() 95 { 96 clear(); 97 } 98 }; 99} 100 101#endif 102