isa.hh revision 13610:5d5404ac6288
111723Sar4jc@virginia.edu/* 211723Sar4jc@virginia.edu * Copyright (c) 2009 The Regents of The University of Michigan 311723Sar4jc@virginia.edu * All rights reserved. 411723Sar4jc@virginia.edu * 511723Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 611723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 711723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 811723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 911723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1011723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1111723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1211723Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1311723Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1411723Sar4jc@virginia.edu * this software without specific prior written permission. 1511723Sar4jc@virginia.edu * 1611723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111723Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211723Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311723Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411723Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711723Sar4jc@virginia.edu * 2811723Sar4jc@virginia.edu * Authors: Gabe Black 2911723Sar4jc@virginia.edu */ 3011723Sar4jc@virginia.edu 3111723Sar4jc@virginia.edu#ifndef __ARCH_MIPS_ISA_HH__ 3211723Sar4jc@virginia.edu#define __ARCH_MIPS_ISA_HH__ 3311723Sar4jc@virginia.edu 3411723Sar4jc@virginia.edu#include <queue> 3511723Sar4jc@virginia.edu#include <string> 3611964Sar4jc@virginia.edu#include <vector> 3711964Sar4jc@virginia.edu 3811964Sar4jc@virginia.edu#include "arch/mips/registers.hh" 3912394Sar4jc@virginia.edu#include "arch/mips/types.hh" 4011964Sar4jc@virginia.edu#include "cpu/reg_class.hh" 4111964Sar4jc@virginia.edu#include "sim/eventq.hh" 4211723Sar4jc@virginia.edu#include "sim/sim_object.hh" 4311723Sar4jc@virginia.edu 4412695Sar4jc@virginia.educlass BaseCPU; 4511723Sar4jc@virginia.educlass Checkpoint; 4612695Sar4jc@virginia.educlass EventManager; 4711723Sar4jc@virginia.edustruct MipsISAParams; 4811723Sar4jc@virginia.educlass ThreadContext; 4912334Sgabeblack@google.com 5012394Sar4jc@virginia.edunamespace MipsISA 5111723Sar4jc@virginia.edu{ 5211964Sar4jc@virginia.edu class ISA : public SimObject 5311723Sar4jc@virginia.edu { 5411964Sar4jc@virginia.edu public: 5511854Sbrandon.potter@amd.com // The MIPS name for this file is CP0 or Coprocessor 0 5611723Sar4jc@virginia.edu typedef ISA CP0; 5711723Sar4jc@virginia.edu 5811800Sbrandon.potter@amd.com typedef MipsISAParams Params; 5911723Sar4jc@virginia.edu 6011723Sar4jc@virginia.edu protected: 6111723Sar4jc@virginia.edu // Number of threads and vpes an individual ISA state can handle 6211723Sar4jc@virginia.edu uint8_t numThreads; 6311723Sar4jc@virginia.edu uint8_t numVpes; 6412431Sgabeblack@google.com 6512448Sgabeblack@google.com enum BankType { 6612448Sgabeblack@google.com perProcessor, 6712432Sgabeblack@google.com perThreadContext, 6811723Sar4jc@virginia.edu perVirtProcessor 6912441Sgabeblack@google.com }; 7013634Saustinharris@utexas.edu 7113634Saustinharris@utexas.edu std::vector<std::vector<MiscReg> > miscRegFile; 7213634Saustinharris@utexas.edu std::vector<std::vector<MiscReg> > miscRegFile_WriteMask; 7313634Saustinharris@utexas.edu std::vector<BankType> bankType; 7413634Saustinharris@utexas.edu 7511970Sar4jc@virginia.edu public: 7612393Sar4jc@virginia.edu void clear(); 7711964Sar4jc@virginia.edu 7811964Sar4jc@virginia.edu void configCP(); 7911964Sar4jc@virginia.edu 8011970Sar4jc@virginia.edu unsigned getVPENum(ThreadID tid) const; 8111905SBrandon.Potter@amd.com 8211964Sar4jc@virginia.edu ////////////////////////////////////////////////////////// 8311723Sar4jc@virginia.edu // 8411723Sar4jc@virginia.edu // READ/WRITE CP0 STATE 8513634Saustinharris@utexas.edu // 8613634Saustinharris@utexas.edu // 8713634Saustinharris@utexas.edu ////////////////////////////////////////////////////////// 8813634Saustinharris@utexas.edu //@TODO: MIPS MT's register view automatically connects 8913634Saustinharris@utexas.edu // Status to TCStatus depending on current thread 9013634Saustinharris@utexas.edu void updateCP0ReadView(int misc_reg, ThreadID tid) { } 9113634Saustinharris@utexas.edu MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; 9213634Saustinharris@utexas.edu 9313634Saustinharris@utexas.edu //template <class TC> 9413634Saustinharris@utexas.edu MiscReg readMiscReg(int misc_reg, 9513634Saustinharris@utexas.edu ThreadContext *tc, ThreadID tid = 0); 9613634Saustinharris@utexas.edu 9713634Saustinharris@utexas.edu MiscReg filterCP0Write(int misc_reg, int reg_sel, MiscReg val); 9811723Sar4jc@virginia.edu void setRegMask(int misc_reg, MiscReg val, ThreadID tid = 0); 9913634Saustinharris@utexas.edu void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0); 10011723Sar4jc@virginia.edu 10111851Sbrandon.potter@amd.com //template <class TC> 10211723Sar4jc@virginia.edu void setMiscReg(int misc_reg, MiscReg val, 10311723Sar4jc@virginia.edu ThreadContext *tc, ThreadID tid=0); 10412695Sar4jc@virginia.edu 10512695Sar4jc@virginia.edu ////////////////////////////////////////////////////////// 10611723Sar4jc@virginia.edu // 10711723Sar4jc@virginia.edu // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0) 10813634Saustinharris@utexas.edu // TO SCHEDULE EVENTS 10913634Saustinharris@utexas.edu // 11013634Saustinharris@utexas.edu ////////////////////////////////////////////////////////// 11113634Saustinharris@utexas.edu 11213634Saustinharris@utexas.edu // Flag that is set when CP0 state has been written to. 11313634Saustinharris@utexas.edu bool cp0Updated; 11413634Saustinharris@utexas.edu 11513634Saustinharris@utexas.edu // Enumerated List of CP0 Event Types 11613634Saustinharris@utexas.edu enum CP0EventType { 11713634Saustinharris@utexas.edu UpdateCP0 11813634Saustinharris@utexas.edu }; 11913634Saustinharris@utexas.edu 12013634Saustinharris@utexas.edu /** Process a CP0 event */ 12113634Saustinharris@utexas.edu void processCP0Event(BaseCPU *cpu, CP0EventType); 12211723Sar4jc@virginia.edu 12311851Sbrandon.potter@amd.com // Schedule a CP0 Update Event 12411723Sar4jc@virginia.edu void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0)); 12512394Sar4jc@virginia.edu 12613634Saustinharris@utexas.edu // If any changes have been made, then check the state for changes 12712394Sar4jc@virginia.edu // and if necessary alert the CPU 12811723Sar4jc@virginia.edu void updateCPU(BaseCPU *cpu); 12911964Sar4jc@virginia.edu 13011964Sar4jc@virginia.edu static std::string miscRegNames[NumMiscRegs]; 13111964Sar4jc@virginia.edu 13211723Sar4jc@virginia.edu public: 13311964Sar4jc@virginia.edu void startup(ThreadContext *tc) {} 13411964Sar4jc@virginia.edu 13512394Sar4jc@virginia.edu /// Explicitly import the otherwise hidden startup 13611964Sar4jc@virginia.edu using SimObject::startup; 13711964Sar4jc@virginia.edu 13811964Sar4jc@virginia.edu const Params *params() const; 13911964Sar4jc@virginia.edu 14013634Saustinharris@utexas.edu ISA(Params *p); 14111723Sar4jc@virginia.edu 14213634Saustinharris@utexas.edu RegId flattenRegId(const RegId& regId) const { return regId; } 14313634Saustinharris@utexas.edu 14411964Sar4jc@virginia.edu int 14513634Saustinharris@utexas.edu flattenIntIndex(int reg) const 14613634Saustinharris@utexas.edu { 14713634Saustinharris@utexas.edu return reg; 14813634Saustinharris@utexas.edu } 14913634Saustinharris@utexas.edu 15013634Saustinharris@utexas.edu int 15113634Saustinharris@utexas.edu flattenFloatIndex(int reg) const 15213634Saustinharris@utexas.edu { 15311964Sar4jc@virginia.edu return reg; 15413634Saustinharris@utexas.edu } 15513634Saustinharris@utexas.edu 15613634Saustinharris@utexas.edu int 15713634Saustinharris@utexas.edu flattenVecIndex(int reg) const 15811964Sar4jc@virginia.edu { 15911964Sar4jc@virginia.edu return reg; 16011964Sar4jc@virginia.edu } 16111964Sar4jc@virginia.edu 16212394Sar4jc@virginia.edu int 16312394Sar4jc@virginia.edu flattenVecElemIndex(int reg) const 16412394Sar4jc@virginia.edu { 16512394Sar4jc@virginia.edu return reg; 16612394Sar4jc@virginia.edu } 16712394Sar4jc@virginia.edu 16812039Sar4jc@virginia.edu int 16911964Sar4jc@virginia.edu flattenVecPredIndex(int reg) const 17011964Sar4jc@virginia.edu { 17111964Sar4jc@virginia.edu return reg; 17211964Sar4jc@virginia.edu } 17311964Sar4jc@virginia.edu 17411964Sar4jc@virginia.edu // dummy 17511964Sar4jc@virginia.edu int 17611964Sar4jc@virginia.edu flattenCCIndex(int reg) const 17711964Sar4jc@virginia.edu { 17811964Sar4jc@virginia.edu return reg; 17911964Sar4jc@virginia.edu } 18011964Sar4jc@virginia.edu 18111964Sar4jc@virginia.edu int 18211964Sar4jc@virginia.edu flattenMiscIndex(int reg) const 18311964Sar4jc@virginia.edu { 18411964Sar4jc@virginia.edu return reg; 18511964Sar4jc@virginia.edu } 18611964Sar4jc@virginia.edu 18711964Sar4jc@virginia.edu }; 18811964Sar4jc@virginia.edu} 18911964Sar4jc@virginia.edu 19011964Sar4jc@virginia.edu#endif 19111964Sar4jc@virginia.edu