isa.hh revision 13582:989577bf6abc
110259SAndrew.Bardsley@arm.com/* 212113Sjose.marinho@arm.com * Copyright (c) 2009 The Regents of The University of Michigan 310259SAndrew.Bardsley@arm.com * All rights reserved. 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 1210259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 1310259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 1510259SAndrew.Bardsley@arm.com * 1610259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710259SAndrew.Bardsley@arm.com * 2810259SAndrew.Bardsley@arm.com * Authors: Gabe Black 2910259SAndrew.Bardsley@arm.com */ 3010259SAndrew.Bardsley@arm.com 3110259SAndrew.Bardsley@arm.com#ifndef __ARCH_MIPS_ISA_HH__ 3210259SAndrew.Bardsley@arm.com#define __ARCH_MIPS_ISA_HH__ 3310259SAndrew.Bardsley@arm.com 3410259SAndrew.Bardsley@arm.com#include <queue> 3510259SAndrew.Bardsley@arm.com#include <string> 3610259SAndrew.Bardsley@arm.com#include <vector> 3710259SAndrew.Bardsley@arm.com 3810259SAndrew.Bardsley@arm.com#include "arch/mips/registers.hh" 3910259SAndrew.Bardsley@arm.com#include "arch/mips/types.hh" 4010259SAndrew.Bardsley@arm.com#include "cpu/reg_class.hh" 4110259SAndrew.Bardsley@arm.com#include "sim/eventq.hh" 4211800Sbrandon.potter@amd.com#include "sim/sim_object.hh" 4311800Sbrandon.potter@amd.com 4411800Sbrandon.potter@amd.comclass BaseCPU; 4510259SAndrew.Bardsley@arm.comclass Checkpoint; 4610259SAndrew.Bardsley@arm.comclass EventManager; 4710259SAndrew.Bardsley@arm.comstruct MipsISAParams; 4810259SAndrew.Bardsley@arm.comclass ThreadContext; 4910259SAndrew.Bardsley@arm.com 5010259SAndrew.Bardsley@arm.comnamespace MipsISA 5110259SAndrew.Bardsley@arm.com{ 5210259SAndrew.Bardsley@arm.com class ISA : public SimObject 5310259SAndrew.Bardsley@arm.com { 5410259SAndrew.Bardsley@arm.com public: 5510259SAndrew.Bardsley@arm.com // The MIPS name for this file is CP0 or Coprocessor 0 5610259SAndrew.Bardsley@arm.com typedef ISA CP0; 5710259SAndrew.Bardsley@arm.com 5810259SAndrew.Bardsley@arm.com typedef MipsISAParams Params; 5910259SAndrew.Bardsley@arm.com 6010259SAndrew.Bardsley@arm.com protected: 6110259SAndrew.Bardsley@arm.com // Number of threads and vpes an individual ISA state can handle 6210259SAndrew.Bardsley@arm.com uint8_t numThreads; 6312113Sjose.marinho@arm.com uint8_t numVpes; 6410259SAndrew.Bardsley@arm.com 6510259SAndrew.Bardsley@arm.com enum BankType { 6610259SAndrew.Bardsley@arm.com perProcessor, 6710259SAndrew.Bardsley@arm.com perThreadContext, 6810259SAndrew.Bardsley@arm.com perVirtProcessor 6910259SAndrew.Bardsley@arm.com }; 7010259SAndrew.Bardsley@arm.com 7110259SAndrew.Bardsley@arm.com std::vector<std::vector<MiscReg> > miscRegFile; 7210259SAndrew.Bardsley@arm.com std::vector<std::vector<MiscReg> > miscRegFile_WriteMask; 7310259SAndrew.Bardsley@arm.com std::vector<BankType> bankType; 7410259SAndrew.Bardsley@arm.com 7510259SAndrew.Bardsley@arm.com public: 7610259SAndrew.Bardsley@arm.com void clear(); 7710259SAndrew.Bardsley@arm.com 7810905Sandreas.sandberg@arm.com void configCP(); 7910259SAndrew.Bardsley@arm.com 8010259SAndrew.Bardsley@arm.com unsigned getVPENum(ThreadID tid) const; 8110259SAndrew.Bardsley@arm.com 8210905Sandreas.sandberg@arm.com ////////////////////////////////////////////////////////// 8310259SAndrew.Bardsley@arm.com // 8410259SAndrew.Bardsley@arm.com // READ/WRITE CP0 STATE 8510259SAndrew.Bardsley@arm.com // 8610905Sandreas.sandberg@arm.com // 8710259SAndrew.Bardsley@arm.com ////////////////////////////////////////////////////////// 8810320SAndrew.Bardsley@arm.com //@TODO: MIPS MT's register view automatically connects 8910259SAndrew.Bardsley@arm.com // Status to TCStatus depending on current thread 9010320SAndrew.Bardsley@arm.com void updateCP0ReadView(int misc_reg, ThreadID tid) { } 9110320SAndrew.Bardsley@arm.com MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; 9210320SAndrew.Bardsley@arm.com 9310320SAndrew.Bardsley@arm.com //template <class TC> 9410320SAndrew.Bardsley@arm.com MiscReg readMiscReg(int misc_reg, 9510320SAndrew.Bardsley@arm.com ThreadContext *tc, ThreadID tid = 0); 9610905Sandreas.sandberg@arm.com 9710259SAndrew.Bardsley@arm.com MiscReg filterCP0Write(int misc_reg, int reg_sel, MiscReg val); 9810259SAndrew.Bardsley@arm.com void setRegMask(int misc_reg, MiscReg val, ThreadID tid = 0); 9910259SAndrew.Bardsley@arm.com void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0); 10010259SAndrew.Bardsley@arm.com 10112113Sjose.marinho@arm.com //template <class TC> 10210259SAndrew.Bardsley@arm.com void setMiscReg(int misc_reg, MiscReg val, 10310259SAndrew.Bardsley@arm.com ThreadContext *tc, ThreadID tid=0); 10410259SAndrew.Bardsley@arm.com 10510259SAndrew.Bardsley@arm.com ////////////////////////////////////////////////////////// 10610259SAndrew.Bardsley@arm.com // 10710259SAndrew.Bardsley@arm.com // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0) 10810259SAndrew.Bardsley@arm.com // TO SCHEDULE EVENTS 10910259SAndrew.Bardsley@arm.com // 11010259SAndrew.Bardsley@arm.com ////////////////////////////////////////////////////////// 11110259SAndrew.Bardsley@arm.com 11212113Sjose.marinho@arm.com // Flag that is set when CP0 state has been written to. 11310259SAndrew.Bardsley@arm.com bool cp0Updated; 11410259SAndrew.Bardsley@arm.com 11510259SAndrew.Bardsley@arm.com // Enumerated List of CP0 Event Types 11610905Sandreas.sandberg@arm.com enum CP0EventType { 11710259SAndrew.Bardsley@arm.com UpdateCP0 11810905Sandreas.sandberg@arm.com }; 11910905Sandreas.sandberg@arm.com 12010259SAndrew.Bardsley@arm.com /** Process a CP0 event */ 12110259SAndrew.Bardsley@arm.com void processCP0Event(BaseCPU *cpu, CP0EventType); 12210905Sandreas.sandberg@arm.com 12310259SAndrew.Bardsley@arm.com // Schedule a CP0 Update Event 12410905Sandreas.sandberg@arm.com void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0)); 12510905Sandreas.sandberg@arm.com 12610259SAndrew.Bardsley@arm.com // If any changes have been made, then check the state for changes 127 // and if necessary alert the CPU 128 void updateCPU(BaseCPU *cpu); 129 130 static std::string miscRegNames[NumMiscRegs]; 131 132 public: 133 void startup(ThreadContext *tc) {} 134 135 /// Explicitly import the otherwise hidden startup 136 using SimObject::startup; 137 138 const Params *params() const; 139 140 ISA(Params *p); 141 142 RegId flattenRegId(const RegId& regId) const { return regId; } 143 144 int 145 flattenIntIndex(int reg) const 146 { 147 return reg; 148 } 149 150 int 151 flattenFloatIndex(int reg) const 152 { 153 return reg; 154 } 155 156 int 157 flattenVecIndex(int reg) const 158 { 159 return reg; 160 } 161 162 int 163 flattenVecElemIndex(int reg) const 164 { 165 return reg; 166 } 167 168 // dummy 169 int 170 flattenCCIndex(int reg) const 171 { 172 return reg; 173 } 174 175 int 176 flattenMiscIndex(int reg) const 177 { 178 return reg; 179 } 180 181 }; 182} 183 184#endif 185