isa.hh revision 13582
113531Sjairo.balart@metempsy.com/* 214167Sgiacomo.travaglini@arm.com * Copyright (c) 2009 The Regents of The University of Michigan 314167Sgiacomo.travaglini@arm.com * All rights reserved. 414167Sgiacomo.travaglini@arm.com * 514167Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 614167Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 714167Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 814167Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 914167Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1014167Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 1114167Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 1214167Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 1314167Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 1413531Sjairo.balart@metempsy.com * this software without specific prior written permission. 1513531Sjairo.balart@metempsy.com * 1613531Sjairo.balart@metempsy.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1713531Sjairo.balart@metempsy.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1813531Sjairo.balart@metempsy.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1913531Sjairo.balart@metempsy.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2013531Sjairo.balart@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2113531Sjairo.balart@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2213531Sjairo.balart@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2313531Sjairo.balart@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2413531Sjairo.balart@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2513531Sjairo.balart@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2613531Sjairo.balart@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2713531Sjairo.balart@metempsy.com * 2813531Sjairo.balart@metempsy.com * Authors: Gabe Black 2913531Sjairo.balart@metempsy.com */ 3013531Sjairo.balart@metempsy.com 3113531Sjairo.balart@metempsy.com#ifndef __ARCH_MIPS_ISA_HH__ 3213531Sjairo.balart@metempsy.com#define __ARCH_MIPS_ISA_HH__ 3313531Sjairo.balart@metempsy.com 3413531Sjairo.balart@metempsy.com#include <queue> 3513531Sjairo.balart@metempsy.com#include <string> 3613531Sjairo.balart@metempsy.com#include <vector> 3713531Sjairo.balart@metempsy.com 3813531Sjairo.balart@metempsy.com#include "arch/mips/registers.hh" 3913531Sjairo.balart@metempsy.com#include "arch/mips/types.hh" 4013531Sjairo.balart@metempsy.com#include "cpu/reg_class.hh" 4113531Sjairo.balart@metempsy.com#include "sim/eventq.hh" 4213756Sjairo.balart@metempsy.com#include "sim/sim_object.hh" 4313531Sjairo.balart@metempsy.com 4413531Sjairo.balart@metempsy.comclass BaseCPU; 4513531Sjairo.balart@metempsy.comclass Checkpoint; 4613531Sjairo.balart@metempsy.comclass EventManager; 4714257Sgiacomo.travaglini@arm.comstruct MipsISAParams; 4813531Sjairo.balart@metempsy.comclass ThreadContext; 4913531Sjairo.balart@metempsy.com 5013531Sjairo.balart@metempsy.comnamespace MipsISA 5113531Sjairo.balart@metempsy.com{ 5213531Sjairo.balart@metempsy.com class ISA : public SimObject 5313756Sjairo.balart@metempsy.com { 5413756Sjairo.balart@metempsy.com public: 5513756Sjairo.balart@metempsy.com // The MIPS name for this file is CP0 or Coprocessor 0 5613756Sjairo.balart@metempsy.com typedef ISA CP0; 5713756Sjairo.balart@metempsy.com 5813756Sjairo.balart@metempsy.com typedef MipsISAParams Params; 5913756Sjairo.balart@metempsy.com 6013531Sjairo.balart@metempsy.com protected: 6113756Sjairo.balart@metempsy.com // Number of threads and vpes an individual ISA state can handle 6213756Sjairo.balart@metempsy.com uint8_t numThreads; 6313756Sjairo.balart@metempsy.com uint8_t numVpes; 6413756Sjairo.balart@metempsy.com 6513756Sjairo.balart@metempsy.com enum BankType { 6613756Sjairo.balart@metempsy.com perProcessor, 6713756Sjairo.balart@metempsy.com perThreadContext, 6813531Sjairo.balart@metempsy.com perVirtProcessor 6913531Sjairo.balart@metempsy.com }; 7013531Sjairo.balart@metempsy.com 7113531Sjairo.balart@metempsy.com std::vector<std::vector<MiscReg> > miscRegFile; 7213531Sjairo.balart@metempsy.com std::vector<std::vector<MiscReg> > miscRegFile_WriteMask; 7313531Sjairo.balart@metempsy.com std::vector<BankType> bankType; 7413531Sjairo.balart@metempsy.com 7513531Sjairo.balart@metempsy.com public: 7613531Sjairo.balart@metempsy.com void clear(); 7713531Sjairo.balart@metempsy.com 7813531Sjairo.balart@metempsy.com void configCP(); 7913531Sjairo.balart@metempsy.com 8014167Sgiacomo.travaglini@arm.com unsigned getVPENum(ThreadID tid) const; 8114257Sgiacomo.travaglini@arm.com 8214167Sgiacomo.travaglini@arm.com ////////////////////////////////////////////////////////// 8314167Sgiacomo.travaglini@arm.com // 8414167Sgiacomo.travaglini@arm.com // READ/WRITE CP0 STATE 8514167Sgiacomo.travaglini@arm.com // 8614167Sgiacomo.travaglini@arm.com // 8713531Sjairo.balart@metempsy.com ////////////////////////////////////////////////////////// 8813531Sjairo.balart@metempsy.com //@TODO: MIPS MT's register view automatically connects 8914257Sgiacomo.travaglini@arm.com // Status to TCStatus depending on current thread 9014257Sgiacomo.travaglini@arm.com void updateCP0ReadView(int misc_reg, ThreadID tid) { } 9114257Sgiacomo.travaglini@arm.com MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; 9214257Sgiacomo.travaglini@arm.com 9314257Sgiacomo.travaglini@arm.com //template <class TC> 9414257Sgiacomo.travaglini@arm.com MiscReg readMiscReg(int misc_reg, 9514257Sgiacomo.travaglini@arm.com ThreadContext *tc, ThreadID tid = 0); 9614257Sgiacomo.travaglini@arm.com 9714257Sgiacomo.travaglini@arm.com MiscReg filterCP0Write(int misc_reg, int reg_sel, MiscReg val); 9814257Sgiacomo.travaglini@arm.com void setRegMask(int misc_reg, MiscReg val, ThreadID tid = 0); 9914257Sgiacomo.travaglini@arm.com void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0); 10014257Sgiacomo.travaglini@arm.com 10114257Sgiacomo.travaglini@arm.com //template <class TC> 10214257Sgiacomo.travaglini@arm.com void setMiscReg(int misc_reg, MiscReg val, 10314257Sgiacomo.travaglini@arm.com ThreadContext *tc, ThreadID tid=0); 10414257Sgiacomo.travaglini@arm.com 10514257Sgiacomo.travaglini@arm.com ////////////////////////////////////////////////////////// 10614257Sgiacomo.travaglini@arm.com // 10714257Sgiacomo.travaglini@arm.com // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0) 10814257Sgiacomo.travaglini@arm.com // TO SCHEDULE EVENTS 10914257Sgiacomo.travaglini@arm.com // 11014257Sgiacomo.travaglini@arm.com ////////////////////////////////////////////////////////// 11114257Sgiacomo.travaglini@arm.com 11214257Sgiacomo.travaglini@arm.com // Flag that is set when CP0 state has been written to. 11314257Sgiacomo.travaglini@arm.com bool cp0Updated; 11414257Sgiacomo.travaglini@arm.com 11514257Sgiacomo.travaglini@arm.com // Enumerated List of CP0 Event Types 11614257Sgiacomo.travaglini@arm.com enum CP0EventType { 11714257Sgiacomo.travaglini@arm.com UpdateCP0 11814257Sgiacomo.travaglini@arm.com }; 11914257Sgiacomo.travaglini@arm.com 12013531Sjairo.balart@metempsy.com /** Process a CP0 event */ 12113531Sjairo.balart@metempsy.com void processCP0Event(BaseCPU *cpu, CP0EventType); 12213531Sjairo.balart@metempsy.com 12313531Sjairo.balart@metempsy.com // Schedule a CP0 Update Event 12413531Sjairo.balart@metempsy.com void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0)); 12513531Sjairo.balart@metempsy.com 12613531Sjairo.balart@metempsy.com // If any changes have been made, then check the state for changes 12713531Sjairo.balart@metempsy.com // and if necessary alert the CPU 12813531Sjairo.balart@metempsy.com void updateCPU(BaseCPU *cpu); 12913531Sjairo.balart@metempsy.com 13013531Sjairo.balart@metempsy.com static std::string miscRegNames[NumMiscRegs]; 13113531Sjairo.balart@metempsy.com 13213531Sjairo.balart@metempsy.com public: 13313531Sjairo.balart@metempsy.com void startup(ThreadContext *tc) {} 13413531Sjairo.balart@metempsy.com 13513531Sjairo.balart@metempsy.com /// Explicitly import the otherwise hidden startup 13613531Sjairo.balart@metempsy.com using SimObject::startup; 13713531Sjairo.balart@metempsy.com 13813531Sjairo.balart@metempsy.com const Params *params() const; 13913531Sjairo.balart@metempsy.com 14013531Sjairo.balart@metempsy.com ISA(Params *p); 14113531Sjairo.balart@metempsy.com 14213531Sjairo.balart@metempsy.com RegId flattenRegId(const RegId& regId) const { return regId; } 14313531Sjairo.balart@metempsy.com 14413531Sjairo.balart@metempsy.com int 14513531Sjairo.balart@metempsy.com flattenIntIndex(int reg) const 14613531Sjairo.balart@metempsy.com { 14713531Sjairo.balart@metempsy.com return reg; 14813531Sjairo.balart@metempsy.com } 14913531Sjairo.balart@metempsy.com 15013531Sjairo.balart@metempsy.com int 15113531Sjairo.balart@metempsy.com flattenFloatIndex(int reg) const 15213531Sjairo.balart@metempsy.com { 15313531Sjairo.balart@metempsy.com return reg; 15413531Sjairo.balart@metempsy.com } 15513531Sjairo.balart@metempsy.com 15613531Sjairo.balart@metempsy.com int 15713531Sjairo.balart@metempsy.com flattenVecIndex(int reg) const 15813531Sjairo.balart@metempsy.com { 15913531Sjairo.balart@metempsy.com return reg; 16013531Sjairo.balart@metempsy.com } 16113531Sjairo.balart@metempsy.com 16213531Sjairo.balart@metempsy.com int 16313531Sjairo.balart@metempsy.com flattenVecElemIndex(int reg) const 16413531Sjairo.balart@metempsy.com { 16513531Sjairo.balart@metempsy.com return reg; 16613531Sjairo.balart@metempsy.com } 16713531Sjairo.balart@metempsy.com 16813531Sjairo.balart@metempsy.com // dummy 16913531Sjairo.balart@metempsy.com int 17013531Sjairo.balart@metempsy.com flattenCCIndex(int reg) const 17113531Sjairo.balart@metempsy.com { 17213531Sjairo.balart@metempsy.com return reg; 17313531Sjairo.balart@metempsy.com } 17413531Sjairo.balart@metempsy.com 17513531Sjairo.balart@metempsy.com int 17613531Sjairo.balart@metempsy.com flattenMiscIndex(int reg) const 17713531Sjairo.balart@metempsy.com { 17813531Sjairo.balart@metempsy.com return reg; 17913531Sjairo.balart@metempsy.com } 18013531Sjairo.balart@metempsy.com 18113531Sjairo.balart@metempsy.com }; 18213756Sjairo.balart@metempsy.com} 18313531Sjairo.balart@metempsy.com 18413531Sjairo.balart@metempsy.com#endif 18513531Sjairo.balart@metempsy.com