isa.hh revision 10698
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 36313Sgblack@eecs.umich.edu * All rights reserved. 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146313Sgblack@eecs.umich.edu * this software without specific prior written permission. 156313Sgblack@eecs.umich.edu * 166313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * Authors: Gabe Black 296313Sgblack@eecs.umich.edu */ 306313Sgblack@eecs.umich.edu 316313Sgblack@eecs.umich.edu#ifndef __ARCH_MIPS_ISA_HH__ 326313Sgblack@eecs.umich.edu#define __ARCH_MIPS_ISA_HH__ 336313Sgblack@eecs.umich.edu 348229Snate@binkert.org#include <queue> 356334Sgblack@eecs.umich.edu#include <string> 366334Sgblack@eecs.umich.edu#include <vector> 376334Sgblack@eecs.umich.edu 386334Sgblack@eecs.umich.edu#include "arch/mips/registers.hh" 396313Sgblack@eecs.umich.edu#include "arch/mips/types.hh" 406334Sgblack@eecs.umich.edu#include "sim/eventq.hh" 419384SAndreas.Sandberg@arm.com#include "sim/sim_object.hh" 426313Sgblack@eecs.umich.edu 436334Sgblack@eecs.umich.educlass BaseCPU; 446313Sgblack@eecs.umich.educlass Checkpoint; 456313Sgblack@eecs.umich.educlass EventManager; 469384SAndreas.Sandberg@arm.comstruct MipsISAParams; 476334Sgblack@eecs.umich.educlass ThreadContext; 486313Sgblack@eecs.umich.edu 496313Sgblack@eecs.umich.edunamespace MipsISA 506313Sgblack@eecs.umich.edu{ 519384SAndreas.Sandberg@arm.com class ISA : public SimObject 526313Sgblack@eecs.umich.edu { 536334Sgblack@eecs.umich.edu public: 546334Sgblack@eecs.umich.edu // The MIPS name for this file is CP0 or Coprocessor 0 556334Sgblack@eecs.umich.edu typedef ISA CP0; 566334Sgblack@eecs.umich.edu 579384SAndreas.Sandberg@arm.com typedef MipsISAParams Params; 589384SAndreas.Sandberg@arm.com 596313Sgblack@eecs.umich.edu protected: 608181Sksewell@umich.edu // Number of threads and vpes an individual ISA state can handle 618181Sksewell@umich.edu uint8_t numThreads; 628181Sksewell@umich.edu uint8_t numVpes; 638181Sksewell@umich.edu 646334Sgblack@eecs.umich.edu enum BankType { 656334Sgblack@eecs.umich.edu perProcessor, 666334Sgblack@eecs.umich.edu perThreadContext, 676334Sgblack@eecs.umich.edu perVirtProcessor 686334Sgblack@eecs.umich.edu }; 696334Sgblack@eecs.umich.edu 706334Sgblack@eecs.umich.edu std::vector<std::vector<MiscReg> > miscRegFile; 716334Sgblack@eecs.umich.edu std::vector<std::vector<MiscReg> > miscRegFile_WriteMask; 726334Sgblack@eecs.umich.edu std::vector<BankType> bankType; 736334Sgblack@eecs.umich.edu 746313Sgblack@eecs.umich.edu public: 758181Sksewell@umich.edu void clear(); 766334Sgblack@eecs.umich.edu 778181Sksewell@umich.edu void configCP(); 786334Sgblack@eecs.umich.edu 7910698Sandreas.hansson@arm.com unsigned getVPENum(ThreadID tid) const; 806334Sgblack@eecs.umich.edu 816334Sgblack@eecs.umich.edu ////////////////////////////////////////////////////////// 826334Sgblack@eecs.umich.edu // 836334Sgblack@eecs.umich.edu // READ/WRITE CP0 STATE 846334Sgblack@eecs.umich.edu // 856334Sgblack@eecs.umich.edu // 866334Sgblack@eecs.umich.edu ////////////////////////////////////////////////////////// 876334Sgblack@eecs.umich.edu //@TODO: MIPS MT's register view automatically connects 886334Sgblack@eecs.umich.edu // Status to TCStatus depending on current thread 896334Sgblack@eecs.umich.edu void updateCP0ReadView(int misc_reg, ThreadID tid) { } 9010698Sandreas.hansson@arm.com MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; 916334Sgblack@eecs.umich.edu 926334Sgblack@eecs.umich.edu //template <class TC> 936334Sgblack@eecs.umich.edu MiscReg readMiscReg(int misc_reg, 946334Sgblack@eecs.umich.edu ThreadContext *tc, ThreadID tid = 0); 956334Sgblack@eecs.umich.edu 966334Sgblack@eecs.umich.edu MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val); 976334Sgblack@eecs.umich.edu void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0); 986334Sgblack@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val, 996334Sgblack@eecs.umich.edu ThreadID tid = 0); 1006334Sgblack@eecs.umich.edu 1016334Sgblack@eecs.umich.edu //template <class TC> 1026334Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val, 1036334Sgblack@eecs.umich.edu ThreadContext *tc, ThreadID tid = 0); 1046334Sgblack@eecs.umich.edu 1056334Sgblack@eecs.umich.edu ////////////////////////////////////////////////////////// 1066334Sgblack@eecs.umich.edu // 1076334Sgblack@eecs.umich.edu // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0) 1086334Sgblack@eecs.umich.edu // TO SCHEDULE EVENTS 1096334Sgblack@eecs.umich.edu // 1106334Sgblack@eecs.umich.edu ////////////////////////////////////////////////////////// 1116334Sgblack@eecs.umich.edu 1126334Sgblack@eecs.umich.edu // Flag that is set when CP0 state has been written to. 1136334Sgblack@eecs.umich.edu bool cp0Updated; 1146334Sgblack@eecs.umich.edu 1156334Sgblack@eecs.umich.edu // Enumerated List of CP0 Event Types 1166334Sgblack@eecs.umich.edu enum CP0EventType { 1176334Sgblack@eecs.umich.edu UpdateCP0 1186334Sgblack@eecs.umich.edu }; 1196334Sgblack@eecs.umich.edu 1206334Sgblack@eecs.umich.edu // Declare A CP0Event Class for scheduling 1216334Sgblack@eecs.umich.edu class CP0Event : public Event 1226313Sgblack@eecs.umich.edu { 1236334Sgblack@eecs.umich.edu protected: 1246334Sgblack@eecs.umich.edu ISA::CP0 *cp0; 1256334Sgblack@eecs.umich.edu BaseCPU *cpu; 1266334Sgblack@eecs.umich.edu CP0EventType cp0EventType; 1276334Sgblack@eecs.umich.edu Fault fault; 1286313Sgblack@eecs.umich.edu 1296334Sgblack@eecs.umich.edu public: 1306334Sgblack@eecs.umich.edu /** Constructs a CP0 event. */ 1316334Sgblack@eecs.umich.edu CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type); 1326313Sgblack@eecs.umich.edu 1336334Sgblack@eecs.umich.edu /** Process this event. */ 1346334Sgblack@eecs.umich.edu virtual void process(); 1356313Sgblack@eecs.umich.edu 1366334Sgblack@eecs.umich.edu /** Returns the description of this event. */ 1376334Sgblack@eecs.umich.edu const char *description() const; 1386334Sgblack@eecs.umich.edu 1396334Sgblack@eecs.umich.edu /** Schedule This Event */ 1409180Sandreas.hansson@arm.com void scheduleEvent(Cycles delay); 1416334Sgblack@eecs.umich.edu 1426334Sgblack@eecs.umich.edu /** Unschedule This Event */ 1436334Sgblack@eecs.umich.edu void unscheduleEvent(); 1446334Sgblack@eecs.umich.edu }; 1456334Sgblack@eecs.umich.edu 1466334Sgblack@eecs.umich.edu // Schedule a CP0 Update Event 1479180Sandreas.hansson@arm.com void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0)); 1486334Sgblack@eecs.umich.edu 1496334Sgblack@eecs.umich.edu // If any changes have been made, then check the state for changes 1506334Sgblack@eecs.umich.edu // and if necessary alert the CPU 1516806Sgblack@eecs.umich.edu void updateCPU(BaseCPU *cpu); 1526334Sgblack@eecs.umich.edu 1536334Sgblack@eecs.umich.edu // Keep a List of CPU Events that need to be deallocated 1546334Sgblack@eecs.umich.edu std::queue<CP0Event*> cp0EventRemoveList; 1556334Sgblack@eecs.umich.edu 1566334Sgblack@eecs.umich.edu static std::string miscRegNames[NumMiscRegs]; 1576334Sgblack@eecs.umich.edu 1586334Sgblack@eecs.umich.edu public: 1599461Snilay@cs.wisc.edu void startup(ThreadContext *tc) {} 1609461Snilay@cs.wisc.edu 1619553Sandreas.hansson@arm.com /// Explicitly import the otherwise hidden startup 1629553Sandreas.hansson@arm.com using SimObject::startup; 1639553Sandreas.hansson@arm.com 1649384SAndreas.Sandberg@arm.com const Params *params() const; 1659384SAndreas.Sandberg@arm.com 1669384SAndreas.Sandberg@arm.com ISA(Params *p); 1676313Sgblack@eecs.umich.edu 1686313Sgblack@eecs.umich.edu int 16910035Sandreas.hansson@arm.com flattenIntIndex(int reg) const 1706313Sgblack@eecs.umich.edu { 1716313Sgblack@eecs.umich.edu return reg; 1726313Sgblack@eecs.umich.edu } 1736313Sgblack@eecs.umich.edu 1746313Sgblack@eecs.umich.edu int 17510035Sandreas.hansson@arm.com flattenFloatIndex(int reg) const 1766313Sgblack@eecs.umich.edu { 1776313Sgblack@eecs.umich.edu return reg; 1786313Sgblack@eecs.umich.edu } 1799920Syasuko.eckert@amd.com 1809920Syasuko.eckert@amd.com // dummy 1819920Syasuko.eckert@amd.com int 18210035Sandreas.hansson@arm.com flattenCCIndex(int reg) const 1839920Syasuko.eckert@amd.com { 1849920Syasuko.eckert@amd.com return reg; 1859920Syasuko.eckert@amd.com } 18610033SAli.Saidi@ARM.com 18710033SAli.Saidi@ARM.com int 18810035Sandreas.hansson@arm.com flattenMiscIndex(int reg) const 18910033SAli.Saidi@ARM.com { 19010033SAli.Saidi@ARM.com return reg; 19110033SAli.Saidi@ARM.com } 19210033SAli.Saidi@ARM.com 1936313Sgblack@eecs.umich.edu }; 1946313Sgblack@eecs.umich.edu} 1956313Sgblack@eecs.umich.edu 1966313Sgblack@eecs.umich.edu#endif 197