isa.cc revision 6313
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2009 The Regents of The University of Michigan 310259SAndrew.Bardsley@arm.com * All rights reserved. 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 1210259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 1310259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 1510259SAndrew.Bardsley@arm.com * 1610259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710259SAndrew.Bardsley@arm.com * 2810259SAndrew.Bardsley@arm.com * Authors: Gabe Black 2910259SAndrew.Bardsley@arm.com */ 3010259SAndrew.Bardsley@arm.com 3110259SAndrew.Bardsley@arm.com#include "arch/mips/isa.hh" 3210259SAndrew.Bardsley@arm.com#include "arch/mips/regfile/misc_regfile.hh" 3310259SAndrew.Bardsley@arm.com#include "cpu/thread_context.hh" 3410259SAndrew.Bardsley@arm.com 3510259SAndrew.Bardsley@arm.comnamespace MipsISA 3610259SAndrew.Bardsley@arm.com{ 3710259SAndrew.Bardsley@arm.com 3810259SAndrew.Bardsley@arm.comvoid 3910259SAndrew.Bardsley@arm.comISA::clear() 4011793Sbrandon.potter@amd.com{ 4111793Sbrandon.potter@amd.com miscRegFile.clear(); 4210259SAndrew.Bardsley@arm.com} 4310259SAndrew.Bardsley@arm.com 4410259SAndrew.Bardsley@arm.comMiscReg 4510259SAndrew.Bardsley@arm.comISA::readMiscRegNoEffect(int miscReg) 4610259SAndrew.Bardsley@arm.com{ 4710259SAndrew.Bardsley@arm.com return miscRegFile.readRegNoEffect(miscReg); 4810259SAndrew.Bardsley@arm.com} 4910259SAndrew.Bardsley@arm.com 5010259SAndrew.Bardsley@arm.comMiscReg 5110259SAndrew.Bardsley@arm.comISA::readMiscReg(int miscReg, ThreadContext *tc) 5210259SAndrew.Bardsley@arm.com{ 5310259SAndrew.Bardsley@arm.com return miscRegFile.readReg(miscReg, tc); 5410259SAndrew.Bardsley@arm.com} 5510259SAndrew.Bardsley@arm.com 5610259SAndrew.Bardsley@arm.comvoid 5710259SAndrew.Bardsley@arm.comISA::setMiscRegNoEffect(int miscReg, const MiscReg val) 5810259SAndrew.Bardsley@arm.com{ 5910259SAndrew.Bardsley@arm.com miscRegFile.setRegNoEffect(miscReg, val); 6010259SAndrew.Bardsley@arm.com} 6110259SAndrew.Bardsley@arm.com 6210259SAndrew.Bardsley@arm.comvoid 6310259SAndrew.Bardsley@arm.comISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc) 6410259SAndrew.Bardsley@arm.com{ 6510259SAndrew.Bardsley@arm.com miscRegFile.setReg(miscReg, val, tc); 6610259SAndrew.Bardsley@arm.com} 6710259SAndrew.Bardsley@arm.com 68void 69ISA::serialize(std::ostream &os) 70{ 71 //miscRegFile.serialize(os); 72} 73 74void 75ISA::unserialize(Checkpoint *cp, const std::string §ion) 76{ 77 //miscRegFile.unserialize(cp, section); 78} 79 80} 81