isa.cc revision 11165
111106Spower.jg@gmail.com/* 211106Spower.jg@gmail.com * Copyright (c) 2009 The Regents of The University of Michigan 311106Spower.jg@gmail.com * All rights reserved. 411106Spower.jg@gmail.com * 511106Spower.jg@gmail.com * Redistribution and use in source and binary forms, with or without 611106Spower.jg@gmail.com * modification, are permitted provided that the following conditions are 711106Spower.jg@gmail.com * met: redistributions of source code must retain the above copyright 811106Spower.jg@gmail.com * notice, this list of conditions and the following disclaimer; 911106Spower.jg@gmail.com * redistributions in binary form must reproduce the above copyright 1011106Spower.jg@gmail.com * notice, this list of conditions and the following disclaimer in the 1111106Spower.jg@gmail.com * documentation and/or other materials provided with the distribution; 1211106Spower.jg@gmail.com * neither the name of the copyright holders nor the names of its 1311106Spower.jg@gmail.com * contributors may be used to endorse or promote products derived from 1411106Spower.jg@gmail.com * this software without specific prior written permission. 1511106Spower.jg@gmail.com * 1611106Spower.jg@gmail.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711570SCurtis.Dunham@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811106Spower.jg@gmail.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911312Santhony.gutierrez@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011106Spower.jg@gmail.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111106Spower.jg@gmail.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211106Spower.jg@gmail.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311106Spower.jg@gmail.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411106Spower.jg@gmail.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511106Spower.jg@gmail.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611680SCurtis.Dunham@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711106Spower.jg@gmail.com * 2811106Spower.jg@gmail.com * Authors: Gabe Black 2911219Snilay@cs.wisc.edu */ 3011106Spower.jg@gmail.com 3111570SCurtis.Dunham@arm.com#include "arch/mips/isa.hh" 3211570SCurtis.Dunham@arm.com#include "arch/mips/mt.hh" 3311570SCurtis.Dunham@arm.com#include "arch/mips/mt_constants.hh" 3411570SCurtis.Dunham@arm.com#include "arch/mips/pra_constants.hh" 3511106Spower.jg@gmail.com#include "base/bitfield.hh" 3611106Spower.jg@gmail.com#include "cpu/base.hh" 3711440SCurtis.Dunham@arm.com#include "cpu/thread_context.hh" 3811440SCurtis.Dunham@arm.com#include "debug/MipsPRA.hh" 3911106Spower.jg@gmail.com#include "params/MipsISA.hh" 4011106Spower.jg@gmail.com 4111106Spower.jg@gmail.comnamespace MipsISA 4211106Spower.jg@gmail.com{ 4311106Spower.jg@gmail.com 4411106Spower.jg@gmail.comstd::string 4511106Spower.jg@gmail.comISA::miscRegNames[NumMiscRegs] = 4611106Spower.jg@gmail.com{ 4711106Spower.jg@gmail.com "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "", 4811106Spower.jg@gmail.com "Random", "VPEControl", "VPEConf0", "VPEConf1", 4911106Spower.jg@gmail.com "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt", 5011106Spower.jg@gmail.com "EntryLo0", "TCStatus", "TCBind", "TCRestart", 5111106Spower.jg@gmail.com "TCHalt", "TCContext", "TCSchedule", "TCScheFBack", 5211106Spower.jg@gmail.com "EntryLo1", "", "", "", "", "", "", "", 5311106Spower.jg@gmail.com "Context", "ContextConfig", "", "", "", "", "", "", 5411106Spower.jg@gmail.com "PageMask", "PageGrain", "", "", "", "", "", "", 5511106Spower.jg@gmail.com "Wired", "SRSConf0", "SRCConf1", "SRSConf2", 5611106Spower.jg@gmail.com "SRSConf3", "SRSConf4", "", "", 5711106Spower.jg@gmail.com "HWREna", "", "", "", "", "", "", "", 5811106Spower.jg@gmail.com "BadVAddr", "", "", "", "", "", "", "", 5911106Spower.jg@gmail.com "Count", "", "", "", "", "", "", "", 6011106Spower.jg@gmail.com "EntryHi", "", "", "", "", "", "", "", 6111106Spower.jg@gmail.com "Compare", "", "", "", "", "", "", "", 6211106Spower.jg@gmail.com "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "", 6311106Spower.jg@gmail.com "Cause", "", "", "", "", "", "", "", 6411106Spower.jg@gmail.com "EPC", "", "", "", "", "", "", "", 6511106Spower.jg@gmail.com "PRId", "EBase", "", "", "", "", "", "", 6611106Spower.jg@gmail.com "Config", "Config1", "Config2", "Config3", "", "", "", "", 6711106Spower.jg@gmail.com "LLAddr", "", "", "", "", "", "", "", 6811106Spower.jg@gmail.com "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3", 6911570SCurtis.Dunham@arm.com "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7", 7011106Spower.jg@gmail.com "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3", 7111106Spower.jg@gmail.com "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7", 7211106Spower.jg@gmail.com "XCContext64", "", "", "", "", "", "", "", 7311106Spower.jg@gmail.com "", "", "", "", "", "", "", "", 7411106Spower.jg@gmail.com "", "", "", "", "", "", "", "", 7511106Spower.jg@gmail.com "Debug", "TraceControl1", "TraceControl2", "UserTraceData", 7611106Spower.jg@gmail.com "TraceBPC", "", "", "", 7711106Spower.jg@gmail.com "DEPC", "", "", "", "", "", "", "", 7811106Spower.jg@gmail.com "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3", 7911106Spower.jg@gmail.com "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7", 8011106Spower.jg@gmail.com "ErrCtl", "", "", "", "", "", "", "", 8111106Spower.jg@gmail.com "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "", 8211106Spower.jg@gmail.com "TagLo0", "DataLo1", "TagLo2", "DataLo3", 8311106Spower.jg@gmail.com "TagLo4", "DataLo5", "TagLo6", "DataLo7", 8411106Spower.jg@gmail.com "TagHi0", "DataHi1", "TagHi2", "DataHi3", 8511106Spower.jg@gmail.com "TagHi4", "DataHi5", "TagHi6", "DataHi7", 8611106Spower.jg@gmail.com "ErrorEPC", "", "", "", "", "", "", "", 8711570SCurtis.Dunham@arm.com "DESAVE", "", "", "", "", "", "", "", 8811570SCurtis.Dunham@arm.com "LLFlag" 8911570SCurtis.Dunham@arm.com}; 9011570SCurtis.Dunham@arm.com 9111106Spower.jg@gmail.comISA::ISA(Params *p) 9211106Spower.jg@gmail.com : SimObject(p), numThreads(p->num_threads), numVpes(p->num_vpes) 9311106Spower.jg@gmail.com{ 9411106Spower.jg@gmail.com miscRegFile.resize(NumMiscRegs); 9511106Spower.jg@gmail.com bankType.resize(NumMiscRegs); 9611960Sgabeblack@google.com 9711106Spower.jg@gmail.com for (int i=0; i < NumMiscRegs; i++) { 9811106Spower.jg@gmail.com miscRegFile[i].resize(1); 9911106Spower.jg@gmail.com bankType[i] = perProcessor; 10011106Spower.jg@gmail.com } 10111106Spower.jg@gmail.com 10211106Spower.jg@gmail.com miscRegFile_WriteMask.resize(NumMiscRegs); 10311106Spower.jg@gmail.com 10411106Spower.jg@gmail.com for (int i = 0; i < NumMiscRegs; i++) { 10511106Spower.jg@gmail.com miscRegFile_WriteMask[i].push_back(0); 10611680SCurtis.Dunham@arm.com } 10711106Spower.jg@gmail.com 10811106Spower.jg@gmail.com // Initialize all Per-VPE regs 10911219Snilay@cs.wisc.edu uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL, 11011960Sgabeblack@google.com MISCREG_VPE_CONF0, MISCREG_VPE_CONF1, 11111570SCurtis.Dunham@arm.com MISCREG_YQMASK, 11211106Spower.jg@gmail.com MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK, 11311106Spower.jg@gmail.com MISCREG_VPE_OPT, MISCREG_SRS_CONF0, 11411106Spower.jg@gmail.com MISCREG_SRS_CONF1, MISCREG_SRS_CONF2, 11511106Spower.jg@gmail.com MISCREG_SRS_CONF3, MISCREG_SRS_CONF4, 11611106Spower.jg@gmail.com MISCREG_EBASE 11711570SCurtis.Dunham@arm.com }; 11811570SCurtis.Dunham@arm.com uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4; 11911570SCurtis.Dunham@arm.com for (int i = 0; i < num_vpe_regs; i++) { 12011570SCurtis.Dunham@arm.com if (numVpes > 1) { 12111106Spower.jg@gmail.com miscRegFile[per_vpe_regs[i]].resize(numVpes); 12211106Spower.jg@gmail.com } 12311106Spower.jg@gmail.com bankType[per_vpe_regs[i]] = perVirtProcessor; 12411106Spower.jg@gmail.com } 12511106Spower.jg@gmail.com 12611106Spower.jg@gmail.com // Initialize all Per-TC regs 12711960Sgabeblack@google.com uint32_t per_tc_regs[] = { MISCREG_STATUS, 12811106Spower.jg@gmail.com MISCREG_TC_STATUS, MISCREG_TC_BIND, 12911106Spower.jg@gmail.com MISCREG_TC_RESTART, MISCREG_TC_HALT, 13011106Spower.jg@gmail.com MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE, 13111219Snilay@cs.wisc.edu MISCREG_TC_SCHEFBACK, 13211106Spower.jg@gmail.com MISCREG_DEBUG, MISCREG_LLADDR 13311106Spower.jg@gmail.com }; 13411106Spower.jg@gmail.com uint32_t num_tc_regs = sizeof(per_tc_regs) / 4; 13511106Spower.jg@gmail.com 13611106Spower.jg@gmail.com for (int i = 0; i < num_tc_regs; i++) { 13711106Spower.jg@gmail.com miscRegFile[per_tc_regs[i]].resize(numThreads); 13811106Spower.jg@gmail.com bankType[per_tc_regs[i]] = perThreadContext; 13911106Spower.jg@gmail.com } 14011960Sgabeblack@google.com 14111570SCurtis.Dunham@arm.com clear(); 14211106Spower.jg@gmail.com} 14311570SCurtis.Dunham@arm.com 14411570SCurtis.Dunham@arm.comconst MipsISAParams * 14511570SCurtis.Dunham@arm.comISA::params() const 14611570SCurtis.Dunham@arm.com{ 14711106Spower.jg@gmail.com return dynamic_cast<const Params *>(_params); 14811106Spower.jg@gmail.com} 14911960Sgabeblack@google.com 15011106Spower.jg@gmail.comvoid 15111106Spower.jg@gmail.comISA::clear() 15211106Spower.jg@gmail.com{ 15311106Spower.jg@gmail.com for(int i = 0; i < NumMiscRegs; i++) { 15411106Spower.jg@gmail.com for (int j = 0; j < miscRegFile[i].size(); j++) 15511106Spower.jg@gmail.com miscRegFile[i][j] = 0; 15611106Spower.jg@gmail.com 15711106Spower.jg@gmail.com for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++) 15811106Spower.jg@gmail.com miscRegFile_WriteMask[i][k] = (long unsigned int)(-1); 15911106Spower.jg@gmail.com } 16011106Spower.jg@gmail.com} 16111106Spower.jg@gmail.com 16211106Spower.jg@gmail.com 16311106Spower.jg@gmail.comvoid 16411106Spower.jg@gmail.comISA::configCP() 16511106Spower.jg@gmail.com{ 16611106Spower.jg@gmail.com DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n", 16711106Spower.jg@gmail.com numThreads, numVpes); 16811106Spower.jg@gmail.com 16911106Spower.jg@gmail.com CoreSpecific cp; 17011570SCurtis.Dunham@arm.com panic("CP state must be set before the following code is used"); 17111106Spower.jg@gmail.com 17211106Spower.jg@gmail.com // Do Default CP0 initialization HERE 17311106Spower.jg@gmail.com 17411570SCurtis.Dunham@arm.com // Do Initialization for MT cores here (eventually use 17511570SCurtis.Dunham@arm.com // core_name parameter to toggle this initialization) 17611570SCurtis.Dunham@arm.com // =================================================== 17711570SCurtis.Dunham@arm.com DPRINTF(MipsPRA, "Initializing CP0 State.... "); 17811106Spower.jg@gmail.com 17911106Spower.jg@gmail.com PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID); 18011106Spower.jg@gmail.com procId.coOp = cp.CP0_PRId_CompanyOptions; 18111106Spower.jg@gmail.com procId.coId = cp.CP0_PRId_CompanyID; 18211106Spower.jg@gmail.com procId.procId = cp.CP0_PRId_ProcessorID; 18311106Spower.jg@gmail.com procId.rev = cp.CP0_PRId_Revision; 18411106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_PRID, procId); 18511106Spower.jg@gmail.com 18611106Spower.jg@gmail.com // Now, create Write Mask for ProcID register 18711106Spower.jg@gmail.com MiscReg procIDMask = 0; // Read-Only register 18811106Spower.jg@gmail.com replaceBits(procIDMask, 0, 32, 0); 18911106Spower.jg@gmail.com setRegMask(MISCREG_PRID, procIDMask); 19011106Spower.jg@gmail.com 19111570SCurtis.Dunham@arm.com // Config 19211106Spower.jg@gmail.com ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG); 19311106Spower.jg@gmail.com cfg.be = cp.CP0_Config_BE; 19411106Spower.jg@gmail.com cfg.at = cp.CP0_Config_AT; 19511570SCurtis.Dunham@arm.com cfg.ar = cp.CP0_Config_AR; 19611570SCurtis.Dunham@arm.com cfg.mt = cp.CP0_Config_MT; 19711570SCurtis.Dunham@arm.com cfg.vi = cp.CP0_Config_VI; 19811570SCurtis.Dunham@arm.com cfg.m = 1; 19911106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_CONFIG, cfg); 20011106Spower.jg@gmail.com // Now, create Write Mask for Config register 20111106Spower.jg@gmail.com MiscReg cfg_Mask = 0x7FFF0007; 20211106Spower.jg@gmail.com replaceBits(cfg_Mask, 0, 32, 0); 20311106Spower.jg@gmail.com setRegMask(MISCREG_CONFIG, cfg_Mask); 20411680SCurtis.Dunham@arm.com 20511106Spower.jg@gmail.com // Config1 20611106Spower.jg@gmail.com Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1); 20711219Snilay@cs.wisc.edu cfg1.mmuSize = cp.CP0_Config1_MMU; 20811960Sgabeblack@google.com cfg1.is = cp.CP0_Config1_IS; 20911570SCurtis.Dunham@arm.com cfg1.il = cp.CP0_Config1_IL; 21011106Spower.jg@gmail.com cfg1.ia = cp.CP0_Config1_IA; 21111106Spower.jg@gmail.com cfg1.ds = cp.CP0_Config1_DS; 21211106Spower.jg@gmail.com cfg1.dl = cp.CP0_Config1_DL; 21311106Spower.jg@gmail.com cfg1.da = cp.CP0_Config1_DA; 21411106Spower.jg@gmail.com cfg1.fp = cp.CP0_Config1_FP; 21511570SCurtis.Dunham@arm.com cfg1.ep = cp.CP0_Config1_EP; 21611570SCurtis.Dunham@arm.com cfg1.wr = cp.CP0_Config1_WR; 21711570SCurtis.Dunham@arm.com cfg1.md = cp.CP0_Config1_MD; 21811570SCurtis.Dunham@arm.com cfg1.c2 = cp.CP0_Config1_C2; 21911106Spower.jg@gmail.com cfg1.pc = cp.CP0_Config1_PC; 22011106Spower.jg@gmail.com cfg1.m = cp.CP0_Config1_M; 22111106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_CONFIG1, cfg1); 22211106Spower.jg@gmail.com // Now, create Write Mask for Config register 22311106Spower.jg@gmail.com MiscReg cfg1_Mask = 0; // Read Only Register 22411106Spower.jg@gmail.com replaceBits(cfg1_Mask, 0, 32, 0); 22511960Sgabeblack@google.com setRegMask(MISCREG_CONFIG1, cfg1_Mask); 22611106Spower.jg@gmail.com 22711106Spower.jg@gmail.com // Config2 22811106Spower.jg@gmail.com Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2); 22911219Snilay@cs.wisc.edu cfg2.tu = cp.CP0_Config2_TU; 23011106Spower.jg@gmail.com cfg2.ts = cp.CP0_Config2_TS; 23111106Spower.jg@gmail.com cfg2.tl = cp.CP0_Config2_TL; 23211106Spower.jg@gmail.com cfg2.ta = cp.CP0_Config2_TA; 23311106Spower.jg@gmail.com cfg2.su = cp.CP0_Config2_SU; 23411106Spower.jg@gmail.com cfg2.ss = cp.CP0_Config2_SS; 23511106Spower.jg@gmail.com cfg2.sl = cp.CP0_Config2_SL; 23611106Spower.jg@gmail.com cfg2.sa = cp.CP0_Config2_SA; 23711106Spower.jg@gmail.com cfg2.m = cp.CP0_Config2_M; 23811960Sgabeblack@google.com setMiscRegNoEffect(MISCREG_CONFIG2, cfg2); 23911570SCurtis.Dunham@arm.com // Now, create Write Mask for Config register 24011106Spower.jg@gmail.com MiscReg cfg2_Mask = 0x7000F000; // Read Only Register 24111570SCurtis.Dunham@arm.com replaceBits(cfg2_Mask, 0, 32, 0); 24211570SCurtis.Dunham@arm.com setRegMask(MISCREG_CONFIG2, cfg2_Mask); 24311570SCurtis.Dunham@arm.com 24411570SCurtis.Dunham@arm.com // Config3 24511106Spower.jg@gmail.com Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3); 24611106Spower.jg@gmail.com cfg3.dspp = cp.CP0_Config3_DSPP; 24711960Sgabeblack@google.com cfg3.lpa = cp.CP0_Config3_LPA; 24811106Spower.jg@gmail.com cfg3.veic = cp.CP0_Config3_VEIC; 24911106Spower.jg@gmail.com cfg3.vint = cp.CP0_Config3_VInt; 25011106Spower.jg@gmail.com cfg3.sp = cp.CP0_Config3_SP; 25111106Spower.jg@gmail.com cfg3.mt = cp.CP0_Config3_MT; 25211106Spower.jg@gmail.com cfg3.sm = cp.CP0_Config3_SM; 25311106Spower.jg@gmail.com cfg3.tl = cp.CP0_Config3_TL; 25411106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_CONFIG3, cfg3); 25511219Snilay@cs.wisc.edu // Now, create Write Mask for Config register 25611106Spower.jg@gmail.com MiscReg cfg3_Mask = 0; // Read Only Register 25711106Spower.jg@gmail.com replaceBits(cfg3_Mask, 0, 32, 0); 25811106Spower.jg@gmail.com setRegMask(MISCREG_CONFIG3, cfg3_Mask); 25911106Spower.jg@gmail.com 26011106Spower.jg@gmail.com // EBase - CPUNum 26111106Spower.jg@gmail.com EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE); 26211106Spower.jg@gmail.com eBase.cpuNum = cp.CP0_EBase_CPUNum; 26311106Spower.jg@gmail.com replaceBits(eBase, 31, 31, 1); 26411106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_EBASE, eBase); 26511106Spower.jg@gmail.com // Now, create Write Mask for Config register 26611106Spower.jg@gmail.com MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the 26711106Spower.jg@gmail.com // entire register is read only 26811106Spower.jg@gmail.com replaceBits(EB_Mask, 0, 32, 0); 26911106Spower.jg@gmail.com setRegMask(MISCREG_EBASE, EB_Mask); 27011106Spower.jg@gmail.com 27111106Spower.jg@gmail.com // SRS Control - HSS (Highest Shadow Set) 27211106Spower.jg@gmail.com SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL); 27311106Spower.jg@gmail.com scsCtl.hss = cp.CP0_SrsCtl_HSS; 27411106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl); 27511106Spower.jg@gmail.com // Now, create Write Mask for the SRS Ctl register 27611106Spower.jg@gmail.com MiscReg SC_Mask = 0x0000F3C0; 27711106Spower.jg@gmail.com replaceBits(SC_Mask, 0, 32, 0); 27811106Spower.jg@gmail.com setRegMask(MISCREG_SRSCTL, SC_Mask); 27911106Spower.jg@gmail.com 28011106Spower.jg@gmail.com // IntCtl - IPTI, IPPCI 28111106Spower.jg@gmail.com IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL); 28211106Spower.jg@gmail.com intCtl.ipti = cp.CP0_IntCtl_IPTI; 28311106Spower.jg@gmail.com intCtl.ippci = cp.CP0_IntCtl_IPPCI; 28411106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_INTCTL, intCtl); 28511106Spower.jg@gmail.com // Now, create Write Mask for the IntCtl register 28611106Spower.jg@gmail.com MiscReg IC_Mask = 0x000003E0; 28711106Spower.jg@gmail.com replaceBits(IC_Mask, 0, 32, 0); 28811106Spower.jg@gmail.com setRegMask(MISCREG_INTCTL, IC_Mask); 28911106Spower.jg@gmail.com 29011106Spower.jg@gmail.com // Watch Hi - M - FIXME (More than 1 Watch register) 29111106Spower.jg@gmail.com WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0); 29211106Spower.jg@gmail.com watchHi.m = cp.CP0_WatchHi_M; 29311106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi); 29411106Spower.jg@gmail.com // Now, create Write Mask for the IntCtl register 29511106Spower.jg@gmail.com MiscReg wh_Mask = 0x7FFF0FFF; 29611106Spower.jg@gmail.com replaceBits(wh_Mask, 0, 32, 0); 29711106Spower.jg@gmail.com setRegMask(MISCREG_WATCHHI0, wh_Mask); 29811106Spower.jg@gmail.com 29911570SCurtis.Dunham@arm.com // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair) 30011106Spower.jg@gmail.com PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0); 30111106Spower.jg@gmail.com perfCntCtl.m = cp.CP0_PerfCtr_M; 30211106Spower.jg@gmail.com perfCntCtl.w = cp.CP0_PerfCtr_W; 30311570SCurtis.Dunham@arm.com setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl); 30411570SCurtis.Dunham@arm.com // Now, create Write Mask for the IntCtl register 30511570SCurtis.Dunham@arm.com MiscReg pc_Mask = 0x00007FF; 30611570SCurtis.Dunham@arm.com replaceBits(pc_Mask, 0, 32, 0); 30711106Spower.jg@gmail.com setRegMask(MISCREG_PERFCNT0, pc_Mask); 30811106Spower.jg@gmail.com 30911106Spower.jg@gmail.com // Random 31011106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63); 31111106Spower.jg@gmail.com // Now, create Write Mask for the IntCtl register 31211106Spower.jg@gmail.com MiscReg random_Mask = 0; 31311106Spower.jg@gmail.com replaceBits(random_Mask, 0, 32, 0); 31411106Spower.jg@gmail.com setRegMask(MISCREG_CP0_RANDOM, random_Mask); 31511106Spower.jg@gmail.com 31611106Spower.jg@gmail.com // PageGrain 31711106Spower.jg@gmail.com PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN); 31811106Spower.jg@gmail.com pageGrain.esp = cp.CP0_Config3_SP; 31911106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain); 32011570SCurtis.Dunham@arm.com // Now, create Write Mask for the IntCtl register 32111106Spower.jg@gmail.com MiscReg pg_Mask = 0x10000000; 32211106Spower.jg@gmail.com replaceBits(pg_Mask, 0, 32, 0); 32311106Spower.jg@gmail.com setRegMask(MISCREG_PAGEGRAIN, pg_Mask); 32411570SCurtis.Dunham@arm.com 32511570SCurtis.Dunham@arm.com // Status 32611570SCurtis.Dunham@arm.com StatusReg status = readMiscRegNoEffect(MISCREG_STATUS); 32711570SCurtis.Dunham@arm.com // Only CU0 and IE are modified on a reset - everything else needs 32811106Spower.jg@gmail.com // to be controlled on a per CPU model basis 32911106Spower.jg@gmail.com 33011106Spower.jg@gmail.com // Enable CP0 on reset 33111106Spower.jg@gmail.com // status.cu0 = 1; 33211106Spower.jg@gmail.com 33311106Spower.jg@gmail.com // Enable ERL bit on a reset 33411106Spower.jg@gmail.com status.erl = 1; 33511960Sgabeblack@google.com // Enable BEV bit on a reset 33611106Spower.jg@gmail.com status.bev = 1; 33711106Spower.jg@gmail.com 33811106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_STATUS, status); 33911106Spower.jg@gmail.com // Now, create Write Mask for the Status register 34011106Spower.jg@gmail.com MiscReg stat_Mask = 0xFF78FF17; 34111106Spower.jg@gmail.com replaceBits(stat_Mask, 0, 32, 0); 34211106Spower.jg@gmail.com setRegMask(MISCREG_STATUS, stat_Mask); 34311106Spower.jg@gmail.com 34411106Spower.jg@gmail.com 34511106Spower.jg@gmail.com // MVPConf0 34611106Spower.jg@gmail.com MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0); 34711106Spower.jg@gmail.com mvpConf0.tca = 1; 34811960Sgabeblack@google.com mvpConf0.pvpe = numVpes - 1; 34911106Spower.jg@gmail.com mvpConf0.ptc = numThreads - 1; 35011960Sgabeblack@google.com setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0); 35111106Spower.jg@gmail.com 35211960Sgabeblack@google.com // VPEConf0 35311106Spower.jg@gmail.com VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0); 35411106Spower.jg@gmail.com vpeConf0.mvp = 1; 35511106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0); 35611106Spower.jg@gmail.com 35711106Spower.jg@gmail.com // TCBind 35811106Spower.jg@gmail.com for (ThreadID tid = 0; tid < numThreads; tid++) { 35911106Spower.jg@gmail.com TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid); 36011106Spower.jg@gmail.com tcBind.curTC = tid; 36111106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid); 36211106Spower.jg@gmail.com } 36311106Spower.jg@gmail.com // TCHalt 36411106Spower.jg@gmail.com TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT); 36511106Spower.jg@gmail.com tcHalt.h = 0; 36611106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt); 36711106Spower.jg@gmail.com 36811219Snilay@cs.wisc.edu // TCStatus 36911106Spower.jg@gmail.com // Set TCStatus Activated to 1 for the initial thread that is running 37011570SCurtis.Dunham@arm.com TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS); 37111106Spower.jg@gmail.com tcStatus.a = 1; 37211106Spower.jg@gmail.com setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus); 37311106Spower.jg@gmail.com 37411570SCurtis.Dunham@arm.com // Set Dynamically Allocatable bit to 1 for all other threads 37511570SCurtis.Dunham@arm.com for (ThreadID tid = 1; tid < numThreads; tid++) { 37611570SCurtis.Dunham@arm.com tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid); 37711440SCurtis.Dunham@arm.com tcStatus.da = 1; 37811570SCurtis.Dunham@arm.com setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid); 37911106Spower.jg@gmail.com } 38011219Snilay@cs.wisc.edu 38111106Spower.jg@gmail.com 38211106Spower.jg@gmail.com MiscReg mask = 0x7FFFFFFF; 38311106Spower.jg@gmail.com 38411106Spower.jg@gmail.com // Now, create Write Mask for the Index register 38511106Spower.jg@gmail.com replaceBits(mask, 0, 32, 0); 38611106Spower.jg@gmail.com setRegMask(MISCREG_INDEX, mask); 38711106Spower.jg@gmail.com 38811219Snilay@cs.wisc.edu mask = 0x3FFFFFFF; 38911219Snilay@cs.wisc.edu replaceBits(mask, 0, 32, 0); 39011219Snilay@cs.wisc.edu setRegMask(MISCREG_ENTRYLO0, mask); 39111219Snilay@cs.wisc.edu setRegMask(MISCREG_ENTRYLO1, mask); 39211219Snilay@cs.wisc.edu 39311219Snilay@cs.wisc.edu mask = 0xFF800000; 39411219Snilay@cs.wisc.edu replaceBits(mask, 0, 32, 0); 39511106Spower.jg@gmail.com setRegMask(MISCREG_CONTEXT, mask); 39611106Spower.jg@gmail.com 39711106Spower.jg@gmail.com mask = 0x1FFFF800; 39811680SCurtis.Dunham@arm.com replaceBits(mask, 0, 32, 0); 39911106Spower.jg@gmail.com setRegMask(MISCREG_PAGEMASK, mask); 40011106Spower.jg@gmail.com 40111219Snilay@cs.wisc.edu mask = 0x0; 40211960Sgabeblack@google.com replaceBits(mask, 0, 32, 0); 40311570SCurtis.Dunham@arm.com setRegMask(MISCREG_BADVADDR, mask); 40411106Spower.jg@gmail.com setRegMask(MISCREG_LLADDR, mask); 40511106Spower.jg@gmail.com 40611106Spower.jg@gmail.com mask = 0x08C00300; 40711106Spower.jg@gmail.com replaceBits(mask, 0, 32, 0); 40811106Spower.jg@gmail.com setRegMask(MISCREG_CAUSE, mask); 40911570SCurtis.Dunham@arm.com 41011570SCurtis.Dunham@arm.com} 41111570SCurtis.Dunham@arm.com 41211570SCurtis.Dunham@arm.cominline unsigned 41311106Spower.jg@gmail.comISA::getVPENum(ThreadID tid) const 41411106Spower.jg@gmail.com{ 41511106Spower.jg@gmail.com TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid]; 41611106Spower.jg@gmail.com return tcBind.curVPE; 41711106Spower.jg@gmail.com} 41811106Spower.jg@gmail.com 41911960Sgabeblack@google.comMiscReg 42011106Spower.jg@gmail.comISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const 42111106Spower.jg@gmail.com{ 42211106Spower.jg@gmail.com unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 42311219Snilay@cs.wisc.edu ? tid : getVPENum(tid); 42411106Spower.jg@gmail.com DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n", 42511106Spower.jg@gmail.com misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], 42611106Spower.jg@gmail.com miscRegFile[misc_reg][reg_sel]); 42711106Spower.jg@gmail.com return miscRegFile[misc_reg][reg_sel]; 42811106Spower.jg@gmail.com} 42911106Spower.jg@gmail.com 43011106Spower.jg@gmail.com//@TODO: MIPS MT's register view automatically connects 43111106Spower.jg@gmail.com// Status to TCStatus depending on current thread 43211960Sgabeblack@google.com//template <class TC> 43311570SCurtis.Dunham@arm.comMiscReg 43411106Spower.jg@gmail.comISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) 43511570SCurtis.Dunham@arm.com{ 43611570SCurtis.Dunham@arm.com unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 43711570SCurtis.Dunham@arm.com ? tid : getVPENum(tid); 43811570SCurtis.Dunham@arm.com DPRINTF(MipsPRA, 43911106Spower.jg@gmail.com "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n", 44011106Spower.jg@gmail.com misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], 44111960Sgabeblack@google.com miscRegFile[misc_reg][reg_sel]); 44211106Spower.jg@gmail.com 44311106Spower.jg@gmail.com return miscRegFile[misc_reg][reg_sel]; 44411106Spower.jg@gmail.com} 44511680SCurtis.Dunham@arm.com 44611106Spower.jg@gmail.comvoid 44711680SCurtis.Dunham@arm.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) 44811106Spower.jg@gmail.com{ 44911106Spower.jg@gmail.com unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 45011106Spower.jg@gmail.com ? tid : getVPENum(tid); 45111680SCurtis.Dunham@arm.com DPRINTF(MipsPRA, 45211106Spower.jg@gmail.com "[tid:%i]: Setting (direct set) CP0 Register:%u " 45311680SCurtis.Dunham@arm.com "Select:%u (%s) to %#x.\n", 45411106Spower.jg@gmail.com tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 45511106Spower.jg@gmail.com 45611106Spower.jg@gmail.com miscRegFile[misc_reg][reg_sel] = val; 45711680SCurtis.Dunham@arm.com} 45811106Spower.jg@gmail.com 45911680SCurtis.Dunham@arm.comvoid 46011106Spower.jg@gmail.comISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid) 46111680SCurtis.Dunham@arm.com{ 46211106Spower.jg@gmail.com unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 46311680SCurtis.Dunham@arm.com ? tid : getVPENum(tid); 46411106Spower.jg@gmail.com DPRINTF(MipsPRA, 46511680SCurtis.Dunham@arm.com "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n", 46611106Spower.jg@gmail.com tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 46711106Spower.jg@gmail.com miscRegFile_WriteMask[misc_reg][reg_sel] = val; 46811106Spower.jg@gmail.com} 46911106Spower.jg@gmail.com 47011106Spower.jg@gmail.com// PROGRAMMER'S NOTES: 47111106Spower.jg@gmail.com// (1) Some CP0 Registers have fields that cannot 47211106Spower.jg@gmail.com// be overwritten. Make sure to handle those particular registers 47311106Spower.jg@gmail.com// with care! 47411106Spower.jg@gmail.comvoid 47511106Spower.jg@gmail.comISA::setMiscReg(int misc_reg, const MiscReg &val, 47611106Spower.jg@gmail.com ThreadContext *tc, ThreadID tid) 47711570SCurtis.Dunham@arm.com{ 47811106Spower.jg@gmail.com int reg_sel = (bankType[misc_reg] == perThreadContext) 47911106Spower.jg@gmail.com ? tid : getVPENum(tid); 48011106Spower.jg@gmail.com 48111106Spower.jg@gmail.com DPRINTF(MipsPRA, 48211106Spower.jg@gmail.com "[tid:%i]: Setting CP0 Register:%u " 48311106Spower.jg@gmail.com "Select:%u (%s) to %#x, with effect.\n", 48411106Spower.jg@gmail.com tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 48511680SCurtis.Dunham@arm.com 48611106Spower.jg@gmail.com MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val); 48711106Spower.jg@gmail.com 48811106Spower.jg@gmail.com miscRegFile[misc_reg][reg_sel] = cp0_val; 48911106Spower.jg@gmail.com 49011570SCurtis.Dunham@arm.com scheduleCP0Update(tc->getCpuPtr(), Cycles(1)); 49111570SCurtis.Dunham@arm.com} 49211570SCurtis.Dunham@arm.com 49311106Spower.jg@gmail.com/** 49411570SCurtis.Dunham@arm.com * This method doesn't need to adjust the Control Register Offset 49511680SCurtis.Dunham@arm.com * since it has already been done in the calling method 49611106Spower.jg@gmail.com * (setRegWithEffect) 49711106Spower.jg@gmail.com*/ 49811106Spower.jg@gmail.comMiscReg 49911106Spower.jg@gmail.comISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) 50011106Spower.jg@gmail.com{ 50111106Spower.jg@gmail.com MiscReg retVal = val; 50211106Spower.jg@gmail.com 50311106Spower.jg@gmail.com // Mask off read-only regions 50411106Spower.jg@gmail.com retVal &= miscRegFile_WriteMask[misc_reg][reg_sel]; 50511106Spower.jg@gmail.com MiscReg curVal = miscRegFile[misc_reg][reg_sel]; 50611106Spower.jg@gmail.com // Mask off current alue with inverse mask (clear writeable bits) 50711106Spower.jg@gmail.com curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]); 50811106Spower.jg@gmail.com retVal |= curVal; // Combine the two 50911106Spower.jg@gmail.com DPRINTF(MipsPRA, 51011106Spower.jg@gmail.com "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, " 51111106Spower.jg@gmail.com "current val: %lx, written val: %x\n", 51211106Spower.jg@gmail.com miscRegFile_WriteMask[misc_reg][reg_sel], 51311106Spower.jg@gmail.com ~miscRegFile_WriteMask[misc_reg][reg_sel], 51411106Spower.jg@gmail.com val, miscRegFile[misc_reg][reg_sel], retVal); 51511106Spower.jg@gmail.com return retVal; 51611106Spower.jg@gmail.com} 51711680SCurtis.Dunham@arm.com 51811106Spower.jg@gmail.comvoid 51911680SCurtis.Dunham@arm.comISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay) 52011106Spower.jg@gmail.com{ 52111106Spower.jg@gmail.com if (!cp0Updated) { 52211106Spower.jg@gmail.com cp0Updated = true; 52311106Spower.jg@gmail.com 52411106Spower.jg@gmail.com //schedule UPDATE 52511106Spower.jg@gmail.com CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0); 52611106Spower.jg@gmail.com cpu->schedule(cp0_event, cpu->clockEdge(delay)); 52711106Spower.jg@gmail.com } 52811680SCurtis.Dunham@arm.com} 52911106Spower.jg@gmail.com 53011570SCurtis.Dunham@arm.comvoid 53111106Spower.jg@gmail.comISA::updateCPU(BaseCPU *cpu) 53211106Spower.jg@gmail.com{ 53311106Spower.jg@gmail.com /////////////////////////////////////////////////////////////////// 53411570SCurtis.Dunham@arm.com // 53511570SCurtis.Dunham@arm.com // EVALUATE CP0 STATE FOR MIPS MT 53611570SCurtis.Dunham@arm.com // 53711440SCurtis.Dunham@arm.com /////////////////////////////////////////////////////////////////// 53811570SCurtis.Dunham@arm.com MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0); 53911106Spower.jg@gmail.com ThreadID num_threads = mvpConf0.ptc + 1; 54011680SCurtis.Dunham@arm.com 54111106Spower.jg@gmail.com for (ThreadID tid = 0; tid < num_threads; tid++) { 54211106Spower.jg@gmail.com TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid); 54311106Spower.jg@gmail.com TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid); 54411106Spower.jg@gmail.com 54511106Spower.jg@gmail.com //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs 54611106Spower.jg@gmail.com if (tcHalt.h == 1 || tcStatus.a == 0) { 54711106Spower.jg@gmail.com haltThread(cpu->getContext(tid)); 54811680SCurtis.Dunham@arm.com } else if (tcHalt.h == 0 && tcStatus.a == 1) { 54911680SCurtis.Dunham@arm.com restoreThread(cpu->getContext(tid)); 55011680SCurtis.Dunham@arm.com } 55111680SCurtis.Dunham@arm.com } 55211680SCurtis.Dunham@arm.com 55311680SCurtis.Dunham@arm.com num_threads = mvpConf0.ptc + 1; 55411680SCurtis.Dunham@arm.com 555 // Toggle update flag after we finished updating 556 cp0Updated = false; 557} 558 559ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type) 560 : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type) 561{ } 562 563void 564ISA::CP0Event::process() 565{ 566 switch (cp0EventType) 567 { 568 case UpdateCP0: 569 cp0->updateCPU(cpu); 570 break; 571 } 572} 573 574const char * 575ISA::CP0Event::description() const 576{ 577 return "Coprocessor-0 event"; 578} 579 580void 581ISA::CP0Event::scheduleEvent(Cycles delay) 582{ 583 cpu->reschedule(this, cpu->clockEdge(delay), true); 584} 585 586void 587ISA::CP0Event::unscheduleEvent() 588{ 589 if (scheduled()) 590 squash(); 591} 592 593} 594 595MipsISA::ISA * 596MipsISAParams::create() 597{ 598 return new MipsISA::ISA(this); 599} 600