isa.cc revision 6383
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 36313Sgblack@eecs.umich.edu * All rights reserved. 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146313Sgblack@eecs.umich.edu * this software without specific prior written permission. 156313Sgblack@eecs.umich.edu * 166313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * Authors: Gabe Black 296313Sgblack@eecs.umich.edu */ 306313Sgblack@eecs.umich.edu 316313Sgblack@eecs.umich.edu#include "arch/mips/isa.hh" 326334Sgblack@eecs.umich.edu#include "arch/mips/mt_constants.hh" 336334Sgblack@eecs.umich.edu#include "arch/mips/mt.hh" 346334Sgblack@eecs.umich.edu#include "arch/mips/pra_constants.hh" 356334Sgblack@eecs.umich.edu#include "base/bitfield.hh" 366334Sgblack@eecs.umich.edu#include "cpu/base.hh" 376313Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 386313Sgblack@eecs.umich.edu 396313Sgblack@eecs.umich.edunamespace MipsISA 406313Sgblack@eecs.umich.edu{ 416313Sgblack@eecs.umich.edu 426334Sgblack@eecs.umich.edustd::string 436334Sgblack@eecs.umich.eduISA::miscRegNames[NumMiscRegs] = 446334Sgblack@eecs.umich.edu{ 456334Sgblack@eecs.umich.edu "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "", 466334Sgblack@eecs.umich.edu "Random", "VPEControl", "VPEConf0", "VPEConf1", 476334Sgblack@eecs.umich.edu "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt", 486334Sgblack@eecs.umich.edu "EntryLo0", "TCStatus", "TCBind", "TCRestart", 496334Sgblack@eecs.umich.edu "TCHalt", "TCContext", "TCSchedule", "TCScheFBack", 506334Sgblack@eecs.umich.edu "EntryLo1", "", "", "", "", "", "", "", 516334Sgblack@eecs.umich.edu "Context", "ContextConfig", "", "", "", "", "", "", 526334Sgblack@eecs.umich.edu "PageMask", "PageGrain", "", "", "", "", "", "", 536334Sgblack@eecs.umich.edu "Wired", "SRSConf0", "SRCConf1", "SRSConf2", 546334Sgblack@eecs.umich.edu "SRSConf3", "SRSConf4", "", "", 556334Sgblack@eecs.umich.edu "HWREna", "", "", "", "", "", "", "", 566334Sgblack@eecs.umich.edu "BadVAddr", "", "", "", "", "", "", "", 576334Sgblack@eecs.umich.edu "Count", "", "", "", "", "", "", "", 586334Sgblack@eecs.umich.edu "EntryHi", "", "", "", "", "", "", "", 596334Sgblack@eecs.umich.edu "Compare", "", "", "", "", "", "", "", 606334Sgblack@eecs.umich.edu "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "", 616334Sgblack@eecs.umich.edu "Cause", "", "", "", "", "", "", "", 626334Sgblack@eecs.umich.edu "EPC", "", "", "", "", "", "", "", 636334Sgblack@eecs.umich.edu "PRId", "EBase", "", "", "", "", "", "", 646334Sgblack@eecs.umich.edu "Config", "Config1", "Config2", "Config3", "", "", "", "", 656334Sgblack@eecs.umich.edu "LLAddr", "", "", "", "", "", "", "", 666334Sgblack@eecs.umich.edu "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3", 676334Sgblack@eecs.umich.edu "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7", 686334Sgblack@eecs.umich.edu "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3", 696334Sgblack@eecs.umich.edu "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7", 706334Sgblack@eecs.umich.edu "XCContext64", "", "", "", "", "", "", "", 716334Sgblack@eecs.umich.edu "", "", "", "", "", "", "", "", 726334Sgblack@eecs.umich.edu "", "", "", "", "", "", "", "", 736334Sgblack@eecs.umich.edu "Debug", "TraceControl1", "TraceControl2", "UserTraceData", 746334Sgblack@eecs.umich.edu "TraceBPC", "", "", "", 756334Sgblack@eecs.umich.edu "DEPC", "", "", "", "", "", "", "", 766334Sgblack@eecs.umich.edu "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3", 776334Sgblack@eecs.umich.edu "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7", 786334Sgblack@eecs.umich.edu "ErrCtl", "", "", "", "", "", "", "", 796334Sgblack@eecs.umich.edu "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "", 806334Sgblack@eecs.umich.edu "TagLo0", "DataLo1", "TagLo2", "DataLo3", 816334Sgblack@eecs.umich.edu "TagLo4", "DataLo5", "TagLo6", "DataLo7", 826334Sgblack@eecs.umich.edu "TagHi0", "DataHi1", "TagHi2", "DataHi3", 836334Sgblack@eecs.umich.edu "TagHi4", "DataHi5", "TagHi6", "DataHi7", 846334Sgblack@eecs.umich.edu "ErrorEPC", "", "", "", "", "", "", "", 856334Sgblack@eecs.umich.edu "DESAVE", "", "", "", "", "", "", "", 866334Sgblack@eecs.umich.edu "LLFlag" 876334Sgblack@eecs.umich.edu}; 886334Sgblack@eecs.umich.edu 896334Sgblack@eecs.umich.eduISA::ISA() 906334Sgblack@eecs.umich.edu{ 916334Sgblack@eecs.umich.edu init(); 926334Sgblack@eecs.umich.edu} 936334Sgblack@eecs.umich.edu 946334Sgblack@eecs.umich.eduISA::ISA(BaseCPU *_cpu) 956334Sgblack@eecs.umich.edu{ 966334Sgblack@eecs.umich.edu cpu = _cpu; 976334Sgblack@eecs.umich.edu init(); 986334Sgblack@eecs.umich.edu} 996334Sgblack@eecs.umich.edu 1006313Sgblack@eecs.umich.eduvoid 1016334Sgblack@eecs.umich.eduISA::init() 1026313Sgblack@eecs.umich.edu{ 1036334Sgblack@eecs.umich.edu miscRegFile.resize(NumMiscRegs); 1046334Sgblack@eecs.umich.edu bankType.resize(NumMiscRegs); 1056334Sgblack@eecs.umich.edu 1066334Sgblack@eecs.umich.edu for (int i=0; i < NumMiscRegs; i++) { 1076334Sgblack@eecs.umich.edu miscRegFile[i].resize(1); 1086334Sgblack@eecs.umich.edu bankType[i] = perProcessor; 1096334Sgblack@eecs.umich.edu } 1106334Sgblack@eecs.umich.edu 1116334Sgblack@eecs.umich.edu miscRegFile_WriteMask.resize(NumMiscRegs); 1126334Sgblack@eecs.umich.edu 1136376Sgblack@eecs.umich.edu for (int i = 0; i < NumMiscRegs; i++) { 1146376Sgblack@eecs.umich.edu miscRegFile_WriteMask[i].push_back(0); 1156334Sgblack@eecs.umich.edu } 1166334Sgblack@eecs.umich.edu clear(0); 1176334Sgblack@eecs.umich.edu} 1186334Sgblack@eecs.umich.edu 1196334Sgblack@eecs.umich.eduvoid 1206334Sgblack@eecs.umich.eduISA::clear(unsigned tid_or_vpn) 1216334Sgblack@eecs.umich.edu{ 1226334Sgblack@eecs.umich.edu for(int i = 0; i < NumMiscRegs; i++) { 1236334Sgblack@eecs.umich.edu miscRegFile[i][tid_or_vpn] = 0; 1246334Sgblack@eecs.umich.edu miscRegFile_WriteMask[i][tid_or_vpn] = (long unsigned int)(-1); 1256334Sgblack@eecs.umich.edu } 1266334Sgblack@eecs.umich.edu} 1276334Sgblack@eecs.umich.edu 1286334Sgblack@eecs.umich.eduvoid 1296334Sgblack@eecs.umich.eduISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes) 1306334Sgblack@eecs.umich.edu{ 1316334Sgblack@eecs.umich.edu // Initialize all Per-VPE regs 1326383Sgblack@eecs.umich.edu uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL, 1336383Sgblack@eecs.umich.edu MISCREG_VPE_CONF0, MISCREG_VPE_CONF1, 1346383Sgblack@eecs.umich.edu MISCREG_YQMASK, 1356383Sgblack@eecs.umich.edu MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK, 1366383Sgblack@eecs.umich.edu MISCREG_VPE_OPT, MISCREG_SRS_CONF0, 1376383Sgblack@eecs.umich.edu MISCREG_SRS_CONF1, MISCREG_SRS_CONF2, 1386383Sgblack@eecs.umich.edu MISCREG_SRS_CONF3, MISCREG_SRS_CONF4, 1396383Sgblack@eecs.umich.edu MISCREG_EBASE 1406334Sgblack@eecs.umich.edu }; 1416334Sgblack@eecs.umich.edu uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4; 1426334Sgblack@eecs.umich.edu for (int i = 0; i < num_vpe_regs; i++) { 1436334Sgblack@eecs.umich.edu if (num_vpes > 1) { 1446334Sgblack@eecs.umich.edu miscRegFile[per_vpe_regs[i]].resize(num_vpes); 1456334Sgblack@eecs.umich.edu } 1466334Sgblack@eecs.umich.edu bankType[per_vpe_regs[i]] = perVirtProcessor; 1476334Sgblack@eecs.umich.edu } 1486334Sgblack@eecs.umich.edu 1496334Sgblack@eecs.umich.edu // Initialize all Per-TC regs 1506383Sgblack@eecs.umich.edu uint32_t per_tc_regs[] = { MISCREG_STATUS, 1516383Sgblack@eecs.umich.edu MISCREG_TC_STATUS, MISCREG_TC_BIND, 1526383Sgblack@eecs.umich.edu MISCREG_TC_RESTART, MISCREG_TC_HALT, 1536383Sgblack@eecs.umich.edu MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE, 1546383Sgblack@eecs.umich.edu MISCREG_TC_SCHEFBACK, 1556383Sgblack@eecs.umich.edu MISCREG_DEBUG, MISCREG_LLADDR 1566334Sgblack@eecs.umich.edu }; 1576334Sgblack@eecs.umich.edu uint32_t num_tc_regs = sizeof(per_tc_regs) / 4; 1586334Sgblack@eecs.umich.edu 1596334Sgblack@eecs.umich.edu for (int i = 0; i < num_tc_regs; i++) { 1606334Sgblack@eecs.umich.edu miscRegFile[per_tc_regs[i]].resize(num_threads); 1616334Sgblack@eecs.umich.edu bankType[per_tc_regs[i]] = perThreadContext; 1626334Sgblack@eecs.umich.edu } 1636334Sgblack@eecs.umich.edu 1646334Sgblack@eecs.umich.edu 1656334Sgblack@eecs.umich.edu if (num_vpes > 1) { 1666334Sgblack@eecs.umich.edu for (int i=1; i < num_vpes; i++) { 1676334Sgblack@eecs.umich.edu clear(i); 1686334Sgblack@eecs.umich.edu } 1696334Sgblack@eecs.umich.edu } 1706334Sgblack@eecs.umich.edu 1716334Sgblack@eecs.umich.edu} 1726334Sgblack@eecs.umich.edu 1736334Sgblack@eecs.umich.edu//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H) 1746334Sgblack@eecs.umich.eduvoid 1756334Sgblack@eecs.umich.eduISA::reset(std::string core_name, ThreadID num_threads, 1766334Sgblack@eecs.umich.edu unsigned num_vpes, BaseCPU *_cpu) 1776334Sgblack@eecs.umich.edu{ 1786334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n", 1796334Sgblack@eecs.umich.edu num_threads, num_vpes); 1806334Sgblack@eecs.umich.edu cpu = _cpu; 1816334Sgblack@eecs.umich.edu 1826334Sgblack@eecs.umich.edu MipsISA::CoreSpecific &cp = cpu->coreParams; 1836334Sgblack@eecs.umich.edu 1846334Sgblack@eecs.umich.edu // Do Default CP0 initialization HERE 1856334Sgblack@eecs.umich.edu 1866334Sgblack@eecs.umich.edu // Do Initialization for MT cores here (eventually use 1876334Sgblack@eecs.umich.edu // core_name parameter to toggle this initialization) 1886334Sgblack@eecs.umich.edu // =================================================== 1896334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Initializing CP0 State.... "); 1906334Sgblack@eecs.umich.edu 1916383Sgblack@eecs.umich.edu PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID); 1926376Sgblack@eecs.umich.edu procId.coOp = cp.CP0_PRId_CompanyOptions; 1936376Sgblack@eecs.umich.edu procId.coId = cp.CP0_PRId_CompanyID; 1946376Sgblack@eecs.umich.edu procId.procId = cp.CP0_PRId_ProcessorID; 1956376Sgblack@eecs.umich.edu procId.rev = cp.CP0_PRId_Revision; 1966383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_PRID, procId); 1976376Sgblack@eecs.umich.edu 1986334Sgblack@eecs.umich.edu // Now, create Write Mask for ProcID register 1996383Sgblack@eecs.umich.edu MiscReg procIDMask = 0; // Read-Only register 2006383Sgblack@eecs.umich.edu replaceBits(procIDMask, 0, 32, 0); 2016383Sgblack@eecs.umich.edu setRegMask(MISCREG_PRID, procIDMask); 2026334Sgblack@eecs.umich.edu 2036334Sgblack@eecs.umich.edu // Config 2046383Sgblack@eecs.umich.edu ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG); 2056376Sgblack@eecs.umich.edu cfg.be = cp.CP0_Config_BE; 2066376Sgblack@eecs.umich.edu cfg.at = cp.CP0_Config_AT; 2076376Sgblack@eecs.umich.edu cfg.ar = cp.CP0_Config_AR; 2086376Sgblack@eecs.umich.edu cfg.mt = cp.CP0_Config_MT; 2096376Sgblack@eecs.umich.edu cfg.vi = cp.CP0_Config_VI; 2106376Sgblack@eecs.umich.edu cfg.m = 1; 2116383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_CONFIG, cfg); 2126334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2136334Sgblack@eecs.umich.edu MiscReg cfg_Mask = 0x7FFF0007; 2146376Sgblack@eecs.umich.edu replaceBits(cfg_Mask, 0, 32, 0); 2156383Sgblack@eecs.umich.edu setRegMask(MISCREG_CONFIG, cfg_Mask); 2166334Sgblack@eecs.umich.edu 2176334Sgblack@eecs.umich.edu // Config1 2186383Sgblack@eecs.umich.edu Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1); 2196376Sgblack@eecs.umich.edu cfg1.mmuSize = cp.CP0_Config1_MMU; 2206376Sgblack@eecs.umich.edu cfg1.is = cp.CP0_Config1_IS; 2216376Sgblack@eecs.umich.edu cfg1.il = cp.CP0_Config1_IL; 2226376Sgblack@eecs.umich.edu cfg1.ia = cp.CP0_Config1_IA; 2236376Sgblack@eecs.umich.edu cfg1.ds = cp.CP0_Config1_DS; 2246376Sgblack@eecs.umich.edu cfg1.dl = cp.CP0_Config1_DL; 2256376Sgblack@eecs.umich.edu cfg1.da = cp.CP0_Config1_DA; 2266376Sgblack@eecs.umich.edu cfg1.fp = cp.CP0_Config1_FP; 2276376Sgblack@eecs.umich.edu cfg1.ep = cp.CP0_Config1_EP; 2286376Sgblack@eecs.umich.edu cfg1.wr = cp.CP0_Config1_WR; 2296376Sgblack@eecs.umich.edu cfg1.md = cp.CP0_Config1_MD; 2306376Sgblack@eecs.umich.edu cfg1.c2 = cp.CP0_Config1_C2; 2316376Sgblack@eecs.umich.edu cfg1.pc = cp.CP0_Config1_PC; 2326376Sgblack@eecs.umich.edu cfg1.m = cp.CP0_Config1_M; 2336383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_CONFIG1, cfg1); 2346334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2356334Sgblack@eecs.umich.edu MiscReg cfg1_Mask = 0; // Read Only Register 2366376Sgblack@eecs.umich.edu replaceBits(cfg1_Mask, 0, 32, 0); 2376383Sgblack@eecs.umich.edu setRegMask(MISCREG_CONFIG1, cfg1_Mask); 2386334Sgblack@eecs.umich.edu 2396334Sgblack@eecs.umich.edu // Config2 2406383Sgblack@eecs.umich.edu Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2); 2416376Sgblack@eecs.umich.edu cfg2.tu = cp.CP0_Config2_TU; 2426376Sgblack@eecs.umich.edu cfg2.ts = cp.CP0_Config2_TS; 2436376Sgblack@eecs.umich.edu cfg2.tl = cp.CP0_Config2_TL; 2446376Sgblack@eecs.umich.edu cfg2.ta = cp.CP0_Config2_TA; 2456376Sgblack@eecs.umich.edu cfg2.su = cp.CP0_Config2_SU; 2466376Sgblack@eecs.umich.edu cfg2.ss = cp.CP0_Config2_SS; 2476376Sgblack@eecs.umich.edu cfg2.sl = cp.CP0_Config2_SL; 2486376Sgblack@eecs.umich.edu cfg2.sa = cp.CP0_Config2_SA; 2496376Sgblack@eecs.umich.edu cfg2.m = cp.CP0_Config2_M; 2506383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_CONFIG2, cfg2); 2516334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2526334Sgblack@eecs.umich.edu MiscReg cfg2_Mask = 0x7000F000; // Read Only Register 2536376Sgblack@eecs.umich.edu replaceBits(cfg2_Mask, 0, 32, 0); 2546383Sgblack@eecs.umich.edu setRegMask(MISCREG_CONFIG2, cfg2_Mask); 2556334Sgblack@eecs.umich.edu 2566334Sgblack@eecs.umich.edu // Config3 2576383Sgblack@eecs.umich.edu Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3); 2586376Sgblack@eecs.umich.edu cfg3.dspp = cp.CP0_Config3_DSPP; 2596376Sgblack@eecs.umich.edu cfg3.lpa = cp.CP0_Config3_LPA; 2606376Sgblack@eecs.umich.edu cfg3.veic = cp.CP0_Config3_VEIC; 2616376Sgblack@eecs.umich.edu cfg3.vint = cp.CP0_Config3_VInt; 2626376Sgblack@eecs.umich.edu cfg3.sp = cp.CP0_Config3_SP; 2636376Sgblack@eecs.umich.edu cfg3.mt = cp.CP0_Config3_MT; 2646376Sgblack@eecs.umich.edu cfg3.sm = cp.CP0_Config3_SM; 2656376Sgblack@eecs.umich.edu cfg3.tl = cp.CP0_Config3_TL; 2666383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_CONFIG3, cfg3); 2676334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2686334Sgblack@eecs.umich.edu MiscReg cfg3_Mask = 0; // Read Only Register 2696376Sgblack@eecs.umich.edu replaceBits(cfg3_Mask, 0, 32, 0); 2706383Sgblack@eecs.umich.edu setRegMask(MISCREG_CONFIG3, cfg3_Mask); 2716334Sgblack@eecs.umich.edu 2726334Sgblack@eecs.umich.edu // EBase - CPUNum 2736383Sgblack@eecs.umich.edu EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE); 2746376Sgblack@eecs.umich.edu eBase.cpuNum = cp.CP0_EBase_CPUNum; 2756376Sgblack@eecs.umich.edu replaceBits(eBase, 31, 31, 1); 2766383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_EBASE, eBase); 2776334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2786334Sgblack@eecs.umich.edu MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the 2796334Sgblack@eecs.umich.edu // entire register is read only 2806376Sgblack@eecs.umich.edu replaceBits(EB_Mask, 0, 32, 0); 2816383Sgblack@eecs.umich.edu setRegMask(MISCREG_EBASE, EB_Mask); 2826334Sgblack@eecs.umich.edu 2836334Sgblack@eecs.umich.edu // SRS Control - HSS (Highest Shadow Set) 2846383Sgblack@eecs.umich.edu SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL); 2856376Sgblack@eecs.umich.edu scsCtl.hss = cp.CP0_SrsCtl_HSS; 2866383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl); 2876334Sgblack@eecs.umich.edu // Now, create Write Mask for the SRS Ctl register 2886334Sgblack@eecs.umich.edu MiscReg SC_Mask = 0x0000F3C0; 2896376Sgblack@eecs.umich.edu replaceBits(SC_Mask, 0, 32, 0); 2906383Sgblack@eecs.umich.edu setRegMask(MISCREG_SRSCTL, SC_Mask); 2916334Sgblack@eecs.umich.edu 2926334Sgblack@eecs.umich.edu // IntCtl - IPTI, IPPCI 2936383Sgblack@eecs.umich.edu IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL); 2946376Sgblack@eecs.umich.edu intCtl.ipti = cp.CP0_IntCtl_IPTI; 2956376Sgblack@eecs.umich.edu intCtl.ippci = cp.CP0_IntCtl_IPPCI; 2966383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_INTCTL, intCtl); 2976334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 2986334Sgblack@eecs.umich.edu MiscReg IC_Mask = 0x000003E0; 2996376Sgblack@eecs.umich.edu replaceBits(IC_Mask, 0, 32, 0); 3006383Sgblack@eecs.umich.edu setRegMask(MISCREG_INTCTL, IC_Mask); 3016334Sgblack@eecs.umich.edu 3026334Sgblack@eecs.umich.edu // Watch Hi - M - FIXME (More than 1 Watch register) 3036383Sgblack@eecs.umich.edu WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0); 3046376Sgblack@eecs.umich.edu watchHi.m = cp.CP0_WatchHi_M; 3056383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi); 3066334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 3076334Sgblack@eecs.umich.edu MiscReg wh_Mask = 0x7FFF0FFF; 3086376Sgblack@eecs.umich.edu replaceBits(wh_Mask, 0, 32, 0); 3096383Sgblack@eecs.umich.edu setRegMask(MISCREG_WATCHHI0, wh_Mask); 3106334Sgblack@eecs.umich.edu 3116334Sgblack@eecs.umich.edu // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair) 3126383Sgblack@eecs.umich.edu PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0); 3136376Sgblack@eecs.umich.edu perfCntCtl.m = cp.CP0_PerfCtr_M; 3146376Sgblack@eecs.umich.edu perfCntCtl.w = cp.CP0_PerfCtr_W; 3156383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl); 3166334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 3176334Sgblack@eecs.umich.edu MiscReg pc_Mask = 0x00007FF; 3186376Sgblack@eecs.umich.edu replaceBits(pc_Mask, 0, 32, 0); 3196383Sgblack@eecs.umich.edu setRegMask(MISCREG_PERFCNT0, pc_Mask); 3206334Sgblack@eecs.umich.edu 3216334Sgblack@eecs.umich.edu // Random 3226383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63); 3236334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 3246334Sgblack@eecs.umich.edu MiscReg random_Mask = 0; 3256376Sgblack@eecs.umich.edu replaceBits(random_Mask, 0, 32, 0); 3266383Sgblack@eecs.umich.edu setRegMask(MISCREG_CP0_RANDOM, random_Mask); 3276334Sgblack@eecs.umich.edu 3286334Sgblack@eecs.umich.edu // PageGrain 3296383Sgblack@eecs.umich.edu PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN); 3306376Sgblack@eecs.umich.edu pageGrain.esp = cp.CP0_Config3_SP; 3316383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain); 3326334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 3336334Sgblack@eecs.umich.edu MiscReg pg_Mask = 0x10000000; 3346376Sgblack@eecs.umich.edu replaceBits(pg_Mask, 0, 32, 0); 3356383Sgblack@eecs.umich.edu setRegMask(MISCREG_PAGEGRAIN, pg_Mask); 3366334Sgblack@eecs.umich.edu 3376334Sgblack@eecs.umich.edu // Status 3386383Sgblack@eecs.umich.edu StatusReg status = readMiscRegNoEffect(MISCREG_STATUS); 3396334Sgblack@eecs.umich.edu // Only CU0 and IE are modified on a reset - everything else needs 3406334Sgblack@eecs.umich.edu // to be controlled on a per CPU model basis 3416334Sgblack@eecs.umich.edu 3426334Sgblack@eecs.umich.edu // Enable CP0 on reset 3436376Sgblack@eecs.umich.edu // status.cu0 = 1; 3446334Sgblack@eecs.umich.edu 3456334Sgblack@eecs.umich.edu // Enable ERL bit on a reset 3466376Sgblack@eecs.umich.edu status.erl = 1; 3476376Sgblack@eecs.umich.edu // Enable BEV bit on a reset 3486376Sgblack@eecs.umich.edu status.bev = 1; 3496334Sgblack@eecs.umich.edu 3506383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_STATUS, status); 3516334Sgblack@eecs.umich.edu // Now, create Write Mask for the Status register 3526334Sgblack@eecs.umich.edu MiscReg stat_Mask = 0xFF78FF17; 3536376Sgblack@eecs.umich.edu replaceBits(stat_Mask, 0, 32, 0); 3546383Sgblack@eecs.umich.edu setRegMask(MISCREG_STATUS, stat_Mask); 3556334Sgblack@eecs.umich.edu 3566334Sgblack@eecs.umich.edu 3576334Sgblack@eecs.umich.edu // MVPConf0 3586383Sgblack@eecs.umich.edu MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0); 3596376Sgblack@eecs.umich.edu mvpConf0.tca = 1; 3606376Sgblack@eecs.umich.edu mvpConf0.pvpe = num_vpes - 1; 3616376Sgblack@eecs.umich.edu mvpConf0.ptc = num_threads - 1; 3626383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0); 3636334Sgblack@eecs.umich.edu 3646334Sgblack@eecs.umich.edu // VPEConf0 3656383Sgblack@eecs.umich.edu VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0); 3666376Sgblack@eecs.umich.edu vpeConf0.mvp = 1; 3676383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0); 3686334Sgblack@eecs.umich.edu 3696334Sgblack@eecs.umich.edu // TCBind 3706334Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < num_threads; tid++) { 3716383Sgblack@eecs.umich.edu TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid); 3726376Sgblack@eecs.umich.edu tcBind.curTC = tid; 3736383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid); 3746334Sgblack@eecs.umich.edu } 3756334Sgblack@eecs.umich.edu // TCHalt 3766383Sgblack@eecs.umich.edu TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT); 3776376Sgblack@eecs.umich.edu tcHalt.h = 0; 3786383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt); 3796334Sgblack@eecs.umich.edu 3806334Sgblack@eecs.umich.edu // TCStatus 3816334Sgblack@eecs.umich.edu // Set TCStatus Activated to 1 for the initial thread that is running 3826383Sgblack@eecs.umich.edu TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS); 3836376Sgblack@eecs.umich.edu tcStatus.a = 1; 3846383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus); 3856334Sgblack@eecs.umich.edu 3866334Sgblack@eecs.umich.edu // Set Dynamically Allocatable bit to 1 for all other threads 3876334Sgblack@eecs.umich.edu for (ThreadID tid = 1; tid < num_threads; tid++) { 3886383Sgblack@eecs.umich.edu tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid); 3896376Sgblack@eecs.umich.edu tcStatus.da = 1; 3906383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid); 3916334Sgblack@eecs.umich.edu } 3926334Sgblack@eecs.umich.edu 3936334Sgblack@eecs.umich.edu 3946383Sgblack@eecs.umich.edu MiscReg mask = 0x7FFFFFFF; 3956334Sgblack@eecs.umich.edu 3966334Sgblack@eecs.umich.edu // Now, create Write Mask for the Index register 3976383Sgblack@eecs.umich.edu replaceBits(mask, 0, 32, 0); 3986383Sgblack@eecs.umich.edu setRegMask(MISCREG_INDEX, mask); 3996334Sgblack@eecs.umich.edu 4006383Sgblack@eecs.umich.edu mask = 0x3FFFFFFF; 4016383Sgblack@eecs.umich.edu replaceBits(mask, 0, 32, 0); 4026383Sgblack@eecs.umich.edu setRegMask(MISCREG_ENTRYLO0, mask); 4036383Sgblack@eecs.umich.edu setRegMask(MISCREG_ENTRYLO1, mask); 4046334Sgblack@eecs.umich.edu 4056383Sgblack@eecs.umich.edu mask = 0xFF800000; 4066383Sgblack@eecs.umich.edu replaceBits(mask, 0, 32, 0); 4076383Sgblack@eecs.umich.edu setRegMask(MISCREG_CONTEXT, mask); 4086334Sgblack@eecs.umich.edu 4096383Sgblack@eecs.umich.edu mask = 0x1FFFF800; 4106383Sgblack@eecs.umich.edu replaceBits(mask, 0, 32, 0); 4116383Sgblack@eecs.umich.edu setRegMask(MISCREG_PAGEMASK, mask); 4126334Sgblack@eecs.umich.edu 4136383Sgblack@eecs.umich.edu mask = 0x0; 4146383Sgblack@eecs.umich.edu replaceBits(mask, 0, 32, 0); 4156383Sgblack@eecs.umich.edu setRegMask(MISCREG_BADVADDR, mask); 4166383Sgblack@eecs.umich.edu setRegMask(MISCREG_LLADDR, mask); 4176334Sgblack@eecs.umich.edu 4186383Sgblack@eecs.umich.edu mask = 0x08C00300; 4196383Sgblack@eecs.umich.edu replaceBits(mask, 0, 32, 0); 4206383Sgblack@eecs.umich.edu setRegMask(MISCREG_CAUSE, mask); 4216334Sgblack@eecs.umich.edu 4226334Sgblack@eecs.umich.edu} 4236334Sgblack@eecs.umich.edu 4246334Sgblack@eecs.umich.eduinline unsigned 4256334Sgblack@eecs.umich.eduISA::getVPENum(ThreadID tid) 4266334Sgblack@eecs.umich.edu{ 4276383Sgblack@eecs.umich.edu TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid]; 4286376Sgblack@eecs.umich.edu return tcBind.curVPE; 4296313Sgblack@eecs.umich.edu} 4306313Sgblack@eecs.umich.edu 4316313Sgblack@eecs.umich.eduMiscReg 4326383Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) 4336313Sgblack@eecs.umich.edu{ 4346334Sgblack@eecs.umich.edu unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 4356334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4366334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n", 4376334Sgblack@eecs.umich.edu misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], 4386334Sgblack@eecs.umich.edu miscRegFile[misc_reg][reg_sel]); 4396334Sgblack@eecs.umich.edu return miscRegFile[misc_reg][reg_sel]; 4406313Sgblack@eecs.umich.edu} 4416313Sgblack@eecs.umich.edu 4426334Sgblack@eecs.umich.edu//@TODO: MIPS MT's register view automatically connects 4436334Sgblack@eecs.umich.edu// Status to TCStatus depending on current thread 4446334Sgblack@eecs.umich.edu//template <class TC> 4456313Sgblack@eecs.umich.eduMiscReg 4466383Sgblack@eecs.umich.eduISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) 4476313Sgblack@eecs.umich.edu{ 4486334Sgblack@eecs.umich.edu unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 4496334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4506334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 4516334Sgblack@eecs.umich.edu "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n", 4526334Sgblack@eecs.umich.edu misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], 4536334Sgblack@eecs.umich.edu miscRegFile[misc_reg][reg_sel]); 4546334Sgblack@eecs.umich.edu 4556378Sgblack@eecs.umich.edu return miscRegFile[misc_reg][reg_sel]; 4566313Sgblack@eecs.umich.edu} 4576313Sgblack@eecs.umich.edu 4586313Sgblack@eecs.umich.eduvoid 4596383Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) 4606313Sgblack@eecs.umich.edu{ 4616334Sgblack@eecs.umich.edu unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 4626334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4636334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 4646334Sgblack@eecs.umich.edu "[tid:%i]: Setting (direct set) CP0 Register:%u " 4656334Sgblack@eecs.umich.edu "Select:%u (%s) to %#x.\n", 4666334Sgblack@eecs.umich.edu tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 4676334Sgblack@eecs.umich.edu 4686334Sgblack@eecs.umich.edu miscRegFile[misc_reg][reg_sel] = val; 4696313Sgblack@eecs.umich.edu} 4706313Sgblack@eecs.umich.edu 4716313Sgblack@eecs.umich.eduvoid 4726383Sgblack@eecs.umich.eduISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid) 4736313Sgblack@eecs.umich.edu{ 4746334Sgblack@eecs.umich.edu unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 4756334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4766334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 4776334Sgblack@eecs.umich.edu "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n", 4786334Sgblack@eecs.umich.edu tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 4796334Sgblack@eecs.umich.edu miscRegFile_WriteMask[misc_reg][reg_sel] = val; 4806334Sgblack@eecs.umich.edu} 4816334Sgblack@eecs.umich.edu 4826334Sgblack@eecs.umich.edu// PROGRAMMER'S NOTES: 4836334Sgblack@eecs.umich.edu// (1) Some CP0 Registers have fields that cannot 4846334Sgblack@eecs.umich.edu// be overwritten. Make sure to handle those particular registers 4856334Sgblack@eecs.umich.edu// with care! 4866334Sgblack@eecs.umich.eduvoid 4876383Sgblack@eecs.umich.eduISA::setMiscReg(int misc_reg, const MiscReg &val, 4886334Sgblack@eecs.umich.edu ThreadContext *tc, ThreadID tid) 4896334Sgblack@eecs.umich.edu{ 4906334Sgblack@eecs.umich.edu int reg_sel = (bankType[misc_reg] == perThreadContext) 4916334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4926334Sgblack@eecs.umich.edu 4936334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 4946334Sgblack@eecs.umich.edu "[tid:%i]: Setting CP0 Register:%u " 4956334Sgblack@eecs.umich.edu "Select:%u (%s) to %#x, with effect.\n", 4966334Sgblack@eecs.umich.edu tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 4976334Sgblack@eecs.umich.edu 4986334Sgblack@eecs.umich.edu MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val); 4996334Sgblack@eecs.umich.edu 5006334Sgblack@eecs.umich.edu miscRegFile[misc_reg][reg_sel] = cp0_val; 5016334Sgblack@eecs.umich.edu 5026334Sgblack@eecs.umich.edu scheduleCP0Update(1); 5036334Sgblack@eecs.umich.edu} 5046334Sgblack@eecs.umich.edu 5056334Sgblack@eecs.umich.edu/** 5066334Sgblack@eecs.umich.edu * This method doesn't need to adjust the Control Register Offset 5076334Sgblack@eecs.umich.edu * since it has already been done in the calling method 5086334Sgblack@eecs.umich.edu * (setRegWithEffect) 5096334Sgblack@eecs.umich.edu*/ 5106334Sgblack@eecs.umich.eduMiscReg 5116334Sgblack@eecs.umich.eduISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) 5126334Sgblack@eecs.umich.edu{ 5136378Sgblack@eecs.umich.edu MiscReg retVal = val; 5146334Sgblack@eecs.umich.edu 5156378Sgblack@eecs.umich.edu // Mask off read-only regions 5166378Sgblack@eecs.umich.edu retVal &= miscRegFile_WriteMask[misc_reg][reg_sel]; 5176378Sgblack@eecs.umich.edu MiscReg curVal = miscRegFile[misc_reg][reg_sel]; 5186378Sgblack@eecs.umich.edu // Mask off current alue with inverse mask (clear writeable bits) 5196378Sgblack@eecs.umich.edu curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]); 5206378Sgblack@eecs.umich.edu retVal |= curVal; // Combine the two 5216378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 5226378Sgblack@eecs.umich.edu "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, " 5236378Sgblack@eecs.umich.edu "current val: %lx, written val: %x\n", 5246378Sgblack@eecs.umich.edu miscRegFile_WriteMask[misc_reg][reg_sel], 5256378Sgblack@eecs.umich.edu ~miscRegFile_WriteMask[misc_reg][reg_sel], 5266378Sgblack@eecs.umich.edu val, miscRegFile[misc_reg][reg_sel], retVal); 5276378Sgblack@eecs.umich.edu return retVal; 5286313Sgblack@eecs.umich.edu} 5296313Sgblack@eecs.umich.edu 5306313Sgblack@eecs.umich.eduvoid 5316334Sgblack@eecs.umich.eduISA::scheduleCP0Update(int delay) 5326313Sgblack@eecs.umich.edu{ 5336334Sgblack@eecs.umich.edu if (!cp0Updated) { 5346334Sgblack@eecs.umich.edu cp0Updated = true; 5356334Sgblack@eecs.umich.edu 5366334Sgblack@eecs.umich.edu //schedule UPDATE 5376334Sgblack@eecs.umich.edu CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0); 5386334Sgblack@eecs.umich.edu cpu->schedule(cp0_event, curTick + cpu->ticks(delay)); 5396334Sgblack@eecs.umich.edu } 5406313Sgblack@eecs.umich.edu} 5416313Sgblack@eecs.umich.edu 5426313Sgblack@eecs.umich.eduvoid 5436334Sgblack@eecs.umich.eduISA::updateCPU() 5446313Sgblack@eecs.umich.edu{ 5456334Sgblack@eecs.umich.edu /////////////////////////////////////////////////////////////////// 5466334Sgblack@eecs.umich.edu // 5476334Sgblack@eecs.umich.edu // EVALUATE CP0 STATE FOR MIPS MT 5486334Sgblack@eecs.umich.edu // 5496334Sgblack@eecs.umich.edu /////////////////////////////////////////////////////////////////// 5506383Sgblack@eecs.umich.edu MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0); 5516376Sgblack@eecs.umich.edu ThreadID num_threads = mvpConf0.ptc + 1; 5526334Sgblack@eecs.umich.edu 5536334Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < num_threads; tid++) { 5546383Sgblack@eecs.umich.edu TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid); 5556383Sgblack@eecs.umich.edu TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid); 5566334Sgblack@eecs.umich.edu 5576334Sgblack@eecs.umich.edu //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs 5586376Sgblack@eecs.umich.edu if (tcHalt.h == 1 || tcStatus.a == 0) { 5596334Sgblack@eecs.umich.edu haltThread(cpu->getContext(tid)); 5606376Sgblack@eecs.umich.edu } else if (tcHalt.h == 0 && tcStatus.a == 1) { 5616334Sgblack@eecs.umich.edu restoreThread(cpu->getContext(tid)); 5626334Sgblack@eecs.umich.edu } 5636334Sgblack@eecs.umich.edu } 5646334Sgblack@eecs.umich.edu 5656376Sgblack@eecs.umich.edu num_threads = mvpConf0.ptc + 1; 5666334Sgblack@eecs.umich.edu 5676334Sgblack@eecs.umich.edu // Toggle update flag after we finished updating 5686334Sgblack@eecs.umich.edu cp0Updated = false; 5696334Sgblack@eecs.umich.edu} 5706334Sgblack@eecs.umich.edu 5716334Sgblack@eecs.umich.eduISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type) 5726334Sgblack@eecs.umich.edu : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type) 5736334Sgblack@eecs.umich.edu{ } 5746334Sgblack@eecs.umich.edu 5756334Sgblack@eecs.umich.eduvoid 5766334Sgblack@eecs.umich.eduISA::CP0Event::process() 5776334Sgblack@eecs.umich.edu{ 5786334Sgblack@eecs.umich.edu switch (cp0EventType) 5796334Sgblack@eecs.umich.edu { 5806334Sgblack@eecs.umich.edu case UpdateCP0: 5816334Sgblack@eecs.umich.edu cp0->updateCPU(); 5826334Sgblack@eecs.umich.edu break; 5836334Sgblack@eecs.umich.edu } 5846334Sgblack@eecs.umich.edu} 5856334Sgblack@eecs.umich.edu 5866334Sgblack@eecs.umich.educonst char * 5876334Sgblack@eecs.umich.eduISA::CP0Event::description() const 5886334Sgblack@eecs.umich.edu{ 5896334Sgblack@eecs.umich.edu return "Coprocessor-0 event"; 5906334Sgblack@eecs.umich.edu} 5916334Sgblack@eecs.umich.edu 5926334Sgblack@eecs.umich.eduvoid 5936334Sgblack@eecs.umich.eduISA::CP0Event::scheduleEvent(int delay) 5946334Sgblack@eecs.umich.edu{ 5956334Sgblack@eecs.umich.edu cpu->reschedule(this, curTick + cpu->ticks(delay), true); 5966334Sgblack@eecs.umich.edu} 5976334Sgblack@eecs.umich.edu 5986334Sgblack@eecs.umich.eduvoid 5996334Sgblack@eecs.umich.eduISA::CP0Event::unscheduleEvent() 6006334Sgblack@eecs.umich.edu{ 6016334Sgblack@eecs.umich.edu if (scheduled()) 6026334Sgblack@eecs.umich.edu squash(); 6036313Sgblack@eecs.umich.edu} 6046313Sgblack@eecs.umich.edu 6056313Sgblack@eecs.umich.edu} 606