isa.cc revision 6334
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 36313Sgblack@eecs.umich.edu * All rights reserved. 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146313Sgblack@eecs.umich.edu * this software without specific prior written permission. 156313Sgblack@eecs.umich.edu * 166313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * Authors: Gabe Black 296313Sgblack@eecs.umich.edu */ 306313Sgblack@eecs.umich.edu 316313Sgblack@eecs.umich.edu#include "arch/mips/isa.hh" 326334Sgblack@eecs.umich.edu#include "arch/mips/mt_constants.hh" 336334Sgblack@eecs.umich.edu#include "arch/mips/mt.hh" 346334Sgblack@eecs.umich.edu#include "arch/mips/pra_constants.hh" 356334Sgblack@eecs.umich.edu#include "base/bitfield.hh" 366334Sgblack@eecs.umich.edu#include "cpu/base.hh" 376313Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 386313Sgblack@eecs.umich.edu 396313Sgblack@eecs.umich.edunamespace MipsISA 406313Sgblack@eecs.umich.edu{ 416313Sgblack@eecs.umich.edu 426334Sgblack@eecs.umich.edustd::string 436334Sgblack@eecs.umich.eduISA::miscRegNames[NumMiscRegs] = 446334Sgblack@eecs.umich.edu{ 456334Sgblack@eecs.umich.edu "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "", 466334Sgblack@eecs.umich.edu "Random", "VPEControl", "VPEConf0", "VPEConf1", 476334Sgblack@eecs.umich.edu "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt", 486334Sgblack@eecs.umich.edu "EntryLo0", "TCStatus", "TCBind", "TCRestart", 496334Sgblack@eecs.umich.edu "TCHalt", "TCContext", "TCSchedule", "TCScheFBack", 506334Sgblack@eecs.umich.edu "EntryLo1", "", "", "", "", "", "", "", 516334Sgblack@eecs.umich.edu "Context", "ContextConfig", "", "", "", "", "", "", 526334Sgblack@eecs.umich.edu "PageMask", "PageGrain", "", "", "", "", "", "", 536334Sgblack@eecs.umich.edu "Wired", "SRSConf0", "SRCConf1", "SRSConf2", 546334Sgblack@eecs.umich.edu "SRSConf3", "SRSConf4", "", "", 556334Sgblack@eecs.umich.edu "HWREna", "", "", "", "", "", "", "", 566334Sgblack@eecs.umich.edu "BadVAddr", "", "", "", "", "", "", "", 576334Sgblack@eecs.umich.edu "Count", "", "", "", "", "", "", "", 586334Sgblack@eecs.umich.edu "EntryHi", "", "", "", "", "", "", "", 596334Sgblack@eecs.umich.edu "Compare", "", "", "", "", "", "", "", 606334Sgblack@eecs.umich.edu "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "", 616334Sgblack@eecs.umich.edu "Cause", "", "", "", "", "", "", "", 626334Sgblack@eecs.umich.edu "EPC", "", "", "", "", "", "", "", 636334Sgblack@eecs.umich.edu "PRId", "EBase", "", "", "", "", "", "", 646334Sgblack@eecs.umich.edu "Config", "Config1", "Config2", "Config3", "", "", "", "", 656334Sgblack@eecs.umich.edu "LLAddr", "", "", "", "", "", "", "", 666334Sgblack@eecs.umich.edu "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3", 676334Sgblack@eecs.umich.edu "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7", 686334Sgblack@eecs.umich.edu "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3", 696334Sgblack@eecs.umich.edu "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7", 706334Sgblack@eecs.umich.edu "XCContext64", "", "", "", "", "", "", "", 716334Sgblack@eecs.umich.edu "", "", "", "", "", "", "", "", 726334Sgblack@eecs.umich.edu "", "", "", "", "", "", "", "", 736334Sgblack@eecs.umich.edu "Debug", "TraceControl1", "TraceControl2", "UserTraceData", 746334Sgblack@eecs.umich.edu "TraceBPC", "", "", "", 756334Sgblack@eecs.umich.edu "DEPC", "", "", "", "", "", "", "", 766334Sgblack@eecs.umich.edu "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3", 776334Sgblack@eecs.umich.edu "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7", 786334Sgblack@eecs.umich.edu "ErrCtl", "", "", "", "", "", "", "", 796334Sgblack@eecs.umich.edu "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "", 806334Sgblack@eecs.umich.edu "TagLo0", "DataLo1", "TagLo2", "DataLo3", 816334Sgblack@eecs.umich.edu "TagLo4", "DataLo5", "TagLo6", "DataLo7", 826334Sgblack@eecs.umich.edu "TagHi0", "DataHi1", "TagHi2", "DataHi3", 836334Sgblack@eecs.umich.edu "TagHi4", "DataHi5", "TagHi6", "DataHi7", 846334Sgblack@eecs.umich.edu "ErrorEPC", "", "", "", "", "", "", "", 856334Sgblack@eecs.umich.edu "DESAVE", "", "", "", "", "", "", "", 866334Sgblack@eecs.umich.edu "LLFlag" 876334Sgblack@eecs.umich.edu}; 886334Sgblack@eecs.umich.edu 896334Sgblack@eecs.umich.eduISA::ISA() 906334Sgblack@eecs.umich.edu{ 916334Sgblack@eecs.umich.edu init(); 926334Sgblack@eecs.umich.edu} 936334Sgblack@eecs.umich.edu 946334Sgblack@eecs.umich.eduISA::ISA(BaseCPU *_cpu) 956334Sgblack@eecs.umich.edu{ 966334Sgblack@eecs.umich.edu cpu = _cpu; 976334Sgblack@eecs.umich.edu init(); 986334Sgblack@eecs.umich.edu} 996334Sgblack@eecs.umich.edu 1006313Sgblack@eecs.umich.eduvoid 1016334Sgblack@eecs.umich.eduISA::init() 1026313Sgblack@eecs.umich.edu{ 1036334Sgblack@eecs.umich.edu miscRegFile.resize(NumMiscRegs); 1046334Sgblack@eecs.umich.edu bankType.resize(NumMiscRegs); 1056334Sgblack@eecs.umich.edu 1066334Sgblack@eecs.umich.edu for (int i=0; i < NumMiscRegs; i++) { 1076334Sgblack@eecs.umich.edu miscRegFile[i].resize(1); 1086334Sgblack@eecs.umich.edu bankType[i] = perProcessor; 1096334Sgblack@eecs.umich.edu } 1106334Sgblack@eecs.umich.edu 1116334Sgblack@eecs.umich.edu miscRegFile_WriteMask.resize(NumMiscRegs); 1126334Sgblack@eecs.umich.edu 1136334Sgblack@eecs.umich.edu for (int i=0; i < NumMiscRegs; i++) { 1146334Sgblack@eecs.umich.edu miscRegFile_WriteMask[i].push_back(0); 1156334Sgblack@eecs.umich.edu } 1166334Sgblack@eecs.umich.edu clear(0); 1176334Sgblack@eecs.umich.edu} 1186334Sgblack@eecs.umich.edu 1196334Sgblack@eecs.umich.eduvoid 1206334Sgblack@eecs.umich.eduISA::clear(unsigned tid_or_vpn) 1216334Sgblack@eecs.umich.edu{ 1226334Sgblack@eecs.umich.edu for(int i = 0; i < NumMiscRegs; i++) { 1236334Sgblack@eecs.umich.edu miscRegFile[i][tid_or_vpn] = 0; 1246334Sgblack@eecs.umich.edu miscRegFile_WriteMask[i][tid_or_vpn] = (long unsigned int)(-1); 1256334Sgblack@eecs.umich.edu } 1266334Sgblack@eecs.umich.edu} 1276334Sgblack@eecs.umich.edu 1286334Sgblack@eecs.umich.eduvoid 1296334Sgblack@eecs.umich.eduISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes) 1306334Sgblack@eecs.umich.edu{ 1316334Sgblack@eecs.umich.edu // Initialize all Per-VPE regs 1326334Sgblack@eecs.umich.edu uint32_t per_vpe_regs[] = { VPEControl, VPEConf0, VPEConf1, YQMask, 1336334Sgblack@eecs.umich.edu VPESchedule, VPEScheFBack, VPEOpt, SRSConf0, 1346334Sgblack@eecs.umich.edu SRSConf1, SRSConf2, SRSConf3, SRSConf4, 1356334Sgblack@eecs.umich.edu EBase 1366334Sgblack@eecs.umich.edu }; 1376334Sgblack@eecs.umich.edu uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4; 1386334Sgblack@eecs.umich.edu for (int i = 0; i < num_vpe_regs; i++) { 1396334Sgblack@eecs.umich.edu if (num_vpes > 1) { 1406334Sgblack@eecs.umich.edu miscRegFile[per_vpe_regs[i]].resize(num_vpes); 1416334Sgblack@eecs.umich.edu } 1426334Sgblack@eecs.umich.edu bankType[per_vpe_regs[i]] = perVirtProcessor; 1436334Sgblack@eecs.umich.edu } 1446334Sgblack@eecs.umich.edu 1456334Sgblack@eecs.umich.edu // Initialize all Per-TC regs 1466334Sgblack@eecs.umich.edu uint32_t per_tc_regs[] = { Status, TCStatus, TCBind, TCRestart, TCHalt, 1476334Sgblack@eecs.umich.edu TCContext, TCSchedule, TCScheFBack, Debug, 1486334Sgblack@eecs.umich.edu LLAddr 1496334Sgblack@eecs.umich.edu }; 1506334Sgblack@eecs.umich.edu uint32_t num_tc_regs = sizeof(per_tc_regs) / 4; 1516334Sgblack@eecs.umich.edu 1526334Sgblack@eecs.umich.edu for (int i = 0; i < num_tc_regs; i++) { 1536334Sgblack@eecs.umich.edu miscRegFile[per_tc_regs[i]].resize(num_threads); 1546334Sgblack@eecs.umich.edu bankType[per_tc_regs[i]] = perThreadContext; 1556334Sgblack@eecs.umich.edu } 1566334Sgblack@eecs.umich.edu 1576334Sgblack@eecs.umich.edu 1586334Sgblack@eecs.umich.edu if (num_vpes > 1) { 1596334Sgblack@eecs.umich.edu for (int i=1; i < num_vpes; i++) { 1606334Sgblack@eecs.umich.edu clear(i); 1616334Sgblack@eecs.umich.edu } 1626334Sgblack@eecs.umich.edu } 1636334Sgblack@eecs.umich.edu 1646334Sgblack@eecs.umich.edu} 1656334Sgblack@eecs.umich.edu 1666334Sgblack@eecs.umich.edu//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H) 1676334Sgblack@eecs.umich.eduvoid 1686334Sgblack@eecs.umich.eduISA::reset(std::string core_name, ThreadID num_threads, 1696334Sgblack@eecs.umich.edu unsigned num_vpes, BaseCPU *_cpu) 1706334Sgblack@eecs.umich.edu{ 1716334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n", 1726334Sgblack@eecs.umich.edu num_threads, num_vpes); 1736334Sgblack@eecs.umich.edu cpu = _cpu; 1746334Sgblack@eecs.umich.edu 1756334Sgblack@eecs.umich.edu MipsISA::CoreSpecific &cp = cpu->coreParams; 1766334Sgblack@eecs.umich.edu 1776334Sgblack@eecs.umich.edu // Do Default CP0 initialization HERE 1786334Sgblack@eecs.umich.edu 1796334Sgblack@eecs.umich.edu // Do Initialization for MT cores here (eventually use 1806334Sgblack@eecs.umich.edu // core_name parameter to toggle this initialization) 1816334Sgblack@eecs.umich.edu // =================================================== 1826334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Initializing CP0 State.... "); 1836334Sgblack@eecs.umich.edu 1846334Sgblack@eecs.umich.edu MiscReg ProcID = readMiscRegNoEffect(PRId); 1856334Sgblack@eecs.umich.edu replaceBits(ProcID,PRIdCoOp_HI,PRIdCoOp_LO,cp.CP0_PRId_CompanyOptions); 1866334Sgblack@eecs.umich.edu replaceBits(ProcID,PRIdCoID_HI,PRIdCoID_LO,cp.CP0_PRId_CompanyID); 1876334Sgblack@eecs.umich.edu replaceBits(ProcID,PRIdProc_ID_HI,PRIdProc_ID_LO,cp.CP0_PRId_ProcessorID); 1886334Sgblack@eecs.umich.edu replaceBits(ProcID,PRIdRev_HI,PRIdRev_LO,cp.CP0_PRId_Revision); 1896334Sgblack@eecs.umich.edu setMiscRegNoEffect(PRId,ProcID); 1906334Sgblack@eecs.umich.edu // Now, create Write Mask for ProcID register 1916334Sgblack@eecs.umich.edu MiscReg ProcID_Mask = 0; // Read-Only register 1926334Sgblack@eecs.umich.edu replaceBits(ProcID_Mask,0,32,0); 1936334Sgblack@eecs.umich.edu setRegMask(PRId,ProcID_Mask); 1946334Sgblack@eecs.umich.edu 1956334Sgblack@eecs.umich.edu // Config 1966334Sgblack@eecs.umich.edu MiscReg cfg = readMiscRegNoEffect(Config); 1976334Sgblack@eecs.umich.edu replaceBits(cfg, Config_BE_HI, Config_BE_LO, cp.CP0_Config_BE); 1986334Sgblack@eecs.umich.edu replaceBits(cfg, Config_AT_HI, Config_AT_LO, cp.CP0_Config_AT); 1996334Sgblack@eecs.umich.edu replaceBits(cfg, Config_AR_HI, Config_AR_LO, cp.CP0_Config_AR); 2006334Sgblack@eecs.umich.edu replaceBits(cfg, Config_MT_HI, Config_MT_LO, cp.CP0_Config_MT); 2016334Sgblack@eecs.umich.edu replaceBits(cfg, Config_VI_HI, Config_VI_LO, cp.CP0_Config_VI); 2026334Sgblack@eecs.umich.edu replaceBits(cfg, Config_M, 1); 2036334Sgblack@eecs.umich.edu setMiscRegNoEffect(Config, cfg); 2046334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2056334Sgblack@eecs.umich.edu MiscReg cfg_Mask = 0x7FFF0007; 2066334Sgblack@eecs.umich.edu replaceBits(cfg_Mask,0,32,0); 2076334Sgblack@eecs.umich.edu setRegMask(Config,cfg_Mask); 2086334Sgblack@eecs.umich.edu 2096334Sgblack@eecs.umich.edu // Config1 2106334Sgblack@eecs.umich.edu MiscReg cfg1 = readMiscRegNoEffect(Config1); 2116334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO, 2126334Sgblack@eecs.umich.edu cp.CP0_Config1_MMU); 2136334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, cp.CP0_Config1_IS); 2146334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_IL_HI, Config1_IL_LO, cp.CP0_Config1_IL); 2156334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_IA_HI, Config1_IA_LO, cp.CP0_Config1_IA); 2166334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_DS_HI, Config1_DS_LO, cp.CP0_Config1_DS); 2176334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_DL_HI, Config1_DL_LO, cp.CP0_Config1_DL); 2186334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_DA_HI, Config1_DA_LO, cp.CP0_Config1_DA); 2196334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_FP_HI, Config1_FP_LO, cp.CP0_Config1_FP); 2206334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_EP_HI, Config1_EP_LO, cp.CP0_Config1_EP); 2216334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_WR_HI, Config1_WR_LO, cp.CP0_Config1_WR); 2226334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_MD_HI, Config1_MD_LO, cp.CP0_Config1_MD); 2236334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_C2_HI, Config1_C2_LO, cp.CP0_Config1_C2); 2246334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_PC_HI, Config1_PC_LO, cp.CP0_Config1_PC); 2256334Sgblack@eecs.umich.edu replaceBits(cfg1, Config1_M, cp.CP0_Config1_M); 2266334Sgblack@eecs.umich.edu setMiscRegNoEffect(Config1, cfg1); 2276334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2286334Sgblack@eecs.umich.edu MiscReg cfg1_Mask = 0; // Read Only Register 2296334Sgblack@eecs.umich.edu replaceBits(cfg1_Mask,0,32,0); 2306334Sgblack@eecs.umich.edu setRegMask(Config1,cfg1_Mask); 2316334Sgblack@eecs.umich.edu 2326334Sgblack@eecs.umich.edu // Config2 2336334Sgblack@eecs.umich.edu MiscReg cfg2 = readMiscRegNoEffect(Config2); 2346334Sgblack@eecs.umich.edu replaceBits(cfg2, Config2_TU_HI, Config2_TU_LO, cp.CP0_Config2_TU); 2356334Sgblack@eecs.umich.edu replaceBits(cfg2, Config2_TS_HI, Config2_TS_LO, cp.CP0_Config2_TS); 2366334Sgblack@eecs.umich.edu replaceBits(cfg2, Config2_TL_HI, Config2_TL_LO, cp.CP0_Config2_TL); 2376334Sgblack@eecs.umich.edu replaceBits(cfg2, Config2_TA_HI, Config2_TA_LO, cp.CP0_Config2_TA); 2386334Sgblack@eecs.umich.edu replaceBits(cfg2, Config2_SU_HI, Config2_SU_LO, cp.CP0_Config2_SU); 2396334Sgblack@eecs.umich.edu replaceBits(cfg2, Config2_SS_HI, Config2_SS_LO, cp.CP0_Config2_SS); 2406334Sgblack@eecs.umich.edu replaceBits(cfg2, Config2_SL_HI, Config2_SL_LO, cp.CP0_Config2_SL); 2416334Sgblack@eecs.umich.edu replaceBits(cfg2, Config2_SA_HI, Config2_SA_LO, cp.CP0_Config2_SA); 2426334Sgblack@eecs.umich.edu replaceBits(cfg2, Config2_M, cp.CP0_Config2_M); 2436334Sgblack@eecs.umich.edu setMiscRegNoEffect(Config2, cfg2); 2446334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2456334Sgblack@eecs.umich.edu MiscReg cfg2_Mask = 0x7000F000; // Read Only Register 2466334Sgblack@eecs.umich.edu replaceBits(cfg2_Mask,0,32,0); 2476334Sgblack@eecs.umich.edu setRegMask(Config2,cfg2_Mask); 2486334Sgblack@eecs.umich.edu 2496334Sgblack@eecs.umich.edu // Config3 2506334Sgblack@eecs.umich.edu MiscReg cfg3 = readMiscRegNoEffect(Config3); 2516334Sgblack@eecs.umich.edu replaceBits(cfg3, Config3_DSPP_HI, Config3_DSPP_LO, cp.CP0_Config3_DSPP); 2526334Sgblack@eecs.umich.edu replaceBits(cfg3, Config3_LPA_HI, Config3_LPA_LO, cp.CP0_Config3_LPA); 2536334Sgblack@eecs.umich.edu replaceBits(cfg3, Config3_VEIC_HI, Config3_VEIC_LO, cp.CP0_Config3_VEIC); 2546334Sgblack@eecs.umich.edu replaceBits(cfg3, Config3_VINT_HI, Config3_VINT_LO, cp.CP0_Config3_VInt); 2556334Sgblack@eecs.umich.edu replaceBits(cfg3, Config3_SP_HI, Config3_SP_LO, cp.CP0_Config3_SP); 2566334Sgblack@eecs.umich.edu replaceBits(cfg3, Config3_MT_HI, Config3_MT_LO, cp.CP0_Config3_MT); 2576334Sgblack@eecs.umich.edu replaceBits(cfg3, Config3_SM_HI, Config3_SM_LO, cp.CP0_Config3_SM); 2586334Sgblack@eecs.umich.edu replaceBits(cfg3, Config3_TL_HI, Config3_TL_LO, cp.CP0_Config3_TL); 2596334Sgblack@eecs.umich.edu setMiscRegNoEffect(Config3, cfg3); 2606334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2616334Sgblack@eecs.umich.edu MiscReg cfg3_Mask = 0; // Read Only Register 2626334Sgblack@eecs.umich.edu replaceBits(cfg3_Mask,0,32,0); 2636334Sgblack@eecs.umich.edu setRegMask(Config3,cfg3_Mask); 2646334Sgblack@eecs.umich.edu 2656334Sgblack@eecs.umich.edu // EBase - CPUNum 2666334Sgblack@eecs.umich.edu MiscReg EB = readMiscRegNoEffect(EBase); 2676334Sgblack@eecs.umich.edu replaceBits(EB, EBase_CPUNum_HI, EBase_CPUNum_LO, cp.CP0_EBase_CPUNum); 2686334Sgblack@eecs.umich.edu replaceBits(EB, 31, 31, 1); 2696334Sgblack@eecs.umich.edu setMiscRegNoEffect(EBase, EB); 2706334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2716334Sgblack@eecs.umich.edu MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the 2726334Sgblack@eecs.umich.edu // entire register is read only 2736334Sgblack@eecs.umich.edu replaceBits(EB_Mask,0,32,0); 2746334Sgblack@eecs.umich.edu setRegMask(EBase,EB_Mask); 2756334Sgblack@eecs.umich.edu 2766334Sgblack@eecs.umich.edu // SRS Control - HSS (Highest Shadow Set) 2776334Sgblack@eecs.umich.edu MiscReg SC = readMiscRegNoEffect(SRSCtl); 2786334Sgblack@eecs.umich.edu replaceBits(SC, SRSCtl_HSS_HI,SRSCtl_HSS_LO,cp.CP0_SrsCtl_HSS); 2796334Sgblack@eecs.umich.edu setMiscRegNoEffect(SRSCtl, SC); 2806334Sgblack@eecs.umich.edu // Now, create Write Mask for the SRS Ctl register 2816334Sgblack@eecs.umich.edu MiscReg SC_Mask = 0x0000F3C0; 2826334Sgblack@eecs.umich.edu replaceBits(SC_Mask,0,32,0); 2836334Sgblack@eecs.umich.edu setRegMask(SRSCtl,SC_Mask); 2846334Sgblack@eecs.umich.edu 2856334Sgblack@eecs.umich.edu // IntCtl - IPTI, IPPCI 2866334Sgblack@eecs.umich.edu MiscReg IC = readMiscRegNoEffect(IntCtl); 2876334Sgblack@eecs.umich.edu replaceBits(IC, IntCtl_IPTI_HI,IntCtl_IPTI_LO,cp.CP0_IntCtl_IPTI); 2886334Sgblack@eecs.umich.edu replaceBits(IC, IntCtl_IPPCI_HI,IntCtl_IPPCI_LO,cp.CP0_IntCtl_IPPCI); 2896334Sgblack@eecs.umich.edu setMiscRegNoEffect(IntCtl, IC); 2906334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 2916334Sgblack@eecs.umich.edu MiscReg IC_Mask = 0x000003E0; 2926334Sgblack@eecs.umich.edu replaceBits(IC_Mask,0,32,0); 2936334Sgblack@eecs.umich.edu setRegMask(IntCtl,IC_Mask); 2946334Sgblack@eecs.umich.edu 2956334Sgblack@eecs.umich.edu // Watch Hi - M - FIXME (More than 1 Watch register) 2966334Sgblack@eecs.umich.edu MiscReg WHi = readMiscRegNoEffect(WatchHi0); 2976334Sgblack@eecs.umich.edu replaceBits(WHi, WatchHi_M, cp.CP0_WatchHi_M); 2986334Sgblack@eecs.umich.edu setMiscRegNoEffect(WatchHi0, WHi); 2996334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 3006334Sgblack@eecs.umich.edu MiscReg wh_Mask = 0x7FFF0FFF; 3016334Sgblack@eecs.umich.edu replaceBits(wh_Mask,0,32,0); 3026334Sgblack@eecs.umich.edu setRegMask(WatchHi0,wh_Mask); 3036334Sgblack@eecs.umich.edu 3046334Sgblack@eecs.umich.edu // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair) 3056334Sgblack@eecs.umich.edu MiscReg PCtr = readMiscRegNoEffect(PerfCnt0); 3066334Sgblack@eecs.umich.edu replaceBits(PCtr, PerfCntCtl_M, cp.CP0_PerfCtr_M); 3076334Sgblack@eecs.umich.edu replaceBits(PCtr, PerfCntCtl_W, cp.CP0_PerfCtr_W); 3086334Sgblack@eecs.umich.edu setMiscRegNoEffect(PerfCnt0, PCtr); 3096334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 3106334Sgblack@eecs.umich.edu MiscReg pc_Mask = 0x00007FF; 3116334Sgblack@eecs.umich.edu replaceBits(pc_Mask,0,32,0); 3126334Sgblack@eecs.umich.edu setRegMask(PerfCnt0,pc_Mask); 3136334Sgblack@eecs.umich.edu 3146334Sgblack@eecs.umich.edu // Random 3156334Sgblack@eecs.umich.edu MiscReg random = readMiscRegNoEffect(CP0_Random); 3166334Sgblack@eecs.umich.edu random = 63; 3176334Sgblack@eecs.umich.edu setMiscRegNoEffect(CP0_Random, random); 3186334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 3196334Sgblack@eecs.umich.edu MiscReg random_Mask = 0; 3206334Sgblack@eecs.umich.edu replaceBits(random_Mask,0,32,0); 3216334Sgblack@eecs.umich.edu setRegMask(CP0_Random,random_Mask); 3226334Sgblack@eecs.umich.edu 3236334Sgblack@eecs.umich.edu // PageGrain 3246334Sgblack@eecs.umich.edu MiscReg pagegrain = readMiscRegNoEffect(PageGrain); 3256334Sgblack@eecs.umich.edu replaceBits(pagegrain,PageGrain_ESP,cp.CP0_Config3_SP); 3266334Sgblack@eecs.umich.edu setMiscRegNoEffect(PageGrain, pagegrain); 3276334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 3286334Sgblack@eecs.umich.edu MiscReg pg_Mask = 0x10000000; 3296334Sgblack@eecs.umich.edu replaceBits(pg_Mask,0,32,0); 3306334Sgblack@eecs.umich.edu setRegMask(PageGrain,pg_Mask); 3316334Sgblack@eecs.umich.edu 3326334Sgblack@eecs.umich.edu // Status 3336334Sgblack@eecs.umich.edu MiscReg stat = readMiscRegNoEffect(Status); 3346334Sgblack@eecs.umich.edu // Only CU0 and IE are modified on a reset - everything else needs 3356334Sgblack@eecs.umich.edu // to be controlled on a per CPU model basis 3366334Sgblack@eecs.umich.edu 3376334Sgblack@eecs.umich.edu // Enable CP0 on reset 3386334Sgblack@eecs.umich.edu // replaceBits(stat, Status_CU0_HI,Status_CU0_LO, 1); 3396334Sgblack@eecs.umich.edu 3406334Sgblack@eecs.umich.edu // Enable ERL bit on a reset 3416334Sgblack@eecs.umich.edu replaceBits(stat, Status_ERL_HI, Status_ERL_LO, 1); 3426334Sgblack@eecs.umich.edu 3436334Sgblack@eecs.umich.edu // Enable BEV bit on a reset 3446334Sgblack@eecs.umich.edu replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1); 3456334Sgblack@eecs.umich.edu 3466334Sgblack@eecs.umich.edu setMiscRegNoEffect(Status, stat); 3476334Sgblack@eecs.umich.edu // Now, create Write Mask for the Status register 3486334Sgblack@eecs.umich.edu MiscReg stat_Mask = 0xFF78FF17; 3496334Sgblack@eecs.umich.edu replaceBits(stat_Mask,0,32,0); 3506334Sgblack@eecs.umich.edu setRegMask(Status,stat_Mask); 3516334Sgblack@eecs.umich.edu 3526334Sgblack@eecs.umich.edu 3536334Sgblack@eecs.umich.edu // MVPConf0 3546334Sgblack@eecs.umich.edu MiscReg mvp_conf0 = readMiscRegNoEffect(MVPConf0); 3556334Sgblack@eecs.umich.edu replaceBits(mvp_conf0, MVPC0_TCA, 1); 3566334Sgblack@eecs.umich.edu replaceBits(mvp_conf0, MVPC0_PVPE_HI, MVPC0_PVPE_LO, num_vpes - 1); 3576334Sgblack@eecs.umich.edu replaceBits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO, num_threads - 1); 3586334Sgblack@eecs.umich.edu setMiscRegNoEffect(MVPConf0, mvp_conf0); 3596334Sgblack@eecs.umich.edu 3606334Sgblack@eecs.umich.edu // VPEConf0 3616334Sgblack@eecs.umich.edu MiscReg vpe_conf0 = readMiscRegNoEffect(VPEConf0); 3626334Sgblack@eecs.umich.edu replaceBits(vpe_conf0, VPEC0_MVP, 1); 3636334Sgblack@eecs.umich.edu setMiscRegNoEffect(VPEConf0, vpe_conf0); 3646334Sgblack@eecs.umich.edu 3656334Sgblack@eecs.umich.edu // TCBind 3666334Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < num_threads; tid++) { 3676334Sgblack@eecs.umich.edu MiscReg tc_bind = readMiscRegNoEffect(TCBind, tid); 3686334Sgblack@eecs.umich.edu replaceBits(tc_bind, TCB_CUR_TC_HI, TCB_CUR_TC_LO, tid); 3696334Sgblack@eecs.umich.edu setMiscRegNoEffect(TCBind, tc_bind, tid); 3706334Sgblack@eecs.umich.edu } 3716334Sgblack@eecs.umich.edu // TCHalt 3726334Sgblack@eecs.umich.edu MiscReg tc_halt = readMiscRegNoEffect(TCHalt); 3736334Sgblack@eecs.umich.edu replaceBits(tc_halt, TCH_H, 0); 3746334Sgblack@eecs.umich.edu setMiscRegNoEffect(TCHalt, tc_halt); 3756334Sgblack@eecs.umich.edu /*for (ThreadID tid = 1; tid < num_threads; tid++) { 3766334Sgblack@eecs.umich.edu // Set TCHalt Halt bit to 1 for all other threads 3776334Sgblack@eecs.umich.edu tc_halt = readMiscRegNoEffect(TCHalt, tid); 3786334Sgblack@eecs.umich.edu replaceBits(tc_halt, TCH_H, 1); 3796334Sgblack@eecs.umich.edu setReg(TCHalt, tc_halt, tid); 3806334Sgblack@eecs.umich.edu }*/ 3816334Sgblack@eecs.umich.edu 3826334Sgblack@eecs.umich.edu // TCStatus 3836334Sgblack@eecs.umich.edu // Set TCStatus Activated to 1 for the initial thread that is running 3846334Sgblack@eecs.umich.edu MiscReg tc_status = readMiscRegNoEffect(TCStatus); 3856334Sgblack@eecs.umich.edu replaceBits(tc_status, TCS_A, 1); 3866334Sgblack@eecs.umich.edu setMiscRegNoEffect(TCStatus, tc_status); 3876334Sgblack@eecs.umich.edu 3886334Sgblack@eecs.umich.edu // Set Dynamically Allocatable bit to 1 for all other threads 3896334Sgblack@eecs.umich.edu for (ThreadID tid = 1; tid < num_threads; tid++) { 3906334Sgblack@eecs.umich.edu tc_status = readMiscRegNoEffect(TCStatus, tid); 3916334Sgblack@eecs.umich.edu replaceBits(tc_status, TCSTATUS_DA, 1); 3926334Sgblack@eecs.umich.edu setMiscRegNoEffect(TCStatus, tc_status, tid); 3936334Sgblack@eecs.umich.edu } 3946334Sgblack@eecs.umich.edu 3956334Sgblack@eecs.umich.edu 3966334Sgblack@eecs.umich.edu MiscReg Mask = 0x7FFFFFFF; 3976334Sgblack@eecs.umich.edu 3986334Sgblack@eecs.umich.edu // Now, create Write Mask for the Index register 3996334Sgblack@eecs.umich.edu replaceBits(Mask,0,32,0); 4006334Sgblack@eecs.umich.edu setRegMask(Index,Mask); 4016334Sgblack@eecs.umich.edu 4026334Sgblack@eecs.umich.edu Mask = 0x3FFFFFFF; 4036334Sgblack@eecs.umich.edu replaceBits(Mask,0,32,0); 4046334Sgblack@eecs.umich.edu setRegMask(EntryLo0,Mask); 4056334Sgblack@eecs.umich.edu setRegMask(EntryLo1,Mask); 4066334Sgblack@eecs.umich.edu 4076334Sgblack@eecs.umich.edu Mask = 0xFF800000; 4086334Sgblack@eecs.umich.edu replaceBits(Mask,0,32,0); 4096334Sgblack@eecs.umich.edu setRegMask(Context,Mask); 4106334Sgblack@eecs.umich.edu 4116334Sgblack@eecs.umich.edu Mask = 0x1FFFF800; 4126334Sgblack@eecs.umich.edu replaceBits(Mask,0,32,0); 4136334Sgblack@eecs.umich.edu setRegMask(PageMask,Mask); 4146334Sgblack@eecs.umich.edu 4156334Sgblack@eecs.umich.edu Mask = 0x0; 4166334Sgblack@eecs.umich.edu replaceBits(Mask,0,32,0); 4176334Sgblack@eecs.umich.edu setRegMask(BadVAddr,Mask); 4186334Sgblack@eecs.umich.edu setRegMask(LLAddr,Mask); 4196334Sgblack@eecs.umich.edu 4206334Sgblack@eecs.umich.edu Mask = 0x08C00300; 4216334Sgblack@eecs.umich.edu replaceBits(Mask,0,32,0); 4226334Sgblack@eecs.umich.edu setRegMask(Cause,Mask); 4236334Sgblack@eecs.umich.edu 4246334Sgblack@eecs.umich.edu} 4256334Sgblack@eecs.umich.edu 4266334Sgblack@eecs.umich.eduinline unsigned 4276334Sgblack@eecs.umich.eduISA::getVPENum(ThreadID tid) 4286334Sgblack@eecs.umich.edu{ 4296334Sgblack@eecs.umich.edu unsigned tc_bind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid]; 4306334Sgblack@eecs.umich.edu return bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO); 4316313Sgblack@eecs.umich.edu} 4326313Sgblack@eecs.umich.edu 4336313Sgblack@eecs.umich.eduMiscReg 4346334Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int reg_idx, ThreadID tid) 4356313Sgblack@eecs.umich.edu{ 4366334Sgblack@eecs.umich.edu int misc_reg = reg_idx - Ctrl_Base_DepTag; 4376334Sgblack@eecs.umich.edu unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 4386334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4396334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n", 4406334Sgblack@eecs.umich.edu misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], 4416334Sgblack@eecs.umich.edu miscRegFile[misc_reg][reg_sel]); 4426334Sgblack@eecs.umich.edu return miscRegFile[misc_reg][reg_sel]; 4436313Sgblack@eecs.umich.edu} 4446313Sgblack@eecs.umich.edu 4456334Sgblack@eecs.umich.edu//@TODO: MIPS MT's register view automatically connects 4466334Sgblack@eecs.umich.edu// Status to TCStatus depending on current thread 4476334Sgblack@eecs.umich.edu//template <class TC> 4486313Sgblack@eecs.umich.eduMiscReg 4496334Sgblack@eecs.umich.eduISA::readMiscReg(int reg_idx, ThreadContext *tc, ThreadID tid) 4506313Sgblack@eecs.umich.edu{ 4516334Sgblack@eecs.umich.edu int misc_reg = reg_idx - Ctrl_Base_DepTag; 4526334Sgblack@eecs.umich.edu unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 4536334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4546334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 4556334Sgblack@eecs.umich.edu "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n", 4566334Sgblack@eecs.umich.edu misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], 4576334Sgblack@eecs.umich.edu miscRegFile[misc_reg][reg_sel]); 4586334Sgblack@eecs.umich.edu 4596334Sgblack@eecs.umich.edu 4606334Sgblack@eecs.umich.edu switch (misc_reg) 4616334Sgblack@eecs.umich.edu { 4626334Sgblack@eecs.umich.edu default: 4636334Sgblack@eecs.umich.edu return miscRegFile[misc_reg][reg_sel]; 4646334Sgblack@eecs.umich.edu } 4656313Sgblack@eecs.umich.edu} 4666313Sgblack@eecs.umich.edu 4676313Sgblack@eecs.umich.eduvoid 4686334Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid) 4696313Sgblack@eecs.umich.edu{ 4706334Sgblack@eecs.umich.edu int misc_reg = reg_idx - Ctrl_Base_DepTag; 4716334Sgblack@eecs.umich.edu unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 4726334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4736334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 4746334Sgblack@eecs.umich.edu "[tid:%i]: Setting (direct set) CP0 Register:%u " 4756334Sgblack@eecs.umich.edu "Select:%u (%s) to %#x.\n", 4766334Sgblack@eecs.umich.edu tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 4776334Sgblack@eecs.umich.edu 4786334Sgblack@eecs.umich.edu miscRegFile[misc_reg][reg_sel] = val; 4796313Sgblack@eecs.umich.edu} 4806313Sgblack@eecs.umich.edu 4816313Sgblack@eecs.umich.eduvoid 4826334Sgblack@eecs.umich.eduISA::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid) 4836313Sgblack@eecs.umich.edu{ 4846334Sgblack@eecs.umich.edu // return; 4856334Sgblack@eecs.umich.edu int misc_reg = reg_idx - Ctrl_Base_DepTag; 4866334Sgblack@eecs.umich.edu unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 4876334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4886334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 4896334Sgblack@eecs.umich.edu "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n", 4906334Sgblack@eecs.umich.edu tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 4916334Sgblack@eecs.umich.edu miscRegFile_WriteMask[misc_reg][reg_sel] = val; 4926334Sgblack@eecs.umich.edu} 4936334Sgblack@eecs.umich.edu 4946334Sgblack@eecs.umich.edu// PROGRAMMER'S NOTES: 4956334Sgblack@eecs.umich.edu// (1) Some CP0 Registers have fields that cannot 4966334Sgblack@eecs.umich.edu// be overwritten. Make sure to handle those particular registers 4976334Sgblack@eecs.umich.edu// with care! 4986334Sgblack@eecs.umich.edu//template <class TC> 4996334Sgblack@eecs.umich.eduvoid 5006334Sgblack@eecs.umich.eduISA::setMiscReg(int reg_idx, const MiscReg &val, 5016334Sgblack@eecs.umich.edu ThreadContext *tc, ThreadID tid) 5026334Sgblack@eecs.umich.edu{ 5036334Sgblack@eecs.umich.edu int misc_reg = reg_idx - Ctrl_Base_DepTag; 5046334Sgblack@eecs.umich.edu int reg_sel = (bankType[misc_reg] == perThreadContext) 5056334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 5066334Sgblack@eecs.umich.edu 5076334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 5086334Sgblack@eecs.umich.edu "[tid:%i]: Setting CP0 Register:%u " 5096334Sgblack@eecs.umich.edu "Select:%u (%s) to %#x, with effect.\n", 5106334Sgblack@eecs.umich.edu tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 5116334Sgblack@eecs.umich.edu 5126334Sgblack@eecs.umich.edu MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val); 5136334Sgblack@eecs.umich.edu 5146334Sgblack@eecs.umich.edu miscRegFile[misc_reg][reg_sel] = cp0_val; 5156334Sgblack@eecs.umich.edu 5166334Sgblack@eecs.umich.edu scheduleCP0Update(1); 5176334Sgblack@eecs.umich.edu} 5186334Sgblack@eecs.umich.edu 5196334Sgblack@eecs.umich.edu/** 5206334Sgblack@eecs.umich.edu * This method doesn't need to adjust the Control Register Offset 5216334Sgblack@eecs.umich.edu * since it has already been done in the calling method 5226334Sgblack@eecs.umich.edu * (setRegWithEffect) 5236334Sgblack@eecs.umich.edu*/ 5246334Sgblack@eecs.umich.eduMiscReg 5256334Sgblack@eecs.umich.eduISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) 5266334Sgblack@eecs.umich.edu{ 5276334Sgblack@eecs.umich.edu MiscReg retVal = val; 5286334Sgblack@eecs.umich.edu 5296334Sgblack@eecs.umich.edu // Mask off read-only regions 5306334Sgblack@eecs.umich.edu retVal &= miscRegFile_WriteMask[misc_reg][reg_sel]; 5316334Sgblack@eecs.umich.edu MiscReg curVal = miscRegFile[misc_reg][reg_sel]; 5326334Sgblack@eecs.umich.edu // Mask off current alue with inverse mask (clear writeable bits) 5336334Sgblack@eecs.umich.edu curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]); 5346334Sgblack@eecs.umich.edu retVal |= curVal; // Combine the two 5356334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 5366334Sgblack@eecs.umich.edu "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, " 5376334Sgblack@eecs.umich.edu "current val: %lx, written val: %x\n", 5386334Sgblack@eecs.umich.edu miscRegFile_WriteMask[misc_reg][reg_sel], 5396334Sgblack@eecs.umich.edu ~miscRegFile_WriteMask[misc_reg][reg_sel], 5406334Sgblack@eecs.umich.edu val, miscRegFile[misc_reg][reg_sel], retVal); 5416334Sgblack@eecs.umich.edu return retVal; 5426313Sgblack@eecs.umich.edu} 5436313Sgblack@eecs.umich.edu 5446313Sgblack@eecs.umich.eduvoid 5456334Sgblack@eecs.umich.eduISA::scheduleCP0Update(int delay) 5466313Sgblack@eecs.umich.edu{ 5476334Sgblack@eecs.umich.edu if (!cp0Updated) { 5486334Sgblack@eecs.umich.edu cp0Updated = true; 5496334Sgblack@eecs.umich.edu 5506334Sgblack@eecs.umich.edu //schedule UPDATE 5516334Sgblack@eecs.umich.edu CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0); 5526334Sgblack@eecs.umich.edu cpu->schedule(cp0_event, curTick + cpu->ticks(delay)); 5536334Sgblack@eecs.umich.edu } 5546313Sgblack@eecs.umich.edu} 5556313Sgblack@eecs.umich.edu 5566313Sgblack@eecs.umich.eduvoid 5576334Sgblack@eecs.umich.eduISA::updateCPU() 5586313Sgblack@eecs.umich.edu{ 5596334Sgblack@eecs.umich.edu /////////////////////////////////////////////////////////////////// 5606334Sgblack@eecs.umich.edu // 5616334Sgblack@eecs.umich.edu // EVALUATE CP0 STATE FOR MIPS MT 5626334Sgblack@eecs.umich.edu // 5636334Sgblack@eecs.umich.edu /////////////////////////////////////////////////////////////////// 5646334Sgblack@eecs.umich.edu unsigned mvp_conf0 = readMiscRegNoEffect(MVPConf0); 5656334Sgblack@eecs.umich.edu ThreadID num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1; 5666334Sgblack@eecs.umich.edu 5676334Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < num_threads; tid++) { 5686334Sgblack@eecs.umich.edu MiscReg tc_status = readMiscRegNoEffect(TCStatus, tid); 5696334Sgblack@eecs.umich.edu MiscReg tc_halt = readMiscRegNoEffect(TCHalt, tid); 5706334Sgblack@eecs.umich.edu 5716334Sgblack@eecs.umich.edu //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs 5726334Sgblack@eecs.umich.edu if (bits(tc_halt, TCH_H) == 1 || bits(tc_status, TCS_A) == 0) { 5736334Sgblack@eecs.umich.edu haltThread(cpu->getContext(tid)); 5746334Sgblack@eecs.umich.edu } else if (bits(tc_halt, TCH_H) == 0 && bits(tc_status, TCS_A) == 1) { 5756334Sgblack@eecs.umich.edu restoreThread(cpu->getContext(tid)); 5766334Sgblack@eecs.umich.edu } 5776334Sgblack@eecs.umich.edu } 5786334Sgblack@eecs.umich.edu 5796334Sgblack@eecs.umich.edu num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1; 5806334Sgblack@eecs.umich.edu 5816334Sgblack@eecs.umich.edu // Toggle update flag after we finished updating 5826334Sgblack@eecs.umich.edu cp0Updated = false; 5836334Sgblack@eecs.umich.edu} 5846334Sgblack@eecs.umich.edu 5856334Sgblack@eecs.umich.eduISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type) 5866334Sgblack@eecs.umich.edu : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type) 5876334Sgblack@eecs.umich.edu{ } 5886334Sgblack@eecs.umich.edu 5896334Sgblack@eecs.umich.eduvoid 5906334Sgblack@eecs.umich.eduISA::CP0Event::process() 5916334Sgblack@eecs.umich.edu{ 5926334Sgblack@eecs.umich.edu switch (cp0EventType) 5936334Sgblack@eecs.umich.edu { 5946334Sgblack@eecs.umich.edu case UpdateCP0: 5956334Sgblack@eecs.umich.edu cp0->updateCPU(); 5966334Sgblack@eecs.umich.edu break; 5976334Sgblack@eecs.umich.edu } 5986334Sgblack@eecs.umich.edu 5996334Sgblack@eecs.umich.edu //cp0EventRemoveList.push(this); 6006334Sgblack@eecs.umich.edu} 6016334Sgblack@eecs.umich.edu 6026334Sgblack@eecs.umich.educonst char * 6036334Sgblack@eecs.umich.eduISA::CP0Event::description() const 6046334Sgblack@eecs.umich.edu{ 6056334Sgblack@eecs.umich.edu return "Coprocessor-0 event"; 6066334Sgblack@eecs.umich.edu} 6076334Sgblack@eecs.umich.edu 6086334Sgblack@eecs.umich.eduvoid 6096334Sgblack@eecs.umich.eduISA::CP0Event::scheduleEvent(int delay) 6106334Sgblack@eecs.umich.edu{ 6116334Sgblack@eecs.umich.edu cpu->reschedule(this, curTick + cpu->ticks(delay), true); 6126334Sgblack@eecs.umich.edu} 6136334Sgblack@eecs.umich.edu 6146334Sgblack@eecs.umich.eduvoid 6156334Sgblack@eecs.umich.eduISA::CP0Event::unscheduleEvent() 6166334Sgblack@eecs.umich.edu{ 6176334Sgblack@eecs.umich.edu if (scheduled()) 6186334Sgblack@eecs.umich.edu squash(); 6196313Sgblack@eecs.umich.edu} 6206313Sgblack@eecs.umich.edu 6216313Sgblack@eecs.umich.edu} 622