isa.cc revision 10844
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 36313Sgblack@eecs.umich.edu * All rights reserved. 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146313Sgblack@eecs.umich.edu * this software without specific prior written permission. 156313Sgblack@eecs.umich.edu * 166313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * Authors: Gabe Black 296313Sgblack@eecs.umich.edu */ 306313Sgblack@eecs.umich.edu 316313Sgblack@eecs.umich.edu#include "arch/mips/isa.hh" 328229Snate@binkert.org#include "arch/mips/mt.hh" 336334Sgblack@eecs.umich.edu#include "arch/mips/mt_constants.hh" 346334Sgblack@eecs.umich.edu#include "arch/mips/pra_constants.hh" 356334Sgblack@eecs.umich.edu#include "base/bitfield.hh" 366334Sgblack@eecs.umich.edu#include "cpu/base.hh" 376313Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 388232Snate@binkert.org#include "debug/MipsPRA.hh" 399384SAndreas.Sandberg@arm.com#include "params/MipsISA.hh" 406313Sgblack@eecs.umich.edu 416313Sgblack@eecs.umich.edunamespace MipsISA 426313Sgblack@eecs.umich.edu{ 436313Sgblack@eecs.umich.edu 446334Sgblack@eecs.umich.edustd::string 456334Sgblack@eecs.umich.eduISA::miscRegNames[NumMiscRegs] = 466334Sgblack@eecs.umich.edu{ 476334Sgblack@eecs.umich.edu "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "", 486334Sgblack@eecs.umich.edu "Random", "VPEControl", "VPEConf0", "VPEConf1", 496334Sgblack@eecs.umich.edu "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt", 506334Sgblack@eecs.umich.edu "EntryLo0", "TCStatus", "TCBind", "TCRestart", 516334Sgblack@eecs.umich.edu "TCHalt", "TCContext", "TCSchedule", "TCScheFBack", 526334Sgblack@eecs.umich.edu "EntryLo1", "", "", "", "", "", "", "", 536334Sgblack@eecs.umich.edu "Context", "ContextConfig", "", "", "", "", "", "", 546334Sgblack@eecs.umich.edu "PageMask", "PageGrain", "", "", "", "", "", "", 556334Sgblack@eecs.umich.edu "Wired", "SRSConf0", "SRCConf1", "SRSConf2", 566334Sgblack@eecs.umich.edu "SRSConf3", "SRSConf4", "", "", 576334Sgblack@eecs.umich.edu "HWREna", "", "", "", "", "", "", "", 586334Sgblack@eecs.umich.edu "BadVAddr", "", "", "", "", "", "", "", 596334Sgblack@eecs.umich.edu "Count", "", "", "", "", "", "", "", 606334Sgblack@eecs.umich.edu "EntryHi", "", "", "", "", "", "", "", 616334Sgblack@eecs.umich.edu "Compare", "", "", "", "", "", "", "", 626334Sgblack@eecs.umich.edu "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "", 636334Sgblack@eecs.umich.edu "Cause", "", "", "", "", "", "", "", 646334Sgblack@eecs.umich.edu "EPC", "", "", "", "", "", "", "", 656334Sgblack@eecs.umich.edu "PRId", "EBase", "", "", "", "", "", "", 666334Sgblack@eecs.umich.edu "Config", "Config1", "Config2", "Config3", "", "", "", "", 676334Sgblack@eecs.umich.edu "LLAddr", "", "", "", "", "", "", "", 686334Sgblack@eecs.umich.edu "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3", 696334Sgblack@eecs.umich.edu "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7", 706334Sgblack@eecs.umich.edu "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3", 716334Sgblack@eecs.umich.edu "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7", 726334Sgblack@eecs.umich.edu "XCContext64", "", "", "", "", "", "", "", 736334Sgblack@eecs.umich.edu "", "", "", "", "", "", "", "", 746334Sgblack@eecs.umich.edu "", "", "", "", "", "", "", "", 756334Sgblack@eecs.umich.edu "Debug", "TraceControl1", "TraceControl2", "UserTraceData", 766334Sgblack@eecs.umich.edu "TraceBPC", "", "", "", 776334Sgblack@eecs.umich.edu "DEPC", "", "", "", "", "", "", "", 786334Sgblack@eecs.umich.edu "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3", 796334Sgblack@eecs.umich.edu "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7", 806334Sgblack@eecs.umich.edu "ErrCtl", "", "", "", "", "", "", "", 816334Sgblack@eecs.umich.edu "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "", 826334Sgblack@eecs.umich.edu "TagLo0", "DataLo1", "TagLo2", "DataLo3", 836334Sgblack@eecs.umich.edu "TagLo4", "DataLo5", "TagLo6", "DataLo7", 846334Sgblack@eecs.umich.edu "TagHi0", "DataHi1", "TagHi2", "DataHi3", 856334Sgblack@eecs.umich.edu "TagHi4", "DataHi5", "TagHi6", "DataHi7", 866334Sgblack@eecs.umich.edu "ErrorEPC", "", "", "", "", "", "", "", 876334Sgblack@eecs.umich.edu "DESAVE", "", "", "", "", "", "", "", 886334Sgblack@eecs.umich.edu "LLFlag" 896334Sgblack@eecs.umich.edu}; 906334Sgblack@eecs.umich.edu 919384SAndreas.Sandberg@arm.comISA::ISA(Params *p) 9210033SAli.Saidi@ARM.com : SimObject(p), numThreads(p->num_threads), numVpes(p->num_vpes) 936334Sgblack@eecs.umich.edu{ 946334Sgblack@eecs.umich.edu miscRegFile.resize(NumMiscRegs); 956334Sgblack@eecs.umich.edu bankType.resize(NumMiscRegs); 966334Sgblack@eecs.umich.edu 976334Sgblack@eecs.umich.edu for (int i=0; i < NumMiscRegs; i++) { 986334Sgblack@eecs.umich.edu miscRegFile[i].resize(1); 996334Sgblack@eecs.umich.edu bankType[i] = perProcessor; 1006334Sgblack@eecs.umich.edu } 1016334Sgblack@eecs.umich.edu 1026334Sgblack@eecs.umich.edu miscRegFile_WriteMask.resize(NumMiscRegs); 1036334Sgblack@eecs.umich.edu 1046376Sgblack@eecs.umich.edu for (int i = 0; i < NumMiscRegs; i++) { 1056376Sgblack@eecs.umich.edu miscRegFile_WriteMask[i].push_back(0); 1066334Sgblack@eecs.umich.edu } 1076334Sgblack@eecs.umich.edu 1086334Sgblack@eecs.umich.edu // Initialize all Per-VPE regs 1096383Sgblack@eecs.umich.edu uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL, 1106383Sgblack@eecs.umich.edu MISCREG_VPE_CONF0, MISCREG_VPE_CONF1, 1116383Sgblack@eecs.umich.edu MISCREG_YQMASK, 1126383Sgblack@eecs.umich.edu MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK, 1136383Sgblack@eecs.umich.edu MISCREG_VPE_OPT, MISCREG_SRS_CONF0, 1146383Sgblack@eecs.umich.edu MISCREG_SRS_CONF1, MISCREG_SRS_CONF2, 1156383Sgblack@eecs.umich.edu MISCREG_SRS_CONF3, MISCREG_SRS_CONF4, 1166383Sgblack@eecs.umich.edu MISCREG_EBASE 1176334Sgblack@eecs.umich.edu }; 1186334Sgblack@eecs.umich.edu uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4; 1196334Sgblack@eecs.umich.edu for (int i = 0; i < num_vpe_regs; i++) { 1208181Sksewell@umich.edu if (numVpes > 1) { 1218181Sksewell@umich.edu miscRegFile[per_vpe_regs[i]].resize(numVpes); 1226334Sgblack@eecs.umich.edu } 1236334Sgblack@eecs.umich.edu bankType[per_vpe_regs[i]] = perVirtProcessor; 1246334Sgblack@eecs.umich.edu } 1256334Sgblack@eecs.umich.edu 1266334Sgblack@eecs.umich.edu // Initialize all Per-TC regs 1276383Sgblack@eecs.umich.edu uint32_t per_tc_regs[] = { MISCREG_STATUS, 1286383Sgblack@eecs.umich.edu MISCREG_TC_STATUS, MISCREG_TC_BIND, 1296383Sgblack@eecs.umich.edu MISCREG_TC_RESTART, MISCREG_TC_HALT, 1306383Sgblack@eecs.umich.edu MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE, 1316383Sgblack@eecs.umich.edu MISCREG_TC_SCHEFBACK, 1326383Sgblack@eecs.umich.edu MISCREG_DEBUG, MISCREG_LLADDR 1336334Sgblack@eecs.umich.edu }; 1346334Sgblack@eecs.umich.edu uint32_t num_tc_regs = sizeof(per_tc_regs) / 4; 1356334Sgblack@eecs.umich.edu 1366334Sgblack@eecs.umich.edu for (int i = 0; i < num_tc_regs; i++) { 1378181Sksewell@umich.edu miscRegFile[per_tc_regs[i]].resize(numThreads); 1386334Sgblack@eecs.umich.edu bankType[per_tc_regs[i]] = perThreadContext; 1396334Sgblack@eecs.umich.edu } 1406334Sgblack@eecs.umich.edu 1418181Sksewell@umich.edu clear(); 1426334Sgblack@eecs.umich.edu} 1436334Sgblack@eecs.umich.edu 1449384SAndreas.Sandberg@arm.comconst MipsISAParams * 1459384SAndreas.Sandberg@arm.comISA::params() const 1469384SAndreas.Sandberg@arm.com{ 1479384SAndreas.Sandberg@arm.com return dynamic_cast<const Params *>(_params); 1489384SAndreas.Sandberg@arm.com} 1499384SAndreas.Sandberg@arm.com 1506334Sgblack@eecs.umich.eduvoid 1518181Sksewell@umich.eduISA::clear() 1528181Sksewell@umich.edu{ 1538181Sksewell@umich.edu for(int i = 0; i < NumMiscRegs; i++) { 1548181Sksewell@umich.edu for (int j = 0; j < miscRegFile[i].size(); j++) 1558181Sksewell@umich.edu miscRegFile[i][j] = 0; 1568181Sksewell@umich.edu 1578181Sksewell@umich.edu for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++) 1588181Sksewell@umich.edu miscRegFile_WriteMask[i][k] = (long unsigned int)(-1); 1598181Sksewell@umich.edu } 1608181Sksewell@umich.edu} 1618181Sksewell@umich.edu 1628181Sksewell@umich.edu 1638181Sksewell@umich.eduvoid 1648181Sksewell@umich.eduISA::configCP() 1656334Sgblack@eecs.umich.edu{ 1666334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n", 1678181Sksewell@umich.edu numThreads, numVpes); 1686334Sgblack@eecs.umich.edu 1698181Sksewell@umich.edu CoreSpecific cp; 1708181Sksewell@umich.edu panic("CP state must be set before the following code is used"); 1716334Sgblack@eecs.umich.edu 1726334Sgblack@eecs.umich.edu // Do Default CP0 initialization HERE 1736334Sgblack@eecs.umich.edu 1746334Sgblack@eecs.umich.edu // Do Initialization for MT cores here (eventually use 1756334Sgblack@eecs.umich.edu // core_name parameter to toggle this initialization) 1766334Sgblack@eecs.umich.edu // =================================================== 1776334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Initializing CP0 State.... "); 1786334Sgblack@eecs.umich.edu 1796383Sgblack@eecs.umich.edu PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID); 1806376Sgblack@eecs.umich.edu procId.coOp = cp.CP0_PRId_CompanyOptions; 1816376Sgblack@eecs.umich.edu procId.coId = cp.CP0_PRId_CompanyID; 1826376Sgblack@eecs.umich.edu procId.procId = cp.CP0_PRId_ProcessorID; 1836376Sgblack@eecs.umich.edu procId.rev = cp.CP0_PRId_Revision; 1846383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_PRID, procId); 1856376Sgblack@eecs.umich.edu 1866334Sgblack@eecs.umich.edu // Now, create Write Mask for ProcID register 1876383Sgblack@eecs.umich.edu MiscReg procIDMask = 0; // Read-Only register 1886383Sgblack@eecs.umich.edu replaceBits(procIDMask, 0, 32, 0); 1896383Sgblack@eecs.umich.edu setRegMask(MISCREG_PRID, procIDMask); 1906334Sgblack@eecs.umich.edu 1916334Sgblack@eecs.umich.edu // Config 1926383Sgblack@eecs.umich.edu ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG); 1936376Sgblack@eecs.umich.edu cfg.be = cp.CP0_Config_BE; 1946376Sgblack@eecs.umich.edu cfg.at = cp.CP0_Config_AT; 1956376Sgblack@eecs.umich.edu cfg.ar = cp.CP0_Config_AR; 1966376Sgblack@eecs.umich.edu cfg.mt = cp.CP0_Config_MT; 1976376Sgblack@eecs.umich.edu cfg.vi = cp.CP0_Config_VI; 1986376Sgblack@eecs.umich.edu cfg.m = 1; 1996383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_CONFIG, cfg); 2006334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2016334Sgblack@eecs.umich.edu MiscReg cfg_Mask = 0x7FFF0007; 2026376Sgblack@eecs.umich.edu replaceBits(cfg_Mask, 0, 32, 0); 2036383Sgblack@eecs.umich.edu setRegMask(MISCREG_CONFIG, cfg_Mask); 2046334Sgblack@eecs.umich.edu 2056334Sgblack@eecs.umich.edu // Config1 2066383Sgblack@eecs.umich.edu Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1); 2076376Sgblack@eecs.umich.edu cfg1.mmuSize = cp.CP0_Config1_MMU; 2086376Sgblack@eecs.umich.edu cfg1.is = cp.CP0_Config1_IS; 2096376Sgblack@eecs.umich.edu cfg1.il = cp.CP0_Config1_IL; 2106376Sgblack@eecs.umich.edu cfg1.ia = cp.CP0_Config1_IA; 2116376Sgblack@eecs.umich.edu cfg1.ds = cp.CP0_Config1_DS; 2126376Sgblack@eecs.umich.edu cfg1.dl = cp.CP0_Config1_DL; 2136376Sgblack@eecs.umich.edu cfg1.da = cp.CP0_Config1_DA; 2146376Sgblack@eecs.umich.edu cfg1.fp = cp.CP0_Config1_FP; 2156376Sgblack@eecs.umich.edu cfg1.ep = cp.CP0_Config1_EP; 2166376Sgblack@eecs.umich.edu cfg1.wr = cp.CP0_Config1_WR; 2176376Sgblack@eecs.umich.edu cfg1.md = cp.CP0_Config1_MD; 2186376Sgblack@eecs.umich.edu cfg1.c2 = cp.CP0_Config1_C2; 2196376Sgblack@eecs.umich.edu cfg1.pc = cp.CP0_Config1_PC; 2206376Sgblack@eecs.umich.edu cfg1.m = cp.CP0_Config1_M; 2216383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_CONFIG1, cfg1); 2226334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2236334Sgblack@eecs.umich.edu MiscReg cfg1_Mask = 0; // Read Only Register 2246376Sgblack@eecs.umich.edu replaceBits(cfg1_Mask, 0, 32, 0); 2256383Sgblack@eecs.umich.edu setRegMask(MISCREG_CONFIG1, cfg1_Mask); 2266334Sgblack@eecs.umich.edu 2276334Sgblack@eecs.umich.edu // Config2 2286383Sgblack@eecs.umich.edu Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2); 2296376Sgblack@eecs.umich.edu cfg2.tu = cp.CP0_Config2_TU; 2306376Sgblack@eecs.umich.edu cfg2.ts = cp.CP0_Config2_TS; 2316376Sgblack@eecs.umich.edu cfg2.tl = cp.CP0_Config2_TL; 2326376Sgblack@eecs.umich.edu cfg2.ta = cp.CP0_Config2_TA; 2336376Sgblack@eecs.umich.edu cfg2.su = cp.CP0_Config2_SU; 2346376Sgblack@eecs.umich.edu cfg2.ss = cp.CP0_Config2_SS; 2356376Sgblack@eecs.umich.edu cfg2.sl = cp.CP0_Config2_SL; 2366376Sgblack@eecs.umich.edu cfg2.sa = cp.CP0_Config2_SA; 2376376Sgblack@eecs.umich.edu cfg2.m = cp.CP0_Config2_M; 2386383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_CONFIG2, cfg2); 2396334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2406334Sgblack@eecs.umich.edu MiscReg cfg2_Mask = 0x7000F000; // Read Only Register 2416376Sgblack@eecs.umich.edu replaceBits(cfg2_Mask, 0, 32, 0); 2426383Sgblack@eecs.umich.edu setRegMask(MISCREG_CONFIG2, cfg2_Mask); 2436334Sgblack@eecs.umich.edu 2446334Sgblack@eecs.umich.edu // Config3 2456383Sgblack@eecs.umich.edu Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3); 2466376Sgblack@eecs.umich.edu cfg3.dspp = cp.CP0_Config3_DSPP; 2476376Sgblack@eecs.umich.edu cfg3.lpa = cp.CP0_Config3_LPA; 2486376Sgblack@eecs.umich.edu cfg3.veic = cp.CP0_Config3_VEIC; 2496376Sgblack@eecs.umich.edu cfg3.vint = cp.CP0_Config3_VInt; 2506376Sgblack@eecs.umich.edu cfg3.sp = cp.CP0_Config3_SP; 2516376Sgblack@eecs.umich.edu cfg3.mt = cp.CP0_Config3_MT; 2526376Sgblack@eecs.umich.edu cfg3.sm = cp.CP0_Config3_SM; 2536376Sgblack@eecs.umich.edu cfg3.tl = cp.CP0_Config3_TL; 2546383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_CONFIG3, cfg3); 2556334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2566334Sgblack@eecs.umich.edu MiscReg cfg3_Mask = 0; // Read Only Register 2576376Sgblack@eecs.umich.edu replaceBits(cfg3_Mask, 0, 32, 0); 2586383Sgblack@eecs.umich.edu setRegMask(MISCREG_CONFIG3, cfg3_Mask); 2596334Sgblack@eecs.umich.edu 2606334Sgblack@eecs.umich.edu // EBase - CPUNum 2616383Sgblack@eecs.umich.edu EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE); 2626376Sgblack@eecs.umich.edu eBase.cpuNum = cp.CP0_EBase_CPUNum; 2636376Sgblack@eecs.umich.edu replaceBits(eBase, 31, 31, 1); 2646383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_EBASE, eBase); 2656334Sgblack@eecs.umich.edu // Now, create Write Mask for Config register 2666334Sgblack@eecs.umich.edu MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the 2676334Sgblack@eecs.umich.edu // entire register is read only 2686376Sgblack@eecs.umich.edu replaceBits(EB_Mask, 0, 32, 0); 2696383Sgblack@eecs.umich.edu setRegMask(MISCREG_EBASE, EB_Mask); 2706334Sgblack@eecs.umich.edu 2716334Sgblack@eecs.umich.edu // SRS Control - HSS (Highest Shadow Set) 2726383Sgblack@eecs.umich.edu SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL); 2736376Sgblack@eecs.umich.edu scsCtl.hss = cp.CP0_SrsCtl_HSS; 2746383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl); 2756334Sgblack@eecs.umich.edu // Now, create Write Mask for the SRS Ctl register 2766334Sgblack@eecs.umich.edu MiscReg SC_Mask = 0x0000F3C0; 2776376Sgblack@eecs.umich.edu replaceBits(SC_Mask, 0, 32, 0); 2786383Sgblack@eecs.umich.edu setRegMask(MISCREG_SRSCTL, SC_Mask); 2796334Sgblack@eecs.umich.edu 2806334Sgblack@eecs.umich.edu // IntCtl - IPTI, IPPCI 2816383Sgblack@eecs.umich.edu IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL); 2826376Sgblack@eecs.umich.edu intCtl.ipti = cp.CP0_IntCtl_IPTI; 2836376Sgblack@eecs.umich.edu intCtl.ippci = cp.CP0_IntCtl_IPPCI; 2846383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_INTCTL, intCtl); 2856334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 2866334Sgblack@eecs.umich.edu MiscReg IC_Mask = 0x000003E0; 2876376Sgblack@eecs.umich.edu replaceBits(IC_Mask, 0, 32, 0); 2886383Sgblack@eecs.umich.edu setRegMask(MISCREG_INTCTL, IC_Mask); 2896334Sgblack@eecs.umich.edu 2906334Sgblack@eecs.umich.edu // Watch Hi - M - FIXME (More than 1 Watch register) 2916383Sgblack@eecs.umich.edu WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0); 2926376Sgblack@eecs.umich.edu watchHi.m = cp.CP0_WatchHi_M; 2936383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi); 2946334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 2956334Sgblack@eecs.umich.edu MiscReg wh_Mask = 0x7FFF0FFF; 2966376Sgblack@eecs.umich.edu replaceBits(wh_Mask, 0, 32, 0); 2976383Sgblack@eecs.umich.edu setRegMask(MISCREG_WATCHHI0, wh_Mask); 2986334Sgblack@eecs.umich.edu 2996334Sgblack@eecs.umich.edu // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair) 3006383Sgblack@eecs.umich.edu PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0); 3016376Sgblack@eecs.umich.edu perfCntCtl.m = cp.CP0_PerfCtr_M; 3026376Sgblack@eecs.umich.edu perfCntCtl.w = cp.CP0_PerfCtr_W; 3036383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl); 3046334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 3056334Sgblack@eecs.umich.edu MiscReg pc_Mask = 0x00007FF; 3066376Sgblack@eecs.umich.edu replaceBits(pc_Mask, 0, 32, 0); 3076383Sgblack@eecs.umich.edu setRegMask(MISCREG_PERFCNT0, pc_Mask); 3086334Sgblack@eecs.umich.edu 3096334Sgblack@eecs.umich.edu // Random 3106383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63); 3116334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 3126334Sgblack@eecs.umich.edu MiscReg random_Mask = 0; 3136376Sgblack@eecs.umich.edu replaceBits(random_Mask, 0, 32, 0); 3146383Sgblack@eecs.umich.edu setRegMask(MISCREG_CP0_RANDOM, random_Mask); 3156334Sgblack@eecs.umich.edu 3166334Sgblack@eecs.umich.edu // PageGrain 3176383Sgblack@eecs.umich.edu PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN); 3186376Sgblack@eecs.umich.edu pageGrain.esp = cp.CP0_Config3_SP; 3196383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain); 3206334Sgblack@eecs.umich.edu // Now, create Write Mask for the IntCtl register 3216334Sgblack@eecs.umich.edu MiscReg pg_Mask = 0x10000000; 3226376Sgblack@eecs.umich.edu replaceBits(pg_Mask, 0, 32, 0); 3236383Sgblack@eecs.umich.edu setRegMask(MISCREG_PAGEGRAIN, pg_Mask); 3246334Sgblack@eecs.umich.edu 3256334Sgblack@eecs.umich.edu // Status 3266383Sgblack@eecs.umich.edu StatusReg status = readMiscRegNoEffect(MISCREG_STATUS); 3276334Sgblack@eecs.umich.edu // Only CU0 and IE are modified on a reset - everything else needs 3286334Sgblack@eecs.umich.edu // to be controlled on a per CPU model basis 3296334Sgblack@eecs.umich.edu 3306334Sgblack@eecs.umich.edu // Enable CP0 on reset 3316376Sgblack@eecs.umich.edu // status.cu0 = 1; 3326334Sgblack@eecs.umich.edu 3336334Sgblack@eecs.umich.edu // Enable ERL bit on a reset 3346376Sgblack@eecs.umich.edu status.erl = 1; 3356376Sgblack@eecs.umich.edu // Enable BEV bit on a reset 3366376Sgblack@eecs.umich.edu status.bev = 1; 3376334Sgblack@eecs.umich.edu 3386383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_STATUS, status); 3396334Sgblack@eecs.umich.edu // Now, create Write Mask for the Status register 3406334Sgblack@eecs.umich.edu MiscReg stat_Mask = 0xFF78FF17; 3416376Sgblack@eecs.umich.edu replaceBits(stat_Mask, 0, 32, 0); 3426383Sgblack@eecs.umich.edu setRegMask(MISCREG_STATUS, stat_Mask); 3436334Sgblack@eecs.umich.edu 3446334Sgblack@eecs.umich.edu 3456334Sgblack@eecs.umich.edu // MVPConf0 3466383Sgblack@eecs.umich.edu MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0); 3476376Sgblack@eecs.umich.edu mvpConf0.tca = 1; 3488181Sksewell@umich.edu mvpConf0.pvpe = numVpes - 1; 3498181Sksewell@umich.edu mvpConf0.ptc = numThreads - 1; 3506383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0); 3516334Sgblack@eecs.umich.edu 3526334Sgblack@eecs.umich.edu // VPEConf0 3536383Sgblack@eecs.umich.edu VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0); 3546376Sgblack@eecs.umich.edu vpeConf0.mvp = 1; 3556383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0); 3566334Sgblack@eecs.umich.edu 3576334Sgblack@eecs.umich.edu // TCBind 3588181Sksewell@umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 3596383Sgblack@eecs.umich.edu TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid); 3606376Sgblack@eecs.umich.edu tcBind.curTC = tid; 3616383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid); 3626334Sgblack@eecs.umich.edu } 3636334Sgblack@eecs.umich.edu // TCHalt 3646383Sgblack@eecs.umich.edu TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT); 3656376Sgblack@eecs.umich.edu tcHalt.h = 0; 3666383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt); 3676334Sgblack@eecs.umich.edu 3686334Sgblack@eecs.umich.edu // TCStatus 3696334Sgblack@eecs.umich.edu // Set TCStatus Activated to 1 for the initial thread that is running 3706383Sgblack@eecs.umich.edu TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS); 3716376Sgblack@eecs.umich.edu tcStatus.a = 1; 3726383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus); 3736334Sgblack@eecs.umich.edu 3746334Sgblack@eecs.umich.edu // Set Dynamically Allocatable bit to 1 for all other threads 3758181Sksewell@umich.edu for (ThreadID tid = 1; tid < numThreads; tid++) { 3766383Sgblack@eecs.umich.edu tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid); 3776376Sgblack@eecs.umich.edu tcStatus.da = 1; 3786383Sgblack@eecs.umich.edu setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid); 3796334Sgblack@eecs.umich.edu } 3806334Sgblack@eecs.umich.edu 3816334Sgblack@eecs.umich.edu 3826383Sgblack@eecs.umich.edu MiscReg mask = 0x7FFFFFFF; 3836334Sgblack@eecs.umich.edu 3846334Sgblack@eecs.umich.edu // Now, create Write Mask for the Index register 3856383Sgblack@eecs.umich.edu replaceBits(mask, 0, 32, 0); 3866383Sgblack@eecs.umich.edu setRegMask(MISCREG_INDEX, mask); 3876334Sgblack@eecs.umich.edu 3886383Sgblack@eecs.umich.edu mask = 0x3FFFFFFF; 3896383Sgblack@eecs.umich.edu replaceBits(mask, 0, 32, 0); 3906383Sgblack@eecs.umich.edu setRegMask(MISCREG_ENTRYLO0, mask); 3916383Sgblack@eecs.umich.edu setRegMask(MISCREG_ENTRYLO1, mask); 3926334Sgblack@eecs.umich.edu 3936383Sgblack@eecs.umich.edu mask = 0xFF800000; 3946383Sgblack@eecs.umich.edu replaceBits(mask, 0, 32, 0); 3956383Sgblack@eecs.umich.edu setRegMask(MISCREG_CONTEXT, mask); 3966334Sgblack@eecs.umich.edu 3976383Sgblack@eecs.umich.edu mask = 0x1FFFF800; 3986383Sgblack@eecs.umich.edu replaceBits(mask, 0, 32, 0); 3996383Sgblack@eecs.umich.edu setRegMask(MISCREG_PAGEMASK, mask); 4006334Sgblack@eecs.umich.edu 4016383Sgblack@eecs.umich.edu mask = 0x0; 4026383Sgblack@eecs.umich.edu replaceBits(mask, 0, 32, 0); 4036383Sgblack@eecs.umich.edu setRegMask(MISCREG_BADVADDR, mask); 4046383Sgblack@eecs.umich.edu setRegMask(MISCREG_LLADDR, mask); 4056334Sgblack@eecs.umich.edu 4066383Sgblack@eecs.umich.edu mask = 0x08C00300; 4076383Sgblack@eecs.umich.edu replaceBits(mask, 0, 32, 0); 4086383Sgblack@eecs.umich.edu setRegMask(MISCREG_CAUSE, mask); 4096334Sgblack@eecs.umich.edu 4106334Sgblack@eecs.umich.edu} 4116334Sgblack@eecs.umich.edu 4126334Sgblack@eecs.umich.eduinline unsigned 41310698Sandreas.hansson@arm.comISA::getVPENum(ThreadID tid) const 4146334Sgblack@eecs.umich.edu{ 4156383Sgblack@eecs.umich.edu TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid]; 4166376Sgblack@eecs.umich.edu return tcBind.curVPE; 4176313Sgblack@eecs.umich.edu} 4186313Sgblack@eecs.umich.edu 4196313Sgblack@eecs.umich.eduMiscReg 42010698Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const 4216313Sgblack@eecs.umich.edu{ 4226334Sgblack@eecs.umich.edu unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 4236334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4246334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n", 4256334Sgblack@eecs.umich.edu misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], 4266334Sgblack@eecs.umich.edu miscRegFile[misc_reg][reg_sel]); 4276334Sgblack@eecs.umich.edu return miscRegFile[misc_reg][reg_sel]; 4286313Sgblack@eecs.umich.edu} 4296313Sgblack@eecs.umich.edu 4306334Sgblack@eecs.umich.edu//@TODO: MIPS MT's register view automatically connects 4316334Sgblack@eecs.umich.edu// Status to TCStatus depending on current thread 4326334Sgblack@eecs.umich.edu//template <class TC> 4336313Sgblack@eecs.umich.eduMiscReg 4346383Sgblack@eecs.umich.eduISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) 4356313Sgblack@eecs.umich.edu{ 4366334Sgblack@eecs.umich.edu unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 4376334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4386334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 4396334Sgblack@eecs.umich.edu "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n", 4406334Sgblack@eecs.umich.edu misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], 4416334Sgblack@eecs.umich.edu miscRegFile[misc_reg][reg_sel]); 4426334Sgblack@eecs.umich.edu 4436378Sgblack@eecs.umich.edu return miscRegFile[misc_reg][reg_sel]; 4446313Sgblack@eecs.umich.edu} 4456313Sgblack@eecs.umich.edu 4466313Sgblack@eecs.umich.eduvoid 4476383Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) 4486313Sgblack@eecs.umich.edu{ 4496334Sgblack@eecs.umich.edu unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 4506334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4516334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 4526334Sgblack@eecs.umich.edu "[tid:%i]: Setting (direct set) CP0 Register:%u " 4536334Sgblack@eecs.umich.edu "Select:%u (%s) to %#x.\n", 4546334Sgblack@eecs.umich.edu tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 4556334Sgblack@eecs.umich.edu 4566334Sgblack@eecs.umich.edu miscRegFile[misc_reg][reg_sel] = val; 4576313Sgblack@eecs.umich.edu} 4586313Sgblack@eecs.umich.edu 4596313Sgblack@eecs.umich.eduvoid 4606383Sgblack@eecs.umich.eduISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid) 4616313Sgblack@eecs.umich.edu{ 4626334Sgblack@eecs.umich.edu unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 4636334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4646334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 4656334Sgblack@eecs.umich.edu "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n", 4666334Sgblack@eecs.umich.edu tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 4676334Sgblack@eecs.umich.edu miscRegFile_WriteMask[misc_reg][reg_sel] = val; 4686334Sgblack@eecs.umich.edu} 4696334Sgblack@eecs.umich.edu 4706334Sgblack@eecs.umich.edu// PROGRAMMER'S NOTES: 4716334Sgblack@eecs.umich.edu// (1) Some CP0 Registers have fields that cannot 4726334Sgblack@eecs.umich.edu// be overwritten. Make sure to handle those particular registers 4736334Sgblack@eecs.umich.edu// with care! 4746334Sgblack@eecs.umich.eduvoid 4756383Sgblack@eecs.umich.eduISA::setMiscReg(int misc_reg, const MiscReg &val, 4766334Sgblack@eecs.umich.edu ThreadContext *tc, ThreadID tid) 4776334Sgblack@eecs.umich.edu{ 4786334Sgblack@eecs.umich.edu int reg_sel = (bankType[misc_reg] == perThreadContext) 4796334Sgblack@eecs.umich.edu ? tid : getVPENum(tid); 4806334Sgblack@eecs.umich.edu 4816334Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 4826334Sgblack@eecs.umich.edu "[tid:%i]: Setting CP0 Register:%u " 4836334Sgblack@eecs.umich.edu "Select:%u (%s) to %#x, with effect.\n", 4846334Sgblack@eecs.umich.edu tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 4856334Sgblack@eecs.umich.edu 4866334Sgblack@eecs.umich.edu MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val); 4876334Sgblack@eecs.umich.edu 4886334Sgblack@eecs.umich.edu miscRegFile[misc_reg][reg_sel] = cp0_val; 4896334Sgblack@eecs.umich.edu 4909180Sandreas.hansson@arm.com scheduleCP0Update(tc->getCpuPtr(), Cycles(1)); 4916334Sgblack@eecs.umich.edu} 4926334Sgblack@eecs.umich.edu 4936334Sgblack@eecs.umich.edu/** 4946334Sgblack@eecs.umich.edu * This method doesn't need to adjust the Control Register Offset 4956334Sgblack@eecs.umich.edu * since it has already been done in the calling method 4966334Sgblack@eecs.umich.edu * (setRegWithEffect) 4976334Sgblack@eecs.umich.edu*/ 4986334Sgblack@eecs.umich.eduMiscReg 4996334Sgblack@eecs.umich.eduISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) 5006334Sgblack@eecs.umich.edu{ 5016378Sgblack@eecs.umich.edu MiscReg retVal = val; 5026334Sgblack@eecs.umich.edu 5036378Sgblack@eecs.umich.edu // Mask off read-only regions 5046378Sgblack@eecs.umich.edu retVal &= miscRegFile_WriteMask[misc_reg][reg_sel]; 5056378Sgblack@eecs.umich.edu MiscReg curVal = miscRegFile[misc_reg][reg_sel]; 5066378Sgblack@eecs.umich.edu // Mask off current alue with inverse mask (clear writeable bits) 5076378Sgblack@eecs.umich.edu curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]); 5086378Sgblack@eecs.umich.edu retVal |= curVal; // Combine the two 5096378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, 5106378Sgblack@eecs.umich.edu "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, " 5116378Sgblack@eecs.umich.edu "current val: %lx, written val: %x\n", 5126378Sgblack@eecs.umich.edu miscRegFile_WriteMask[misc_reg][reg_sel], 5136378Sgblack@eecs.umich.edu ~miscRegFile_WriteMask[misc_reg][reg_sel], 5146378Sgblack@eecs.umich.edu val, miscRegFile[misc_reg][reg_sel], retVal); 5156378Sgblack@eecs.umich.edu return retVal; 5166313Sgblack@eecs.umich.edu} 5176313Sgblack@eecs.umich.edu 5186313Sgblack@eecs.umich.eduvoid 5199180Sandreas.hansson@arm.comISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay) 5206313Sgblack@eecs.umich.edu{ 5216334Sgblack@eecs.umich.edu if (!cp0Updated) { 5226334Sgblack@eecs.umich.edu cp0Updated = true; 5236334Sgblack@eecs.umich.edu 5246334Sgblack@eecs.umich.edu //schedule UPDATE 5256334Sgblack@eecs.umich.edu CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0); 5269180Sandreas.hansson@arm.com cpu->schedule(cp0_event, cpu->clockEdge(delay)); 5276334Sgblack@eecs.umich.edu } 5286313Sgblack@eecs.umich.edu} 5296313Sgblack@eecs.umich.edu 5306313Sgblack@eecs.umich.eduvoid 5316806Sgblack@eecs.umich.eduISA::updateCPU(BaseCPU *cpu) 5326313Sgblack@eecs.umich.edu{ 5336334Sgblack@eecs.umich.edu /////////////////////////////////////////////////////////////////// 5346334Sgblack@eecs.umich.edu // 5356334Sgblack@eecs.umich.edu // EVALUATE CP0 STATE FOR MIPS MT 5366334Sgblack@eecs.umich.edu // 5376334Sgblack@eecs.umich.edu /////////////////////////////////////////////////////////////////// 5386383Sgblack@eecs.umich.edu MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0); 5396376Sgblack@eecs.umich.edu ThreadID num_threads = mvpConf0.ptc + 1; 5406334Sgblack@eecs.umich.edu 5416334Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < num_threads; tid++) { 5426383Sgblack@eecs.umich.edu TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid); 5436383Sgblack@eecs.umich.edu TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid); 5446334Sgblack@eecs.umich.edu 5456334Sgblack@eecs.umich.edu //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs 5466376Sgblack@eecs.umich.edu if (tcHalt.h == 1 || tcStatus.a == 0) { 5476334Sgblack@eecs.umich.edu haltThread(cpu->getContext(tid)); 5486376Sgblack@eecs.umich.edu } else if (tcHalt.h == 0 && tcStatus.a == 1) { 5496334Sgblack@eecs.umich.edu restoreThread(cpu->getContext(tid)); 5506334Sgblack@eecs.umich.edu } 5516334Sgblack@eecs.umich.edu } 5526334Sgblack@eecs.umich.edu 5536376Sgblack@eecs.umich.edu num_threads = mvpConf0.ptc + 1; 5546334Sgblack@eecs.umich.edu 5556334Sgblack@eecs.umich.edu // Toggle update flag after we finished updating 5566334Sgblack@eecs.umich.edu cp0Updated = false; 5576334Sgblack@eecs.umich.edu} 5586334Sgblack@eecs.umich.edu 5596334Sgblack@eecs.umich.eduISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type) 5606334Sgblack@eecs.umich.edu : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type) 5616334Sgblack@eecs.umich.edu{ } 5626334Sgblack@eecs.umich.edu 5636334Sgblack@eecs.umich.eduvoid 5646334Sgblack@eecs.umich.eduISA::CP0Event::process() 5656334Sgblack@eecs.umich.edu{ 5666334Sgblack@eecs.umich.edu switch (cp0EventType) 5676334Sgblack@eecs.umich.edu { 5686334Sgblack@eecs.umich.edu case UpdateCP0: 5696806Sgblack@eecs.umich.edu cp0->updateCPU(cpu); 5706334Sgblack@eecs.umich.edu break; 5716334Sgblack@eecs.umich.edu } 5726334Sgblack@eecs.umich.edu} 5736334Sgblack@eecs.umich.edu 5746334Sgblack@eecs.umich.educonst char * 5756334Sgblack@eecs.umich.eduISA::CP0Event::description() const 5766334Sgblack@eecs.umich.edu{ 5776334Sgblack@eecs.umich.edu return "Coprocessor-0 event"; 5786334Sgblack@eecs.umich.edu} 5796334Sgblack@eecs.umich.edu 5806334Sgblack@eecs.umich.eduvoid 5819180Sandreas.hansson@arm.comISA::CP0Event::scheduleEvent(Cycles delay) 5826334Sgblack@eecs.umich.edu{ 5839180Sandreas.hansson@arm.com cpu->reschedule(this, cpu->clockEdge(delay), true); 5846334Sgblack@eecs.umich.edu} 5856334Sgblack@eecs.umich.edu 5866334Sgblack@eecs.umich.eduvoid 5876334Sgblack@eecs.umich.eduISA::CP0Event::unscheduleEvent() 5886334Sgblack@eecs.umich.edu{ 5896334Sgblack@eecs.umich.edu if (scheduled()) 5906334Sgblack@eecs.umich.edu squash(); 5916313Sgblack@eecs.umich.edu} 5926313Sgblack@eecs.umich.edu 5936313Sgblack@eecs.umich.edu} 5949384SAndreas.Sandberg@arm.com 5959384SAndreas.Sandberg@arm.comMipsISA::ISA * 5969384SAndreas.Sandberg@arm.comMipsISAParams::create() 5979384SAndreas.Sandberg@arm.com{ 5989384SAndreas.Sandberg@arm.com return new MipsISA::ISA(this); 5999384SAndreas.Sandberg@arm.com} 600