interrupts.hh revision 6378
1/* 2 * Copyright (c) 2007 MIPS Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Rick Strong 29 */ 30 31#ifndef __ARCH_MIPS_INTERRUPT_HH__ 32#define __ARCH_MIPS_INTERRUPT_HH__ 33 34#include "arch/mips/faults.hh" 35#include "base/compiler.hh" 36 37namespace MipsISA 38{ 39 40class Interrupts 41{ 42 public: 43 Interrupts() 44 { 45 newInfoSet = false; 46 } 47 48 // post(int int_num, int index) is responsible 49 // for posting an interrupt. It sets a bit 50 // in intstatus corresponding to Cause IP*. The 51 // MIPS register Cause is updated by updateIntrInfo 52 // which is called by checkInterrupts 53 // 54 void post(int int_num, ThreadContext *tc); 55 void post(int int_num, int index); 56 57 // clear(int int_num, int index) is responsible 58 // for clearing an interrupt. It clear a bit 59 // in intstatus corresponding to Cause IP*. The 60 // MIPS register Cause is updated by updateIntrInfo 61 // which is called by checkInterrupts 62 // 63 void clear(int int_num, ThreadContext* tc); 64 void clear(int int_num, int index); 65 66 // clearAll() is responsible 67 // for clearing all interrupts. It clears all bits 68 // in intstatus corresponding to Cause IP*. The 69 // MIPS register Cause is updated by updateIntrInfo 70 // which is called by checkInterrupts 71 // 72 void clearAll(ThreadContext *tc); 73 void clearAll(); 74 75 // getInterrupt(ThreadContext * tc) checks if an interrupt 76 // should be returned. It ands the interrupt mask and 77 // and interrupt pending bits to see if one exists. It 78 // also makes sure interrupts are enabled (IE) and 79 // that ERL and ERX are not set 80 // 81 Fault getInterrupt(ThreadContext *tc); 82 83 // updateIntrInfo(ThreadContext *tc) const syncs the 84 // MIPS cause register with the instatus variable. instatus 85 // is essentially a copy of the MIPS cause[IP7:IP0] 86 // 87 void updateIntrInfo(ThreadContext *tc) const; 88 bool interruptsPending(ThreadContext *tc) const; 89 bool onCpuTimerInterrupt(ThreadContext *tc) const; 90 91 bool 92 checkInterrupts(ThreadContext *tc) const 93 { 94 return interruptsPending(tc); 95 } 96 97 98 void 99 serialize(std::ostream &os) 100 { 101 fatal("Serialization of Interrupts Unimplemented for MIPS"); 102 } 103 104 void 105 unserialize(Checkpoint *cp, const std::string §ion) 106 { 107 fatal("Unserialization of Interrupts Unimplemented for MIPS"); 108 } 109 110 private: 111 bool newInfoSet; 112 int newIpl; 113 int newSummary; 114}; 115 116} 117 118#endif 119 120