interrupts.hh revision 5704:98224505352a
12023SN/A/* 22023SN/A * Copyright (c) 2007 MIPS Technologies, Inc. 32023SN/A * All rights reserved. 42023SN/A * 52023SN/A * Redistribution and use in source and binary forms, with or without 62023SN/A * modification, are permitted provided that the following conditions are 72023SN/A * met: redistributions of source code must retain the above copyright 82023SN/A * notice, this list of conditions and the following disclaimer; 92023SN/A * redistributions in binary form must reproduce the above copyright 102023SN/A * notice, this list of conditions and the following disclaimer in the 112023SN/A * documentation and/or other materials provided with the distribution; 122023SN/A * neither the name of the copyright holders nor the names of its 132023SN/A * contributors may be used to endorse or promote products derived from 142023SN/A * this software without specific prior written permission. 152023SN/A * 162023SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172023SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182023SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192023SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202023SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212023SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222023SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232023SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242023SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252023SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262023SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272023SN/A * 282665Ssaidi@eecs.umich.edu * Authors: Rick Strong 292665Ssaidi@eecs.umich.edu */ 302665Ssaidi@eecs.umich.edu 312023SN/A#ifndef __ARCH_MIPS_INTERRUPT_HH__ 324202Sbinkertn@umich.edu#define __ARCH_MIPS_INTERRUPT_HH__ 332023SN/A 344202Sbinkertn@umich.edu 354997Sgblack@eecs.umich.edu#include "arch/mips/faults.hh" 364202Sbinkertn@umich.edu#include "base/compiler.hh" 374997Sgblack@eecs.umich.edu 386313Sgblack@eecs.umich.edu 394202Sbinkertn@umich.edu 404997Sgblack@eecs.umich.edunamespace MipsISA 414202Sbinkertn@umich.edu{ 426327Sgblack@eecs.umich.educlass Interrupts 434202Sbinkertn@umich.edu{ 444997Sgblack@eecs.umich.edu /* 454826Ssaidi@eecs.umich.edu protected: 462023SN/A uint8_t intstatus; 474997Sgblack@eecs.umich.edu bool oncputimerintr; 484997Sgblack@eecs.umich.edu public: 494202Sbinkertn@umich.edu Interrupts() 505647Sgblack@eecs.umich.edu { 514486Sbinkertn@umich.edu intstatus = 0; 524486Sbinkertn@umich.edu newInfoSet = false; 534202Sbinkertn@umich.edu oncputimerintr = false; 545647Sgblack@eecs.umich.edu 554202Sbinkertn@umich.edu } 564202Sbinkertn@umich.edu // post(int int_num, int index) is responsible 574202Sbinkertn@umich.edu // for posting an interrupt. It sets a bit 584202Sbinkertn@umich.edu // in intstatus corresponding to Cause IP*. The 594202Sbinkertn@umich.edu // MIPS register Cause is updated by updateIntrInfo 602023SN/A // which is called by checkInterrupts 614202Sbinkertn@umich.edu // 624202Sbinkertn@umich.edu void post(int int_num, int index); 634202Sbinkertn@umich.edu // clear(int int_num, int index) is responsible 642023SN/A // for clearing an interrupt. It clear a bit 654202Sbinkertn@umich.edu // in intstatus corresponding to Cause IP*. The 664202Sbinkertn@umich.edu // MIPS register Cause is updated by updateIntrInfo 672023SN/A // which is called by checkInterrupts 684202Sbinkertn@umich.edu // 694202Sbinkertn@umich.edu void clear(int int_num, int index); 702023SN/A // clearAll() is responsible 714202Sbinkertn@umich.edu // for clearing all interrupts. It clears all bits 724202Sbinkertn@umich.edu // in intstatus corresponding to Cause IP*. The 732023SN/A // MIPS register Cause is updated by updateIntrInfo 744202Sbinkertn@umich.edu // which is called by checkInterrupts 754202Sbinkertn@umich.edu // 764202Sbinkertn@umich.edu void clearAll(); 774202Sbinkertn@umich.edu 784202Sbinkertn@umich.edu // getInterrupt(ThreadContext * tc) checks if an interrupt 794202Sbinkertn@umich.edu // should be returned. It ands the interrupt mask and 80 // and interrupt pending bits to see if one exists. It 81 // also makes sure interrupts are enabled (IE) and 82 // that ERL and ERX are not set 83 // 84 Fault getInterrupt(ThreadContext * tc); 85 86 // updateIntrInfo(ThreadContext *tc) const syncs the 87 // MIPS cause register with the instatus variable. instatus 88 // is essentially a copy of the MIPS cause[IP7:IP0] 89 // 90 void updateIntrInfo(ThreadContext *tc) const; 91 void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const; 92 bool onCpuTimerInterrupt(ThreadContext *tc) const; 93 94 bool checkInterrupts(ThreadContext *tc) const { 95 //return (intstatus != 0) && !(tc->readPC() & 0x3); 96 if (oncputimerintr == false){ 97 updateIntrInfo(tc); 98 return ((intstatus != 0) || onCpuTimerInterrupt(tc)); 99 } 100 else 101 return true; 102 103 } 104 */ 105 106 107 protected: 108 //uint8_t intstatus; 109 //bool oncputimerintr; 110 public: 111 Interrupts() 112 { 113 //intstatus = 0; 114 newInfoSet = false; 115 //oncputimerintr = false; 116 117 } 118 // post(int int_num, int index) is responsible 119 // for posting an interrupt. It sets a bit 120 // in intstatus corresponding to Cause IP*. The 121 // MIPS register Cause is updated by updateIntrInfo 122 // which is called by checkInterrupts 123 // 124 void post(int int_num, ThreadContext* tc); 125 void post(int int_num, int index); 126 127 // clear(int int_num, int index) is responsible 128 // for clearing an interrupt. It clear a bit 129 // in intstatus corresponding to Cause IP*. The 130 // MIPS register Cause is updated by updateIntrInfo 131 // which is called by checkInterrupts 132 // 133 void clear(int int_num, ThreadContext* tc); 134 void clear(int int_num, int index); 135 136 // clearAll() is responsible 137 // for clearing all interrupts. It clears all bits 138 // in intstatus corresponding to Cause IP*. The 139 // MIPS register Cause is updated by updateIntrInfo 140 // which is called by checkInterrupts 141 // 142 void clearAll(ThreadContext* tc); 143 void clearAll(); 144 145 // getInterrupt(ThreadContext * tc) checks if an interrupt 146 // should be returned. It ands the interrupt mask and 147 // and interrupt pending bits to see if one exists. It 148 // also makes sure interrupts are enabled (IE) and 149 // that ERL and ERX are not set 150 // 151 Fault getInterrupt(ThreadContext * tc); 152 153 // updateIntrInfo(ThreadContext *tc) const syncs the 154 // MIPS cause register with the instatus variable. instatus 155 // is essentially a copy of the MIPS cause[IP7:IP0] 156 // 157 void updateIntrInfo(ThreadContext *tc) const; 158 bool interruptsPending(ThreadContext *tc) const; 159 bool onCpuTimerInterrupt(ThreadContext *tc) const; 160 161 bool 162 checkInterrupts(ThreadContext *tc) const 163 { 164 return interruptsPending(tc); 165 } 166 167 168 void serialize(std::ostream &os) 169 { 170 fatal("Serialization of Interrupts Unimplemented for MIPS"); 171 //SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 172 //SERIALIZE_SCALAR(intstatus); 173 } 174 175 void unserialize(Checkpoint *cp, const std::string §ion) 176 { 177 fatal("Unserialization of Interrupts Unimplemented for MIPS"); 178 //UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); 179 //UNSERIALIZE_SCALAR(intstatus); 180 } 181 182 183 184 private: 185 bool newInfoSet; 186 int newIpl; 187 int newSummary; 188 189}; 190 191} 192 193#endif 194 195