interrupts.hh revision 6379
12SN/A/* 21762SN/A * Copyright (c) 2007 MIPS Technologies, Inc. 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 284762Snate@binkert.org * Authors: Rick Strong 292SN/A */ 302SN/A 312410SN/A#ifndef __ARCH_MIPS_INTERRUPT_HH__ 322410SN/A#define __ARCH_MIPS_INTERRUPT_HH__ 332SN/A 344762Snate@binkert.org#include <string> 354762Snate@binkert.org 364762Snate@binkert.org#include "arch/mips/faults.hh" 374762Snate@binkert.org#include "base/compiler.hh" 384762Snate@binkert.org#include "base/misc.hh" 392SN/A#include "params/MipsInterrupts.hh" 404762Snate@binkert.org#include "sim/serialize.hh" 414762Snate@binkert.org#include "sim/sim_object.hh" 424762Snate@binkert.org 432SN/Aclass BaseCPU; 444762Snate@binkert.orgclass Checkpoint; 454762Snate@binkert.org 464762Snate@binkert.orgnamespace MipsISA 474762Snate@binkert.org{ 484762Snate@binkert.org 494762Snate@binkert.orgclass Interrupts : public SimObject 504762Snate@binkert.org{ 514762Snate@binkert.org public: 524762Snate@binkert.org typedef MipsInterruptsParams Params; 534762Snate@binkert.org 544762Snate@binkert.org const Params * 554762Snate@binkert.org params() const 564762Snate@binkert.org { 574762Snate@binkert.org return dynamic_cast<const Params *>(_params); 582SN/A } 592410SN/A 60 Interrupts(Params * p) : SimObject(p) 61 { 62 newInfoSet = false; 63 } 64 65 void 66 setCPU(BaseCPU *_cpu) 67 {} 68 69 // post(int int_num, int index) is responsible 70 // for posting an interrupt. It sets a bit 71 // in intstatus corresponding to Cause IP*. The 72 // MIPS register Cause is updated by updateIntrInfo 73 // which is called by checkInterrupts 74 // 75 void post(int int_num, ThreadContext *tc); 76 void post(int int_num, int index); 77 78 // clear(int int_num, int index) is responsible 79 // for clearing an interrupt. It clear a bit 80 // in intstatus corresponding to Cause IP*. The 81 // MIPS register Cause is updated by updateIntrInfo 82 // which is called by checkInterrupts 83 // 84 void clear(int int_num, ThreadContext* tc); 85 void clear(int int_num, int index); 86 87 // clearAll() is responsible 88 // for clearing all interrupts. It clears all bits 89 // in intstatus corresponding to Cause IP*. The 90 // MIPS register Cause is updated by updateIntrInfo 91 // which is called by checkInterrupts 92 // 93 void clearAll(ThreadContext *tc); 94 void clearAll(); 95 96 // getInterrupt(ThreadContext * tc) checks if an interrupt 97 // should be returned. It ands the interrupt mask and 98 // and interrupt pending bits to see if one exists. It 99 // also makes sure interrupts are enabled (IE) and 100 // that ERL and ERX are not set 101 // 102 Fault getInterrupt(ThreadContext *tc); 103 104 // updateIntrInfo(ThreadContext *tc) const syncs the 105 // MIPS cause register with the instatus variable. instatus 106 // is essentially a copy of the MIPS cause[IP7:IP0] 107 // 108 void updateIntrInfo(ThreadContext *tc) const; 109 bool interruptsPending(ThreadContext *tc) const; 110 bool onCpuTimerInterrupt(ThreadContext *tc) const; 111 112 bool 113 checkInterrupts(ThreadContext *tc) const 114 { 115 return interruptsPending(tc); 116 } 117 118 119 void 120 serialize(std::ostream &os) 121 { 122 fatal("Serialization of Interrupts Unimplemented for MIPS"); 123 } 124 125 void 126 unserialize(Checkpoint *cp, const std::string §ion) 127 { 128 fatal("Unserialization of Interrupts Unimplemented for MIPS"); 129 } 130 131 private: 132 bool newInfoSet; 133 int newIpl; 134 int newSummary; 135}; 136 137} 138 139#endif 140 141