interrupts.hh revision 5222
15222Sksewell@umich.edu/* 25222Sksewell@umich.edu * Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved 35222Sksewell@umich.edu * 45222Sksewell@umich.edu * This software is part of the M5 simulator. 55222Sksewell@umich.edu * 65222Sksewell@umich.edu * THIS IS A LEGAL AGREEMENT. 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($(B!H(BMIPS$(B!I(B) is not used in any 185222Sksewell@umich.edu * advertising or publicity pertaining to the use or distribution of 195222Sksewell@umich.edu * this software without specific, written prior authorization. 205222Sksewell@umich.edu * 215222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND 225222Sksewell@umich.edu * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 235222Sksewell@umich.edu * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 245222Sksewell@umich.edu * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 255222Sksewell@umich.edu * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 265222Sksewell@umich.edu * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 275222Sksewell@umich.edu * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 285222Sksewell@umich.edu * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 295222Sksewell@umich.edu * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 305222Sksewell@umich.edu * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 315222Sksewell@umich.edu * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 325222Sksewell@umich.edu * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 335222Sksewell@umich.edu * 345222Sksewell@umich.edu * Authors: Richard Strong 355222Sksewell@umich.edu */ 365222Sksewell@umich.edu 375222Sksewell@umich.edu#ifndef __ARCH_MIPS_INTERRUPT_HH__ 385222Sksewell@umich.edu#define __ARCH_MIPS_INTERRUPT_HH__ 395222Sksewell@umich.edu 405222Sksewell@umich.edu 415222Sksewell@umich.edu#include "arch/mips/faults.hh" 425222Sksewell@umich.edu#include "base/compiler.hh" 435222Sksewell@umich.edu 445222Sksewell@umich.edu 455222Sksewell@umich.edu 465222Sksewell@umich.edunamespace MipsISA 475222Sksewell@umich.edu{ 485222Sksewell@umich.educlass Interrupts 495222Sksewell@umich.edu{ 505222Sksewell@umich.edu /* 515222Sksewell@umich.edu protected: 525222Sksewell@umich.edu uint8_t intstatus; 535222Sksewell@umich.edu bool oncputimerintr; 545222Sksewell@umich.edu public: 555222Sksewell@umich.edu Interrupts() 565222Sksewell@umich.edu { 575222Sksewell@umich.edu intstatus = 0; 585222Sksewell@umich.edu newInfoSet = false; 595222Sksewell@umich.edu oncputimerintr = false; 605222Sksewell@umich.edu 615222Sksewell@umich.edu } 625222Sksewell@umich.edu // post(int int_num, int index) is responsible 635222Sksewell@umich.edu // for posting an interrupt. It sets a bit 645222Sksewell@umich.edu // in intstatus corresponding to Cause IP*. The 655222Sksewell@umich.edu // MIPS register Cause is updated by updateIntrInfo 665222Sksewell@umich.edu // which is called by check_interrupts 675222Sksewell@umich.edu // 685222Sksewell@umich.edu void post(int int_num, int index); 695222Sksewell@umich.edu // clear(int int_num, int index) is responsible 705222Sksewell@umich.edu // for clearing an interrupt. It clear a bit 715222Sksewell@umich.edu // in intstatus corresponding to Cause IP*. The 725222Sksewell@umich.edu // MIPS register Cause is updated by updateIntrInfo 735222Sksewell@umich.edu // which is called by check_interrupts 745222Sksewell@umich.edu // 755222Sksewell@umich.edu void clear(int int_num, int index); 765222Sksewell@umich.edu // clear_all() is responsible 775222Sksewell@umich.edu // for clearing all interrupts. It clears all bits 785222Sksewell@umich.edu // in intstatus corresponding to Cause IP*. The 795222Sksewell@umich.edu // MIPS register Cause is updated by updateIntrInfo 805222Sksewell@umich.edu // which is called by check_interrupts 815222Sksewell@umich.edu // 825222Sksewell@umich.edu void clear_all(); 835222Sksewell@umich.edu 845222Sksewell@umich.edu // getInterrupt(ThreadContext * tc) checks if an interrupt 855222Sksewell@umich.edu // should be returned. It ands the interrupt mask and 865222Sksewell@umich.edu // and interrupt pending bits to see if one exists. It 875222Sksewell@umich.edu // also makes sure interrupts are enabled (IE) and 885222Sksewell@umich.edu // that ERL and ERX are not set 895222Sksewell@umich.edu // 905222Sksewell@umich.edu Fault getInterrupt(ThreadContext * tc); 915222Sksewell@umich.edu 925222Sksewell@umich.edu // updateIntrInfo(ThreadContext *tc) const syncs the 935222Sksewell@umich.edu // MIPS cause register with the instatus variable. instatus 945222Sksewell@umich.edu // is essentially a copy of the MIPS cause[IP7:IP0] 955222Sksewell@umich.edu // 965222Sksewell@umich.edu void updateIntrInfo(ThreadContext *tc) const; 975222Sksewell@umich.edu void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const; 985222Sksewell@umich.edu bool onCpuTimerInterrupt(ThreadContext *tc) const; 995222Sksewell@umich.edu 1005222Sksewell@umich.edu uint64_t get_vec(int int_num); 1015222Sksewell@umich.edu 1025222Sksewell@umich.edu bool check_interrupts(ThreadContext * tc) const{ 1035222Sksewell@umich.edu //return (intstatus != 0) && !(tc->readPC() & 0x3); 1045222Sksewell@umich.edu if (oncputimerintr == false){ 1055222Sksewell@umich.edu updateIntrInfo(tc); 1065222Sksewell@umich.edu return ((intstatus != 0) || onCpuTimerInterrupt(tc)); 1075222Sksewell@umich.edu } 1085222Sksewell@umich.edu else 1095222Sksewell@umich.edu return true; 1105222Sksewell@umich.edu 1115222Sksewell@umich.edu } 1125222Sksewell@umich.edu */ 1135222Sksewell@umich.edu 1145222Sksewell@umich.edu 1155222Sksewell@umich.edu protected: 1165222Sksewell@umich.edu //uint8_t intstatus; 1175222Sksewell@umich.edu //bool oncputimerintr; 1185222Sksewell@umich.edu public: 1195222Sksewell@umich.edu Interrupts() 1205222Sksewell@umich.edu { 1215222Sksewell@umich.edu //intstatus = 0; 1225222Sksewell@umich.edu newInfoSet = false; 1235222Sksewell@umich.edu //oncputimerintr = false; 1245222Sksewell@umich.edu 1255222Sksewell@umich.edu } 1265222Sksewell@umich.edu // post(int int_num, int index) is responsible 1275222Sksewell@umich.edu // for posting an interrupt. It sets a bit 1285222Sksewell@umich.edu // in intstatus corresponding to Cause IP*. The 1295222Sksewell@umich.edu // MIPS register Cause is updated by updateIntrInfo 1305222Sksewell@umich.edu // which is called by check_interrupts 1315222Sksewell@umich.edu // 1325222Sksewell@umich.edu void post(int int_num, ThreadContext* tc); 1335222Sksewell@umich.edu void post(int int_num, int index); 1345222Sksewell@umich.edu 1355222Sksewell@umich.edu // clear(int int_num, int index) is responsible 1365222Sksewell@umich.edu // for clearing an interrupt. It clear a bit 1375222Sksewell@umich.edu // in intstatus corresponding to Cause IP*. The 1385222Sksewell@umich.edu // MIPS register Cause is updated by updateIntrInfo 1395222Sksewell@umich.edu // which is called by check_interrupts 1405222Sksewell@umich.edu // 1415222Sksewell@umich.edu void clear(int int_num, ThreadContext* tc); 1425222Sksewell@umich.edu void clear(int int_num, int index); 1435222Sksewell@umich.edu 1445222Sksewell@umich.edu // clear_all() is responsible 1455222Sksewell@umich.edu // for clearing all interrupts. It clears all bits 1465222Sksewell@umich.edu // in intstatus corresponding to Cause IP*. The 1475222Sksewell@umich.edu // MIPS register Cause is updated by updateIntrInfo 1485222Sksewell@umich.edu // which is called by check_interrupts 1495222Sksewell@umich.edu // 1505222Sksewell@umich.edu void clear_all(ThreadContext* tc); 1515222Sksewell@umich.edu void clear_all(); 1525222Sksewell@umich.edu 1535222Sksewell@umich.edu // getInterrupt(ThreadContext * tc) checks if an interrupt 1545222Sksewell@umich.edu // should be returned. It ands the interrupt mask and 1555222Sksewell@umich.edu // and interrupt pending bits to see if one exists. It 1565222Sksewell@umich.edu // also makes sure interrupts are enabled (IE) and 1575222Sksewell@umich.edu // that ERL and ERX are not set 1585222Sksewell@umich.edu // 1595222Sksewell@umich.edu Fault getInterrupt(ThreadContext * tc); 1605222Sksewell@umich.edu 1615222Sksewell@umich.edu // updateIntrInfo(ThreadContext *tc) const syncs the 1625222Sksewell@umich.edu // MIPS cause register with the instatus variable. instatus 1635222Sksewell@umich.edu // is essentially a copy of the MIPS cause[IP7:IP0] 1645222Sksewell@umich.edu // 1655222Sksewell@umich.edu void updateIntrInfo(ThreadContext *tc) const; 1665222Sksewell@umich.edu bool interruptsPending(ThreadContext *tc) const; 1675222Sksewell@umich.edu bool onCpuTimerInterrupt(ThreadContext *tc) const; 1685222Sksewell@umich.edu 1695222Sksewell@umich.edu uint64_t get_vec(int int_num); 1705222Sksewell@umich.edu 1715222Sksewell@umich.edu bool check_interrupts(ThreadContext * tc) const{ 1725222Sksewell@umich.edu return interruptsPending(tc); 1735222Sksewell@umich.edu } 1745222Sksewell@umich.edu 1755222Sksewell@umich.edu 1765222Sksewell@umich.edu void serialize(std::ostream &os) 1775222Sksewell@umich.edu { 1785222Sksewell@umich.edu fatal("Serialization of Interrupts Unimplemented for MIPS"); 1795222Sksewell@umich.edu //SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 1805222Sksewell@umich.edu //SERIALIZE_SCALAR(intstatus); 1815222Sksewell@umich.edu } 1825222Sksewell@umich.edu 1835222Sksewell@umich.edu void unserialize(Checkpoint *cp, const std::string §ion) 1845222Sksewell@umich.edu { 1855222Sksewell@umich.edu fatal("Unserialization of Interrupts Unimplemented for MIPS"); 1865222Sksewell@umich.edu //UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); 1875222Sksewell@umich.edu //UNSERIALIZE_SCALAR(intstatus); 1885222Sksewell@umich.edu } 1895222Sksewell@umich.edu 1905222Sksewell@umich.edu 1915222Sksewell@umich.edu 1925222Sksewell@umich.edu private: 1935222Sksewell@umich.edu bool newInfoSet; 1945222Sksewell@umich.edu int newIpl; 1955222Sksewell@umich.edu int newSummary; 1965222Sksewell@umich.edu 1975222Sksewell@umich.edu}; 1985222Sksewell@umich.edu 1995222Sksewell@umich.edu} 2005222Sksewell@umich.edu 2015222Sksewell@umich.edu#endif 2025222Sksewell@umich.edu 203