interrupts.hh revision 11566
15222Sksewell@umich.edu/* 25254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 35254Sksewell@umich.edu * All rights reserved. 45222Sksewell@umich.edu * 55254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145254Sksewell@umich.edu * this software without specific prior written permission. 155222Sksewell@umich.edu * 165254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275222Sksewell@umich.edu * 285254Sksewell@umich.edu * Authors: Rick Strong 295222Sksewell@umich.edu */ 305222Sksewell@umich.edu 315222Sksewell@umich.edu#ifndef __ARCH_MIPS_INTERRUPT_HH__ 325222Sksewell@umich.edu#define __ARCH_MIPS_INTERRUPT_HH__ 335222Sksewell@umich.edu 346379Sgblack@eecs.umich.edu#include <string> 356379Sgblack@eecs.umich.edu 365222Sksewell@umich.edu#include "arch/mips/faults.hh" 375222Sksewell@umich.edu#include "base/compiler.hh" 386379Sgblack@eecs.umich.edu#include "base/misc.hh" 396379Sgblack@eecs.umich.edu#include "params/MipsInterrupts.hh" 406379Sgblack@eecs.umich.edu#include "sim/serialize.hh" 416379Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 426379Sgblack@eecs.umich.edu 436379Sgblack@eecs.umich.educlass BaseCPU; 446379Sgblack@eecs.umich.educlass Checkpoint; 455222Sksewell@umich.edu 465222Sksewell@umich.edunamespace MipsISA 475222Sksewell@umich.edu{ 486378Sgblack@eecs.umich.edu 496379Sgblack@eecs.umich.educlass Interrupts : public SimObject 505222Sksewell@umich.edu{ 515222Sksewell@umich.edu public: 526379Sgblack@eecs.umich.edu typedef MipsInterruptsParams Params; 536379Sgblack@eecs.umich.edu 546379Sgblack@eecs.umich.edu const Params * 556379Sgblack@eecs.umich.edu params() const 566379Sgblack@eecs.umich.edu { 576379Sgblack@eecs.umich.edu return dynamic_cast<const Params *>(_params); 586379Sgblack@eecs.umich.edu } 596379Sgblack@eecs.umich.edu 606379Sgblack@eecs.umich.edu Interrupts(Params * p) : SimObject(p) 615222Sksewell@umich.edu { 626378Sgblack@eecs.umich.edu } 635222Sksewell@umich.edu 646379Sgblack@eecs.umich.edu void 656379Sgblack@eecs.umich.edu setCPU(BaseCPU *_cpu) 666379Sgblack@eecs.umich.edu {} 676379Sgblack@eecs.umich.edu 685222Sksewell@umich.edu // post(int int_num, int index) is responsible 695222Sksewell@umich.edu // for posting an interrupt. It sets a bit 705222Sksewell@umich.edu // in intstatus corresponding to Cause IP*. The 715222Sksewell@umich.edu // MIPS register Cause is updated by updateIntrInfo 725704Snate@binkert.org // which is called by checkInterrupts 735222Sksewell@umich.edu // 746378Sgblack@eecs.umich.edu void post(int int_num, ThreadContext *tc); 755222Sksewell@umich.edu void post(int int_num, int index); 765222Sksewell@umich.edu 775222Sksewell@umich.edu // clear(int int_num, int index) is responsible 785222Sksewell@umich.edu // for clearing an interrupt. It clear a bit 795222Sksewell@umich.edu // in intstatus corresponding to Cause IP*. The 805222Sksewell@umich.edu // MIPS register Cause is updated by updateIntrInfo 815704Snate@binkert.org // which is called by checkInterrupts 825222Sksewell@umich.edu // 835222Sksewell@umich.edu void clear(int int_num, ThreadContext* tc); 845222Sksewell@umich.edu void clear(int int_num, int index); 855222Sksewell@umich.edu 865704Snate@binkert.org // clearAll() is responsible 875222Sksewell@umich.edu // for clearing all interrupts. It clears all bits 885222Sksewell@umich.edu // in intstatus corresponding to Cause IP*. The 895222Sksewell@umich.edu // MIPS register Cause is updated by updateIntrInfo 905704Snate@binkert.org // which is called by checkInterrupts 915222Sksewell@umich.edu // 926378Sgblack@eecs.umich.edu void clearAll(ThreadContext *tc); 935704Snate@binkert.org void clearAll(); 945222Sksewell@umich.edu 955222Sksewell@umich.edu // getInterrupt(ThreadContext * tc) checks if an interrupt 965222Sksewell@umich.edu // should be returned. It ands the interrupt mask and 975222Sksewell@umich.edu // and interrupt pending bits to see if one exists. It 985222Sksewell@umich.edu // also makes sure interrupts are enabled (IE) and 995222Sksewell@umich.edu // that ERL and ERX are not set 1005222Sksewell@umich.edu // 1016378Sgblack@eecs.umich.edu Fault getInterrupt(ThreadContext *tc); 1025222Sksewell@umich.edu 1035222Sksewell@umich.edu // updateIntrInfo(ThreadContext *tc) const syncs the 1045222Sksewell@umich.edu // MIPS cause register with the instatus variable. instatus 1055222Sksewell@umich.edu // is essentially a copy of the MIPS cause[IP7:IP0] 1065222Sksewell@umich.edu // 1075222Sksewell@umich.edu void updateIntrInfo(ThreadContext *tc) const; 1085222Sksewell@umich.edu bool interruptsPending(ThreadContext *tc) const; 1095222Sksewell@umich.edu bool onCpuTimerInterrupt(ThreadContext *tc) const; 11011566Smitch.hayenga@arm.com bool checkInterrupts(ThreadContext *tc) const; 1115222Sksewell@umich.edu 1126378Sgblack@eecs.umich.edu void 11311168Sandreas.hansson@arm.com serialize(CheckpointOut &cp) const override 1145222Sksewell@umich.edu { 1155222Sksewell@umich.edu fatal("Serialization of Interrupts Unimplemented for MIPS"); 1165222Sksewell@umich.edu } 1175222Sksewell@umich.edu 1186378Sgblack@eecs.umich.edu void 11911168Sandreas.hansson@arm.com unserialize(CheckpointIn &cp) override 1205222Sksewell@umich.edu { 1215222Sksewell@umich.edu fatal("Unserialization of Interrupts Unimplemented for MIPS"); 1225222Sksewell@umich.edu } 1235222Sksewell@umich.edu}; 1245222Sksewell@umich.edu 1255222Sksewell@umich.edu} 1265222Sksewell@umich.edu 1275222Sksewell@umich.edu#endif 1285222Sksewell@umich.edu 129