faults.hh revision 8577:37dbd858c367 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Korey Sewell
31 *          Jaidev Patwardhan
32 */
33
34#ifndef __MIPS_FAULTS_HH__
35#define __MIPS_FAULTS_HH__
36
37#include "arch/mips/pra_constants.hh"
38#include "cpu/thread_context.hh"
39#include "debug/MipsPRA.hh"
40#include "sim/faults.hh"
41
42namespace MipsISA
43{
44
45typedef const Addr FaultVect;
46
47class MipsFaultBase : public FaultBase
48{
49  public:
50    struct FaultVals
51    {
52        const FaultName name;
53        const FaultVect vect;
54    };
55
56#if FULL_SYSTEM
57    void invoke(ThreadContext * tc,
58            StaticInst::StaticInstPtr inst = StaticInst::nullStaticInstPtr)
59    {}
60#endif
61    void setExceptionState(ThreadContext *, uint8_t);
62};
63
64template <typename T>
65class MipsFault : public MipsFaultBase
66{
67  protected:
68    static FaultVals vals;
69  public:
70    FaultName name() const { return vals.name; }
71    FaultVect vect() const { return vals.vect; }
72};
73
74template <typename T>
75class AddressFault : public MipsFault<T>
76{
77  protected:
78    Addr vaddr;
79    bool store;
80
81    AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
82    {}
83};
84
85template <typename T>
86class TlbFault : public AddressFault<T>
87{
88  protected:
89    Addr asid;
90    Addr vpn;
91
92    TlbFault(Addr _asid, Addr _vaddr, Addr _vpn, bool _store) :
93        AddressFault<T>(_vaddr, _store), asid(_asid), vpn(_vpn)
94    {}
95
96    void
97    setTlbExceptionState(ThreadContext *tc, uint8_t excCode)
98    {
99        DPRINTF(MipsPRA, "%s encountered.\n", name());
100        this->setExceptionState(tc, excCode);
101
102        tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr);
103        EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
104        entryHi.asid = this->asid;
105        entryHi.vpn2 = this->vpn >> 2;
106        entryHi.vpn2x = this->vpn & 0x3;
107        tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
108
109        ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
110        context.badVPN2 = this->vpn >> 2;
111        tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
112    }
113};
114
115class MachineCheckFault : public MipsFault<MachineCheckFault>
116{
117  public:
118    bool isMachineCheckFault() {return true;}
119};
120
121static inline Fault genMachineCheckFault()
122{
123    return new MachineCheckFault;
124}
125
126class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
127{
128  public:
129    bool isNonMaskableInterrupt() {return true;}
130};
131
132class AddressErrorFault : public AddressFault<AddressErrorFault>
133{
134  public:
135    AddressErrorFault(Addr _vaddr, bool _store) :
136        AddressFault<AddressErrorFault>(_vaddr, _store)
137    {}
138#if FULL_SYSTEM
139    void invoke(ThreadContext * tc,
140            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
141#endif
142
143};
144
145class ResetFault : public MipsFault<ResetFault>
146{
147  public:
148    void invoke(ThreadContext * tc,
149            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
150
151};
152
153class SystemCallFault : public MipsFault<SystemCallFault>
154{
155  public:
156#if FULL_SYSTEM
157    void invoke(ThreadContext * tc,
158            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
159#endif
160};
161
162class SoftResetFault : public MipsFault<SoftResetFault>
163{
164  public:
165    void invoke(ThreadContext * tc,
166            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
167};
168
169class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
170{
171  protected:
172    int coProcID;
173  public:
174    CoprocessorUnusableFault(int _procid) : coProcID(_procid)
175    {}
176
177    void invoke(ThreadContext * tc,
178            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
179};
180
181class ReservedInstructionFault : public MipsFault<ReservedInstructionFault>
182{
183  public:
184    void invoke(ThreadContext * tc,
185            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
186};
187
188class ThreadFault : public MipsFault<ThreadFault>
189{
190  public:
191    void invoke(ThreadContext * tc,
192            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
193};
194
195class IntegerOverflowFault : public MipsFault<IntegerOverflowFault>
196{
197  public:
198#if FULL_SYSTEM
199    void invoke(ThreadContext * tc,
200            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
201#endif
202};
203
204class InterruptFault : public MipsFault<InterruptFault>
205{
206  public:
207#if FULL_SYSTEM
208    void invoke(ThreadContext * tc,
209            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
210#endif
211};
212
213class TrapFault : public MipsFault<TrapFault>
214{
215  public:
216#if FULL_SYSTEM
217    void invoke(ThreadContext * tc,
218            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
219#endif
220};
221
222class BreakpointFault : public MipsFault<BreakpointFault>
223{
224  public:
225#if FULL_SYSTEM
226    void invoke(ThreadContext * tc,
227            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
228#endif
229};
230
231class TlbRefillFault : public TlbFault<TlbRefillFault>
232{
233  public:
234    TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store) :
235        TlbFault<TlbRefillFault>(asid, vaddr, vpn, store)
236    {}
237#if FULL_SYSTEM
238    void invoke(ThreadContext * tc,
239            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
240#endif
241};
242
243class TlbInvalidFault : public TlbFault<TlbInvalidFault>
244{
245  public:
246    TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store) :
247        TlbFault<TlbInvalidFault>(asid, vaddr, vpn, store)
248    {}
249#if FULL_SYSTEM
250    void invoke(ThreadContext * tc,
251            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
252#endif
253};
254
255class TlbModifiedFault : public TlbFault<TlbModifiedFault>
256{
257  public:
258    TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) :
259        TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false)
260    {}
261#if FULL_SYSTEM
262    void invoke(ThreadContext * tc,
263            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
264#endif
265};
266
267class DspStateDisabledFault : public MipsFault<DspStateDisabledFault>
268{
269  public:
270    void invoke(ThreadContext * tc,
271            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
272};
273
274} // namespace MipsISA
275
276#endif // __MIPS_FAULTS_HH__
277