faults.hh revision 8576:d8cca7565744 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Korey Sewell
31 *          Jaidev Patwardhan
32 */
33
34#ifndef __MIPS_FAULTS_HH__
35#define __MIPS_FAULTS_HH__
36
37#include "arch/mips/pra_constants.hh"
38#include "cpu/thread_context.hh"
39#include "debug/MipsPRA.hh"
40#include "sim/faults.hh"
41
42namespace MipsISA
43{
44
45typedef const Addr FaultVect;
46
47class MipsFaultBase : public FaultBase
48{
49  public:
50    struct FaultVals
51    {
52        const FaultName name;
53        const FaultVect vect;
54    };
55
56#if FULL_SYSTEM
57    void invoke(ThreadContext * tc,
58            StaticInst::StaticInstPtr inst = StaticInst::nullStaticInstPtr)
59    {}
60    void setHandlerPC(Addr, ThreadContext *);
61#endif
62    void setExceptionState(ThreadContext *, uint8_t);
63};
64
65template <typename T>
66class MipsFault : public MipsFaultBase
67{
68  protected:
69    static FaultVals vals;
70  public:
71    FaultName name() const { return vals.name; }
72    FaultVect vect() const { return vals.vect; }
73};
74
75template <typename T>
76class AddressFault : public MipsFault<T>
77{
78  protected:
79    Addr vaddr;
80    bool store;
81
82    AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
83    {}
84};
85
86template <typename T>
87class TlbFault : public AddressFault<T>
88{
89  protected:
90    Addr asid;
91    Addr vpn;
92
93    TlbFault(Addr _asid, Addr _vaddr, Addr _vpn, bool _store) :
94        AddressFault<T>(_vaddr, _store), asid(_asid), vpn(_vpn)
95    {}
96
97    void
98    setTlbExceptionState(ThreadContext *tc, uint8_t excCode)
99    {
100        DPRINTF(MipsPRA, "%s encountered.\n", name());
101        this->setExceptionState(tc, excCode);
102
103        tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr);
104        EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
105        entryHi.asid = this->asid;
106        entryHi.vpn2 = this->vpn >> 2;
107        entryHi.vpn2x = this->vpn & 0x3;
108        tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
109
110        ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
111        context.badVPN2 = this->vpn >> 2;
112        tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
113    }
114};
115
116class MachineCheckFault : public MipsFault<MachineCheckFault>
117{
118  public:
119    bool isMachineCheckFault() {return true;}
120};
121
122static inline Fault genMachineCheckFault()
123{
124    return new MachineCheckFault;
125}
126
127class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
128{
129  public:
130    bool isNonMaskableInterrupt() {return true;}
131};
132
133class AddressErrorFault : public AddressFault<AddressErrorFault>
134{
135  public:
136    AddressErrorFault(Addr _vaddr, bool _store) :
137        AddressFault<AddressErrorFault>(_vaddr, _store)
138    {}
139#if FULL_SYSTEM
140    void invoke(ThreadContext * tc,
141            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
142#endif
143
144};
145
146class ResetFault : public MipsFault<ResetFault>
147{
148  public:
149    void invoke(ThreadContext * tc,
150            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
151
152};
153
154class SystemCallFault : public MipsFault<SystemCallFault>
155{
156  public:
157#if FULL_SYSTEM
158    void invoke(ThreadContext * tc,
159            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
160#endif
161};
162
163class SoftResetFault : public MipsFault<SoftResetFault>
164{
165  public:
166    void invoke(ThreadContext * tc,
167            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
168};
169
170class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
171{
172  protected:
173    int coProcID;
174  public:
175    CoprocessorUnusableFault(int _procid) : coProcID(_procid)
176    {}
177
178    void invoke(ThreadContext * tc,
179            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
180};
181
182class ReservedInstructionFault : public MipsFault<ReservedInstructionFault>
183{
184  public:
185    void invoke(ThreadContext * tc,
186            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
187};
188
189class ThreadFault : public MipsFault<ThreadFault>
190{
191  public:
192    void invoke(ThreadContext * tc,
193            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
194};
195
196class IntegerOverflowFault : public MipsFault<IntegerOverflowFault>
197{
198  public:
199#if FULL_SYSTEM
200    void invoke(ThreadContext * tc,
201            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
202#endif
203};
204
205class InterruptFault : public MipsFault<InterruptFault>
206{
207  public:
208#if FULL_SYSTEM
209    void invoke(ThreadContext * tc,
210            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
211#endif
212};
213
214class TrapFault : public MipsFault<TrapFault>
215{
216  public:
217#if FULL_SYSTEM
218    void invoke(ThreadContext * tc,
219            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
220#endif
221};
222
223class BreakpointFault : public MipsFault<BreakpointFault>
224{
225  public:
226#if FULL_SYSTEM
227    void invoke(ThreadContext * tc,
228            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
229#endif
230};
231
232class TlbRefillFault : public TlbFault<TlbRefillFault>
233{
234  public:
235    TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store) :
236        TlbFault<TlbRefillFault>(asid, vaddr, vpn, store)
237    {}
238#if FULL_SYSTEM
239    void invoke(ThreadContext * tc,
240            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
241#endif
242};
243
244class TlbInvalidFault : public TlbFault<TlbInvalidFault>
245{
246  public:
247    TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store) :
248        TlbFault<TlbInvalidFault>(asid, vaddr, vpn, store)
249    {}
250#if FULL_SYSTEM
251    void invoke(ThreadContext * tc,
252            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
253#endif
254};
255
256class TlbModifiedFault : public TlbFault<TlbModifiedFault>
257{
258  public:
259    TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) :
260        TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false)
261    {}
262#if FULL_SYSTEM
263    void invoke(ThreadContext * tc,
264            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
265#endif
266};
267
268class DspStateDisabledFault : public MipsFault<DspStateDisabledFault>
269{
270  public:
271    void invoke(ThreadContext * tc,
272            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
273};
274
275} // namespace MipsISA
276
277#endif // __MIPS_FAULTS_HH__
278