faults.hh revision 8567:d154cd83c353
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Gabe Black 30 * Korey Sewell 31 * Jaidev Patwardhan 32 */ 33 34#ifndef __MIPS_FAULTS_HH__ 35#define __MIPS_FAULTS_HH__ 36 37#include "sim/faults.hh" 38 39namespace MipsISA 40{ 41 42typedef const Addr FaultVect; 43 44class MipsFaultBase : public FaultBase 45{ 46 protected: 47 virtual bool skipFaultingInstruction() {return false;} 48 virtual bool setRestartAddress() {return true;} 49 public: 50 struct FaultVals 51 { 52 const FaultName name; 53 const FaultVect vect; 54 FaultStat count; 55 }; 56 57 Addr badVAddr; 58 Addr entryHiAsid; 59 Addr entryHiVPN2; 60 Addr entryHiVPN2X; 61 Addr contextBadVPN2; 62#if FULL_SYSTEM 63 void invoke(ThreadContext * tc, 64 StaticInst::StaticInstPtr inst = StaticInst::nullStaticInstPtr) 65 {} 66 void setExceptionState(ThreadContext *, uint8_t); 67 void setHandlerPC(Addr, ThreadContext *); 68#endif 69}; 70 71template <typename T> 72class MipsFault : public MipsFaultBase 73{ 74 protected: 75 static FaultVals vals; 76 public: 77 FaultName name() const { return vals.name; } 78 FaultVect vect() const { return vals.vect; } 79 FaultStat & countStat() { return vals.count; } 80}; 81 82class MachineCheckFault : public MipsFault<MachineCheckFault> 83{ 84 public: 85 bool isMachineCheckFault() {return true;} 86}; 87 88class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt> 89{ 90 public: 91 bool isNonMaskableInterrupt() {return true;} 92}; 93 94class AlignmentFault : public MipsFault<AlignmentFault> 95{ 96 public: 97 bool isAlignmentFault() {return true;} 98}; 99 100class AddressErrorFault : public MipsFault<AddressErrorFault> 101{ 102 public: 103 AddressErrorFault(Addr vaddr) { badVAddr = vaddr; } 104#if FULL_SYSTEM 105 void invoke(ThreadContext * tc, 106 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 107#endif 108 109}; 110 111class StoreAddressErrorFault : public MipsFault<StoreAddressErrorFault> 112{ 113 public: 114 StoreAddressErrorFault(Addr vaddr) { badVAddr = vaddr; } 115#if FULL_SYSTEM 116 void invoke(ThreadContext * tc, 117 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 118#endif 119}; 120 121class UnimplementedOpcodeFault : public MipsFault<UnimplementedOpcodeFault> {}; 122 123class TLBRefillIFetchFault : public MipsFault<TLBRefillIFetchFault> 124{ 125 public: 126 void invoke(ThreadContext * tc, 127 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 128}; 129 130class TLBInvalidIFetchFault : public MipsFault<TLBInvalidIFetchFault> 131{ 132 public: 133 void invoke(ThreadContext * tc, 134 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 135}; 136 137class NDtbMissFault : public MipsFault<NDtbMissFault> {}; 138class PDtbMissFault : public MipsFault<PDtbMissFault> {}; 139class DtbPageFault : public MipsFault<DtbPageFault> {}; 140class DtbAcvFault : public MipsFault<DtbAcvFault> {}; 141 142static inline Fault genMachineCheckFault() 143{ 144 return new MachineCheckFault; 145} 146 147static inline Fault genAlignmentFault() 148{ 149 return new AlignmentFault; 150} 151 152class ResetFault : public MipsFault<ResetFault> 153{ 154 public: 155 void invoke(ThreadContext * tc, 156 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 157 158}; 159 160class SystemCallFault : public MipsFault<SystemCallFault> 161{ 162 public: 163#if FULL_SYSTEM 164 void invoke(ThreadContext * tc, 165 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 166#endif 167}; 168 169class SoftResetFault : public MipsFault<SoftResetFault> 170{ 171 public: 172 void invoke(ThreadContext * tc, 173 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 174}; 175 176class DebugSingleStep : public MipsFault<DebugSingleStep> 177{ 178 public: 179 void invoke(ThreadContext * tc, 180 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 181}; 182 183class DebugInterrupt : public MipsFault<DebugInterrupt> 184{ 185 public: 186 void invoke(ThreadContext * tc, 187 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 188}; 189 190class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault> 191{ 192 protected: 193 int coProcID; 194 public: 195 CoprocessorUnusableFault(int _procid) : coProcID(_procid) 196 {} 197 198 void invoke(ThreadContext * tc, 199 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 200}; 201 202class ReservedInstructionFault : public MipsFault<ReservedInstructionFault> 203{ 204 public: 205 void invoke(ThreadContext * tc, 206 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 207}; 208 209class ThreadFault : public MipsFault<ThreadFault> 210{ 211 public: 212 void invoke(ThreadContext * tc, 213 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 214}; 215 216class ArithmeticFault : public MipsFault<ArithmeticFault> 217{ 218 protected: 219 bool skipFaultingInstruction() {return true;} 220 public: 221#if FULL_SYSTEM 222 void invoke(ThreadContext * tc, 223 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 224#endif 225}; 226 227class InterruptFault : public MipsFault<InterruptFault> 228{ 229 protected: 230 bool setRestartAddress() {return false;} 231 public: 232#if FULL_SYSTEM 233 void invoke(ThreadContext * tc, 234 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 235#endif 236}; 237 238class TrapFault : public MipsFault<TrapFault> 239{ 240 public: 241#if FULL_SYSTEM 242 void invoke(ThreadContext * tc, 243 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 244#endif 245}; 246 247class BreakpointFault : public MipsFault<BreakpointFault> 248{ 249 public: 250#if FULL_SYSTEM 251 void invoke(ThreadContext * tc, 252 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 253#endif 254}; 255 256class ItbRefillFault : public MipsFault<ItbRefillFault> 257{ 258 public: 259 ItbRefillFault(Addr asid, Addr vaddr, Addr vpn) 260 { 261 entryHiAsid = asid; 262 entryHiVPN2 = vpn >> 2; 263 entryHiVPN2X = vpn & 0x3; 264 badVAddr = vaddr; 265 contextBadVPN2 = vpn >> 2; 266 } 267#if FULL_SYSTEM 268 void invoke(ThreadContext * tc, 269 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 270#endif 271}; 272 273class DtbRefillFault : public MipsFault<DtbRefillFault> 274{ 275 public: 276 DtbRefillFault(Addr asid, Addr vaddr, Addr vpn) 277 { 278 entryHiAsid = asid; 279 entryHiVPN2 = vpn >> 2; 280 entryHiVPN2X = vpn & 0x3; 281 badVAddr = vaddr; 282 contextBadVPN2 = vpn >> 2; 283 } 284#if FULL_SYSTEM 285 void invoke(ThreadContext * tc, 286 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 287#endif 288}; 289 290class ItbPageFault : public MipsFault<ItbPageFault> 291{ 292 public: 293#if FULL_SYSTEM 294 void invoke(ThreadContext * tc, 295 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 296#endif 297}; 298 299class ItbInvalidFault : public MipsFault<ItbInvalidFault> 300{ 301 public: 302 ItbInvalidFault(Addr asid, Addr vaddr, Addr vpn) 303 { 304 entryHiAsid = asid; 305 entryHiVPN2 = vpn >> 2; 306 entryHiVPN2X = vpn & 0x3; 307 badVAddr = vaddr; 308 contextBadVPN2 = vpn >> 2; 309 } 310#if FULL_SYSTEM 311 void invoke(ThreadContext * tc, 312 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 313#endif 314}; 315 316class TLBModifiedFault : public MipsFault<TLBModifiedFault> 317{ 318 public: 319 TLBModifiedFault(Addr asid, Addr vaddr, Addr vpn) 320 { 321 entryHiAsid = asid; 322 entryHiVPN2 = vpn >> 2; 323 entryHiVPN2X = vpn & 0x3; 324 badVAddr = vaddr; 325 contextBadVPN2 = vpn >> 2; 326 } 327#if FULL_SYSTEM 328 void invoke(ThreadContext * tc, 329 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 330#endif 331}; 332 333class DtbInvalidFault : public MipsFault<DtbInvalidFault> 334{ 335 public: 336 DtbInvalidFault(Addr asid, Addr vaddr, Addr vpn) 337 { 338 entryHiAsid = asid; 339 entryHiVPN2 = vpn >> 2; 340 entryHiVPN2X = vpn & 0x3; 341 badVAddr = vaddr; 342 contextBadVPN2 = vpn >> 2; 343 } 344#if FULL_SYSTEM 345 void invoke(ThreadContext * tc, 346 StaticInst::StaticInstPtr inst = nullStaticInstPtr); 347#endif 348}; 349 350class FloatEnableFault : public MipsFault<FloatEnableFault> {}; 351class ItbMissFault : public MipsFault<ItbMissFault> {}; 352class ItbAcvFault : public MipsFault<ItbAcvFault> {}; 353class IntegerOverflowFault : public MipsFault<IntegerOverflowFault> {}; 354 355class DspStateDisabledFault : public MipsFault<DspStateDisabledFault> 356{ 357 public: 358 void invoke(ThreadContext * tc, 359 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 360}; 361 362} // namespace MipsISA 363 364#endif // __MIPS_FAULTS_HH__ 365