faults.hh revision 8738
12131SN/A/* 25268Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35224Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45224Sksewell@umich.edu * All rights reserved. 52131SN/A * 65224Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75224Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85224Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95224Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105224Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115224Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125224Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135224Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145224Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155224Sksewell@umich.edu * this software without specific prior written permission. 162131SN/A * 175224Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185224Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195224Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205224Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215224Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225224Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235224Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245224Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255224Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265224Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275224Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 295224Sksewell@umich.edu * Authors: Gabe Black 305224Sksewell@umich.edu * Korey Sewell 315222Sksewell@umich.edu * Jaidev Patwardhan 322131SN/A */ 332131SN/A 342239SN/A#ifndef __MIPS_FAULTS_HH__ 352239SN/A#define __MIPS_FAULTS_HH__ 362131SN/A 378575Sgblack@eecs.umich.edu#include "arch/mips/pra_constants.hh" 388575Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 398575Sgblack@eecs.umich.edu#include "debug/MipsPRA.hh" 402131SN/A#include "sim/faults.hh" 418738Sgblack@eecs.umich.edu#include "sim/full_system.hh" 422447SN/A 432447SN/Anamespace MipsISA 442447SN/A{ 456378Sgblack@eecs.umich.edu 462447SN/Atypedef const Addr FaultVect; 472131SN/A 488578Sgblack@eecs.umich.eduenum ExcCode { 498578Sgblack@eecs.umich.edu // A dummy value to use when the code isn't defined or doesn't matter. 508578Sgblack@eecs.umich.edu ExcCodeDummy = 0, 518578Sgblack@eecs.umich.edu 528578Sgblack@eecs.umich.edu ExcCodeInt = 0, 538578Sgblack@eecs.umich.edu ExcCodeMod = 1, 548578Sgblack@eecs.umich.edu ExcCodeTlbL = 2, 558578Sgblack@eecs.umich.edu ExcCodeTlbS = 3, 568578Sgblack@eecs.umich.edu ExcCodeAdEL = 4, 578578Sgblack@eecs.umich.edu ExcCodeAdES = 5, 588578Sgblack@eecs.umich.edu ExcCodeIBE = 6, 598578Sgblack@eecs.umich.edu ExcCodeDBE = 7, 608578Sgblack@eecs.umich.edu ExcCodeSys = 8, 618578Sgblack@eecs.umich.edu ExcCodeBp = 9, 628578Sgblack@eecs.umich.edu ExcCodeRI = 10, 638578Sgblack@eecs.umich.edu ExcCodeCpU = 11, 648578Sgblack@eecs.umich.edu ExcCodeOv = 12, 658578Sgblack@eecs.umich.edu ExcCodeTr = 13, 668578Sgblack@eecs.umich.edu ExcCodeC2E = 18, 678578Sgblack@eecs.umich.edu ExcCodeMDMX = 22, 688578Sgblack@eecs.umich.edu ExcCodeWatch = 23, 698578Sgblack@eecs.umich.edu ExcCodeMCheck = 24, 708578Sgblack@eecs.umich.edu ExcCodeThread = 25, 718578Sgblack@eecs.umich.edu ExcCodeCacheErr = 30 728578Sgblack@eecs.umich.edu}; 738578Sgblack@eecs.umich.edu 748566Sgblack@eecs.umich.educlass MipsFaultBase : public FaultBase 752131SN/A{ 762131SN/A public: 778566Sgblack@eecs.umich.edu struct FaultVals 788566Sgblack@eecs.umich.edu { 798566Sgblack@eecs.umich.edu const FaultName name; 808578Sgblack@eecs.umich.edu const FaultVect offset; 818578Sgblack@eecs.umich.edu const ExcCode code; 828566Sgblack@eecs.umich.edu }; 838566Sgblack@eecs.umich.edu 848578Sgblack@eecs.umich.edu void setExceptionState(ThreadContext *, uint8_t); 858578Sgblack@eecs.umich.edu 868578Sgblack@eecs.umich.edu virtual FaultVect offset(ThreadContext *tc) const = 0; 878578Sgblack@eecs.umich.edu virtual ExcCode code() const = 0; 888578Sgblack@eecs.umich.edu virtual FaultVect base(ThreadContext *tc) const 898578Sgblack@eecs.umich.edu { 908578Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 918578Sgblack@eecs.umich.edu if (status.bev) 928578Sgblack@eecs.umich.edu return tc->readMiscReg(MISCREG_EBASE); 938578Sgblack@eecs.umich.edu else 948578Sgblack@eecs.umich.edu return 0xbfc00200; 958578Sgblack@eecs.umich.edu } 968578Sgblack@eecs.umich.edu 978578Sgblack@eecs.umich.edu FaultVect 988578Sgblack@eecs.umich.edu vect(ThreadContext *tc) const 998578Sgblack@eecs.umich.edu { 1008578Sgblack@eecs.umich.edu return base(tc) + offset(tc); 1018578Sgblack@eecs.umich.edu } 1028578Sgblack@eecs.umich.edu 1037678Sgblack@eecs.umich.edu void invoke(ThreadContext * tc, 1048578Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 1052131SN/A}; 1062131SN/A 1078566Sgblack@eecs.umich.edutemplate <typename T> 1088566Sgblack@eecs.umich.educlass MipsFault : public MipsFaultBase 1092131SN/A{ 1108566Sgblack@eecs.umich.edu protected: 1118566Sgblack@eecs.umich.edu static FaultVals vals; 1122131SN/A public: 1138566Sgblack@eecs.umich.edu FaultName name() const { return vals.name; } 1148578Sgblack@eecs.umich.edu FaultVect offset(ThreadContext *tc) const { return vals.offset; } 1158578Sgblack@eecs.umich.edu ExcCode code() const { return vals.code; } 1168578Sgblack@eecs.umich.edu}; 1178578Sgblack@eecs.umich.edu 1188578Sgblack@eecs.umich.educlass SystemCallFault : public MipsFault<SystemCallFault> {}; 1198578Sgblack@eecs.umich.educlass ReservedInstructionFault : public MipsFault<ReservedInstructionFault> {}; 1208578Sgblack@eecs.umich.educlass ThreadFault : public MipsFault<ThreadFault> {}; 1218578Sgblack@eecs.umich.educlass IntegerOverflowFault : public MipsFault<IntegerOverflowFault> {}; 1228578Sgblack@eecs.umich.educlass TrapFault : public MipsFault<TrapFault> {}; 1238578Sgblack@eecs.umich.educlass BreakpointFault : public MipsFault<BreakpointFault> {}; 1248578Sgblack@eecs.umich.educlass DspStateDisabledFault : public MipsFault<DspStateDisabledFault> {}; 1258578Sgblack@eecs.umich.edu 1268578Sgblack@eecs.umich.educlass MachineCheckFault : public MipsFault<MachineCheckFault> 1278578Sgblack@eecs.umich.edu{ 1288578Sgblack@eecs.umich.edu public: 1298578Sgblack@eecs.umich.edu bool isMachineCheckFault() { return true; } 1308578Sgblack@eecs.umich.edu}; 1318578Sgblack@eecs.umich.edu 1328578Sgblack@eecs.umich.educlass ResetFault : public MipsFault<ResetFault> 1338578Sgblack@eecs.umich.edu{ 1348578Sgblack@eecs.umich.edu public: 1358578Sgblack@eecs.umich.edu void invoke(ThreadContext * tc, 1368578Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 1378578Sgblack@eecs.umich.edu 1388578Sgblack@eecs.umich.edu}; 1398578Sgblack@eecs.umich.edu 1408578Sgblack@eecs.umich.educlass SoftResetFault : public MipsFault<SoftResetFault> 1418578Sgblack@eecs.umich.edu{ 1428578Sgblack@eecs.umich.edu public: 1438578Sgblack@eecs.umich.edu void invoke(ThreadContext * tc, 1448578Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 1458578Sgblack@eecs.umich.edu}; 1468578Sgblack@eecs.umich.edu 1478578Sgblack@eecs.umich.educlass NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt> 1488578Sgblack@eecs.umich.edu{ 1498578Sgblack@eecs.umich.edu public: 1508578Sgblack@eecs.umich.edu void invoke(ThreadContext * tc, 1518578Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 1528578Sgblack@eecs.umich.edu}; 1538578Sgblack@eecs.umich.edu 1548578Sgblack@eecs.umich.educlass CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault> 1558578Sgblack@eecs.umich.edu{ 1568578Sgblack@eecs.umich.edu protected: 1578578Sgblack@eecs.umich.edu int coProcID; 1588578Sgblack@eecs.umich.edu public: 1598578Sgblack@eecs.umich.edu CoprocessorUnusableFault(int _procid) : coProcID(_procid) 1608578Sgblack@eecs.umich.edu {} 1618578Sgblack@eecs.umich.edu 1628578Sgblack@eecs.umich.edu void 1638578Sgblack@eecs.umich.edu invoke(ThreadContext * tc, 1648578Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr) 1658578Sgblack@eecs.umich.edu { 1668578Sgblack@eecs.umich.edu MipsFault<CoprocessorUnusableFault>::invoke(tc, inst); 1678738Sgblack@eecs.umich.edu if (FullSystem) { 1688578Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 1698578Sgblack@eecs.umich.edu cause.ce = coProcID; 1708578Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CAUSE, cause); 1718578Sgblack@eecs.umich.edu } 1728578Sgblack@eecs.umich.edu } 1738578Sgblack@eecs.umich.edu}; 1748578Sgblack@eecs.umich.edu 1758578Sgblack@eecs.umich.educlass InterruptFault : public MipsFault<InterruptFault> 1768578Sgblack@eecs.umich.edu{ 1778578Sgblack@eecs.umich.edu public: 1788578Sgblack@eecs.umich.edu FaultVect 1798578Sgblack@eecs.umich.edu offset(ThreadContext *tc) const 1808578Sgblack@eecs.umich.edu { 1818578Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); 1828578Sgblack@eecs.umich.edu return cause.iv ? 0x200 : 0x000; 1838578Sgblack@eecs.umich.edu } 1848566Sgblack@eecs.umich.edu}; 1858566Sgblack@eecs.umich.edu 1868575Sgblack@eecs.umich.edutemplate <typename T> 1878575Sgblack@eecs.umich.educlass AddressFault : public MipsFault<T> 1888575Sgblack@eecs.umich.edu{ 1898575Sgblack@eecs.umich.edu protected: 1908575Sgblack@eecs.umich.edu Addr vaddr; 1918575Sgblack@eecs.umich.edu bool store; 1928575Sgblack@eecs.umich.edu 1938575Sgblack@eecs.umich.edu AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store) 1948575Sgblack@eecs.umich.edu {} 1958578Sgblack@eecs.umich.edu 1968578Sgblack@eecs.umich.edu void 1978578Sgblack@eecs.umich.edu invoke(ThreadContext * tc, 1988578Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr) 1998578Sgblack@eecs.umich.edu { 2008578Sgblack@eecs.umich.edu MipsFault<T>::invoke(tc, inst); 2018738Sgblack@eecs.umich.edu if (FullSystem) 2028578Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr); 2038578Sgblack@eecs.umich.edu } 2048578Sgblack@eecs.umich.edu}; 2058578Sgblack@eecs.umich.edu 2068578Sgblack@eecs.umich.educlass AddressErrorFault : public AddressFault<AddressErrorFault> 2078578Sgblack@eecs.umich.edu{ 2088578Sgblack@eecs.umich.edu public: 2098578Sgblack@eecs.umich.edu AddressErrorFault(Addr _vaddr, bool _store) : 2108578Sgblack@eecs.umich.edu AddressFault<AddressErrorFault>(_vaddr, _store) 2118578Sgblack@eecs.umich.edu {} 2128578Sgblack@eecs.umich.edu 2138578Sgblack@eecs.umich.edu ExcCode 2148578Sgblack@eecs.umich.edu code() const 2158578Sgblack@eecs.umich.edu { 2168578Sgblack@eecs.umich.edu return store ? ExcCodeAdES : ExcCodeAdEL; 2178578Sgblack@eecs.umich.edu } 2188578Sgblack@eecs.umich.edu 2198575Sgblack@eecs.umich.edu}; 2208575Sgblack@eecs.umich.edu 2218575Sgblack@eecs.umich.edutemplate <typename T> 2228575Sgblack@eecs.umich.educlass TlbFault : public AddressFault<T> 2238575Sgblack@eecs.umich.edu{ 2248575Sgblack@eecs.umich.edu protected: 2258575Sgblack@eecs.umich.edu Addr asid; 2268575Sgblack@eecs.umich.edu Addr vpn; 2278575Sgblack@eecs.umich.edu 2288575Sgblack@eecs.umich.edu TlbFault(Addr _asid, Addr _vaddr, Addr _vpn, bool _store) : 2298575Sgblack@eecs.umich.edu AddressFault<T>(_vaddr, _store), asid(_asid), vpn(_vpn) 2308575Sgblack@eecs.umich.edu {} 2318575Sgblack@eecs.umich.edu 2328575Sgblack@eecs.umich.edu void 2338575Sgblack@eecs.umich.edu setTlbExceptionState(ThreadContext *tc, uint8_t excCode) 2348575Sgblack@eecs.umich.edu { 2358575Sgblack@eecs.umich.edu this->setExceptionState(tc, excCode); 2368575Sgblack@eecs.umich.edu 2378575Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr); 2388575Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2398575Sgblack@eecs.umich.edu entryHi.asid = this->asid; 2408575Sgblack@eecs.umich.edu entryHi.vpn2 = this->vpn >> 2; 2418575Sgblack@eecs.umich.edu entryHi.vpn2x = this->vpn & 0x3; 2428575Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2438575Sgblack@eecs.umich.edu 2448575Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2458575Sgblack@eecs.umich.edu context.badVPN2 = this->vpn >> 2; 2468575Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2478575Sgblack@eecs.umich.edu } 2488575Sgblack@eecs.umich.edu 2498578Sgblack@eecs.umich.edu void 2508578Sgblack@eecs.umich.edu invoke(ThreadContext * tc, 2518578Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr) 2528578Sgblack@eecs.umich.edu { 2538738Sgblack@eecs.umich.edu if (FullSystem) { 2548578Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Fault %s encountered.\n", name()); 2558578Sgblack@eecs.umich.edu tc->pcState(this->vect(tc)); 2568578Sgblack@eecs.umich.edu setTlbExceptionState(tc, this->code()); 2578578Sgblack@eecs.umich.edu } else { 2588578Sgblack@eecs.umich.edu AddressFault<T>::invoke(tc, inst); 2598578Sgblack@eecs.umich.edu } 2608578Sgblack@eecs.umich.edu } 2615222Sksewell@umich.edu 2628578Sgblack@eecs.umich.edu ExcCode 2638578Sgblack@eecs.umich.edu code() const 2648578Sgblack@eecs.umich.edu { 2658578Sgblack@eecs.umich.edu return this->store ? ExcCodeTlbS : ExcCodeTlbL; 2668578Sgblack@eecs.umich.edu } 2675222Sksewell@umich.edu}; 2685222Sksewell@umich.edu 2698575Sgblack@eecs.umich.educlass TlbRefillFault : public TlbFault<TlbRefillFault> 2705222Sksewell@umich.edu{ 2715222Sksewell@umich.edu public: 2728575Sgblack@eecs.umich.edu TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store) : 2738575Sgblack@eecs.umich.edu TlbFault<TlbRefillFault>(asid, vaddr, vpn, store) 2748575Sgblack@eecs.umich.edu {} 2758578Sgblack@eecs.umich.edu 2768578Sgblack@eecs.umich.edu FaultVect 2778578Sgblack@eecs.umich.edu offset(ThreadContext *tc) const 2788578Sgblack@eecs.umich.edu { 2798578Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 2808578Sgblack@eecs.umich.edu return status.exl ? 0x180 : 0x000; 2818578Sgblack@eecs.umich.edu } 2825222Sksewell@umich.edu}; 2836378Sgblack@eecs.umich.edu 2848575Sgblack@eecs.umich.educlass TlbInvalidFault : public TlbFault<TlbInvalidFault> 2855222Sksewell@umich.edu{ 2865222Sksewell@umich.edu public: 2878575Sgblack@eecs.umich.edu TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store) : 2888575Sgblack@eecs.umich.edu TlbFault<TlbInvalidFault>(asid, vaddr, vpn, store) 2898575Sgblack@eecs.umich.edu {} 2906378Sgblack@eecs.umich.edu}; 2915222Sksewell@umich.edu 2928575Sgblack@eecs.umich.educlass TlbModifiedFault : public TlbFault<TlbModifiedFault> 2935222Sksewell@umich.edu{ 2945222Sksewell@umich.edu public: 2958575Sgblack@eecs.umich.edu TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) : 2968575Sgblack@eecs.umich.edu TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false) 2978575Sgblack@eecs.umich.edu {} 2985222Sksewell@umich.edu 2998578Sgblack@eecs.umich.edu ExcCode code() const { return vals.code; } 3004661Sksewell@umich.edu}; 3014661Sksewell@umich.edu 3027811Ssteve.reinhardt@amd.com} // namespace MipsISA 3032131SN/A 3045222Sksewell@umich.edu#endif // __MIPS_FAULTS_HH__ 305