faults.hh revision 8566
110663SN/A/*
210663SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
310663SN/A * Copyright (c) 2007 MIPS Technologies, Inc.
410663SN/A * All rights reserved.
510663SN/A *
610663SN/A * Redistribution and use in source and binary forms, with or without
710663SN/A * modification, are permitted provided that the following conditions are
810663SN/A * met: redistributions of source code must retain the above copyright
910663SN/A * notice, this list of conditions and the following disclaimer;
1010663SN/A * redistributions in binary form must reproduce the above copyright
1110663SN/A * notice, this list of conditions and the following disclaimer in the
1210663SN/A * documentation and/or other materials provided with the distribution;
1310663SN/A * neither the name of the copyright holders nor the names of its
1410663SN/A * contributors may be used to endorse or promote products derived from
1510663SN/A * this software without specific prior written permission.
1610663SN/A *
1710663SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1810663SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1910663SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
2010663SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2110663SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2210663SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2310663SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2410663SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2510663SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2610663SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2710663SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2810663SN/A *
2910663SN/A * Authors: Gabe Black
3010663SN/A *          Korey Sewell
3110663SN/A *          Jaidev Patwardhan
3210663SN/A */
3310695SAli.Saidi@ARM.com
3410695SAli.Saidi@ARM.com#ifndef __MIPS_FAULTS_HH__
3510695SAli.Saidi@ARM.com#define __MIPS_FAULTS_HH__
3610695SAli.Saidi@ARM.com
3710695SAli.Saidi@ARM.com#include "sim/faults.hh"
38
39namespace MipsISA
40{
41
42typedef const Addr FaultVect;
43
44class MipsFaultBase : public FaultBase
45{
46  protected:
47    virtual bool skipFaultingInstruction() {return false;}
48    virtual bool setRestartAddress() {return true;}
49  public:
50    struct FaultVals
51    {
52        const FaultName name;
53        const FaultVect vect;
54        FaultStat count;
55    };
56
57    Addr badVAddr;
58    Addr entryHiAsid;
59    Addr entryHiVPN2;
60    Addr entryHiVPN2X;
61    Addr contextBadVPN2;
62#if FULL_SYSTEM
63    void invoke(ThreadContext * tc,
64            StaticInst::StaticInstPtr inst = StaticInst::nullStaticInstPtr)
65    {}
66    void setExceptionState(ThreadContext *, uint8_t);
67    void setHandlerPC(Addr, ThreadContext *);
68#endif
69};
70
71template <typename T>
72class MipsFault : public MipsFaultBase
73{
74  protected:
75    static FaultVals vals;
76  public:
77    FaultName name() const { return vals.name; }
78    FaultVect vect() const { return vals.vect; }
79    FaultStat & countStat() { return vals.count; }
80};
81
82class MachineCheckFault : public MipsFault<MachineCheckFault>
83{
84  public:
85    bool isMachineCheckFault() {return true;}
86};
87
88class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
89{
90  public:
91    bool isNonMaskableInterrupt() {return true;}
92};
93
94class AlignmentFault : public MipsFault<AlignmentFault>
95{
96  public:
97    bool isAlignmentFault() {return true;}
98};
99
100class AddressErrorFault : public MipsFault<AddressErrorFault>
101{
102  public:
103#if FULL_SYSTEM
104    void invoke(ThreadContext * tc,
105            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
106#endif
107
108};
109
110class StoreAddressErrorFault : public MipsFault<StoreAddressErrorFault>
111{
112  public:
113#if FULL_SYSTEM
114    void invoke(ThreadContext * tc,
115            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
116#endif
117};
118
119class UnimplementedOpcodeFault : public MipsFault<UnimplementedOpcodeFault> {};
120
121class TLBRefillIFetchFault : public MipsFault<TLBRefillIFetchFault>
122{
123  public:
124    void invoke(ThreadContext * tc,
125            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
126};
127
128class TLBInvalidIFetchFault : public MipsFault<TLBInvalidIFetchFault>
129{
130  public:
131    void invoke(ThreadContext * tc,
132            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
133};
134
135class NDtbMissFault : public MipsFault<NDtbMissFault> {};
136class PDtbMissFault : public MipsFault<PDtbMissFault> {};
137class DtbPageFault : public MipsFault<DtbPageFault> {};
138class DtbAcvFault : public MipsFault<DtbAcvFault> {};
139
140static inline Fault genMachineCheckFault()
141{
142    return new MachineCheckFault;
143}
144
145static inline Fault genAlignmentFault()
146{
147    return new AlignmentFault;
148}
149
150class ResetFault : public MipsFault<ResetFault>
151{
152  public:
153    void invoke(ThreadContext * tc,
154            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
155
156};
157
158class SystemCallFault : public MipsFault<SystemCallFault>
159{
160  public:
161#if FULL_SYSTEM
162    void invoke(ThreadContext * tc,
163            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
164#endif
165};
166
167class SoftResetFault : public MipsFault<SoftResetFault>
168{
169  public:
170    void invoke(ThreadContext * tc,
171            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
172};
173
174class DebugSingleStep : public MipsFault<DebugSingleStep>
175{
176  public:
177    void invoke(ThreadContext * tc,
178            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
179};
180
181class DebugInterrupt : public MipsFault<DebugInterrupt>
182{
183  public:
184    void invoke(ThreadContext * tc,
185            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
186};
187
188class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
189{
190  protected:
191    int coProcID;
192  public:
193    CoprocessorUnusableFault(int _procid) : coProcID(_procid)
194    {}
195
196    void invoke(ThreadContext * tc,
197            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
198};
199
200class ReservedInstructionFault : public MipsFault<ReservedInstructionFault>
201{
202  public:
203    void invoke(ThreadContext * tc,
204            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
205};
206
207class ThreadFault : public MipsFault<ThreadFault>
208{
209  public:
210    void invoke(ThreadContext * tc,
211            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
212};
213
214class ArithmeticFault : public MipsFault<ArithmeticFault>
215{
216  protected:
217    bool skipFaultingInstruction() {return true;}
218  public:
219#if FULL_SYSTEM
220    void invoke(ThreadContext * tc,
221            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
222#endif
223};
224
225class InterruptFault : public MipsFault<InterruptFault>
226{
227  protected:
228    bool setRestartAddress() {return false;}
229  public:
230#if FULL_SYSTEM
231    void invoke(ThreadContext * tc,
232            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
233#endif
234};
235
236class TrapFault : public MipsFault<TrapFault>
237{
238  public:
239#if FULL_SYSTEM
240    void invoke(ThreadContext * tc,
241            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
242#endif
243};
244
245class BreakpointFault : public MipsFault<BreakpointFault>
246{
247  public:
248#if FULL_SYSTEM
249    void invoke(ThreadContext * tc,
250            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
251#endif
252};
253
254class ItbRefillFault : public MipsFault<ItbRefillFault>
255{
256  public:
257#if FULL_SYSTEM
258    void invoke(ThreadContext * tc,
259            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
260#endif
261};
262
263class DtbRefillFault : public MipsFault<DtbRefillFault>
264{
265  public:
266#if FULL_SYSTEM
267    void invoke(ThreadContext * tc,
268            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
269#endif
270};
271
272class ItbPageFault : public MipsFault<ItbPageFault>
273{
274  public:
275#if FULL_SYSTEM
276    void invoke(ThreadContext * tc,
277            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
278#endif
279};
280
281class ItbInvalidFault : public MipsFault<ItbInvalidFault>
282{
283  public:
284#if FULL_SYSTEM
285    void invoke(ThreadContext * tc,
286            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
287#endif
288};
289
290class TLBModifiedFault : public MipsFault<TLBModifiedFault>
291{
292  public:
293#if FULL_SYSTEM
294    void invoke(ThreadContext * tc,
295            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
296#endif
297};
298
299class DtbInvalidFault : public MipsFault<DtbInvalidFault>
300{
301  public:
302#if FULL_SYSTEM
303    void invoke(ThreadContext * tc,
304            StaticInst::StaticInstPtr inst = nullStaticInstPtr);
305#endif
306};
307
308class FloatEnableFault : public MipsFault<FloatEnableFault> {};
309class ItbMissFault : public MipsFault<ItbMissFault> {};
310class ItbAcvFault : public MipsFault<ItbAcvFault> {};
311class IntegerOverflowFault : public MipsFault<IntegerOverflowFault> {};
312
313class DspStateDisabledFault : public MipsFault<DspStateDisabledFault>
314{
315  public:
316    void invoke(ThreadContext * tc,
317            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
318};
319
320} // namespace MipsISA
321
322#endif // __MIPS_FAULTS_HH__
323