faults.cc revision 8775:1e3ca5d77b53 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Korey Sewell
31 *          Jaidev Patwardhan
32 */
33
34#include "arch/mips/faults.hh"
35#include "arch/mips/pra_constants.hh"
36#include "base/trace.hh"
37#include "cpu/base.hh"
38#include "cpu/thread_context.hh"
39#include "debug/MipsPRA.hh"
40#include "mem/page_table.hh"
41#include "sim/process.hh"
42
43namespace MipsISA
44{
45
46typedef MipsFaultBase::FaultVals FaultVals;
47
48template <> FaultVals MipsFault<SystemCallFault>::vals =
49    { "Syscall", 0x180, ExcCodeSys };
50
51template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
52    { "Reserved Instruction Fault", 0x180, ExcCodeRI };
53
54template <> FaultVals MipsFault<ThreadFault>::vals =
55    { "Thread Fault", 0x180, ExcCodeDummy };
56
57template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
58    { "Integer Overflow Exception", 0x180, ExcCodeOv };
59
60template <> FaultVals MipsFault<TrapFault>::vals =
61    { "Trap", 0x180, ExcCodeTr };
62
63template <> FaultVals MipsFault<BreakpointFault>::vals =
64    { "Breakpoint", 0x180, ExcCodeBp };
65
66template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
67    { "DSP Disabled Fault", 0x180, ExcCodeDummy };
68
69template <> FaultVals MipsFault<MachineCheckFault>::vals =
70    { "Machine Check", 0x180, ExcCodeMCheck };
71
72template <> FaultVals MipsFault<ResetFault>::vals =
73    { "Reset Fault", 0x000, ExcCodeDummy };
74
75template <> FaultVals MipsFault<SoftResetFault>::vals =
76    { "Soft Reset Fault", 0x000, ExcCodeDummy };
77
78template <> FaultVals MipsFault<NonMaskableInterrupt>::vals =
79    { "Non Maskable Interrupt", 0x000, ExcCodeDummy };
80
81template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
82    { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU };
83
84template <> FaultVals MipsFault<InterruptFault>::vals =
85    { "Interrupt", 0x000, ExcCodeInt };
86
87template <> FaultVals MipsFault<AddressErrorFault>::vals =
88    { "Address Error", 0x180, ExcCodeDummy };
89
90template <> FaultVals MipsFault<TlbInvalidFault>::vals =
91    { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
92
93template <> FaultVals MipsFault<TlbRefillFault>::vals =
94    { "TLB Refill Exception", 0x180, ExcCodeDummy };
95
96template <> FaultVals MipsFault<TlbModifiedFault>::vals =
97    { "TLB Modified Exception", 0x180, ExcCodeMod };
98
99void
100MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
101{
102    // modify SRS Ctl - Save CSS, put ESS into CSS
103    StatusReg status = tc->readMiscReg(MISCREG_STATUS);
104    if (status.exl != 1 && status.bev != 1) {
105        // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
106        SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
107        srsCtl.pss = srsCtl.css;
108        srsCtl.css = srsCtl.ess;
109        tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
110    }
111
112    // set EXL bit (don't care if it is already set!)
113    status.exl = 1;
114    tc->setMiscRegNoEffect(MISCREG_STATUS, status);
115
116    // write EPC
117    PCState pc = tc->pcState();
118    DPRINTF(MipsPRA, "PC: %s\n", pc);
119    bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
120    tc->setMiscRegNoEffect(MISCREG_EPC,
121            pc.pc() - delay_slot ? sizeof(MachInst) : 0);
122
123    // Set Cause_EXCCODE field
124    CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
125    cause.excCode = excCode;
126    cause.bd = delay_slot ? 1 : 0;
127    cause.ce = 0;
128    tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
129}
130
131void
132MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
133{
134    if (FullSystem) {
135        DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
136        setExceptionState(tc, code());
137        tc->pcState(vect(tc));
138    } else {
139        panic("Fault %s encountered.\n", name());
140    }
141}
142
143void
144ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
145{
146    if (FullSystem) {
147        DPRINTF(MipsPRA, "%s encountered.\n", name());
148        /* All reset activity must be invoked from here */
149        Addr handler = vect(tc);
150        tc->pcState(handler);
151        DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
152    }
153
154    // Set Coprocessor 1 (Floating Point) To Usable
155    StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
156    status.cu.cu1 = 1;
157    tc->setMiscReg(MISCREG_STATUS, status);
158}
159
160void
161SoftResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
162{
163    panic("Soft reset not implemented.\n");
164}
165
166void
167NonMaskableInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
168{
169    panic("Non maskable interrupt not implemented.\n");
170}
171
172} // namespace MipsISA
173
174