faults.cc revision 8574 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Korey Sewell
31 *          Jaidev Patwardhan
32 */
33
34#include "arch/mips/faults.hh"
35#include "arch/mips/pra_constants.hh"
36#include "base/trace.hh"
37#include "cpu/base.hh"
38#include "cpu/thread_context.hh"
39#include "debug/MipsPRA.hh"
40
41#if !FULL_SYSTEM
42#include "mem/page_table.hh"
43#include "sim/process.hh"
44#endif
45
46namespace MipsISA
47{
48
49typedef MipsFaultBase::FaultVals FaultVals;
50
51template <> FaultVals MipsFault<MachineCheckFault>::vals =
52    { "Machine Check", 0x0401 };
53
54template <> FaultVals MipsFault<ResetFault>::vals =
55#if  FULL_SYSTEM
56    { "Reset Fault", 0xBFC00000};
57#else
58    { "Reset Fault", 0x001};
59#endif
60
61template <> FaultVals MipsFault<AddressErrorFault>::vals =
62    { "Address Error", 0x0180 };
63
64template <> FaultVals MipsFault<SystemCallFault>::vals =
65    { "Syscall", 0x0180 };
66
67template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
68    { "Coprocessor Unusable Fault", 0x180 };
69
70template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
71    { "Reserved Instruction Fault", 0x0180 };
72
73template <> FaultVals MipsFault<ThreadFault>::vals =
74    { "Thread Fault", 0x00F1 };
75
76template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
77    { "Integer Overflow Exception", 0x180 };
78
79template <> FaultVals MipsFault<InterruptFault>::vals =
80    { "interrupt", 0x0180 };
81
82template <> FaultVals MipsFault<TrapFault>::vals =
83    { "Trap", 0x0180 };
84
85template <> FaultVals MipsFault<BreakpointFault>::vals =
86    { "Breakpoint", 0x0180 };
87
88template <> FaultVals MipsFault<TlbInvalidFault>::vals =
89    { "Invalid TLB Entry Exception", 0x0180 };
90
91template <> FaultVals MipsFault<TlbRefillFault>::vals =
92    { "TLB Refill Exception", 0x0180 };
93
94template <> FaultVals MipsFault<TLBModifiedFault>::vals =
95    { "TLB Modified Exception", 0x0180 };
96
97template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
98    { "DSP Disabled Fault", 0x001a };
99
100void
101MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
102{
103    // modify SRS Ctl - Save CSS, put ESS into CSS
104    StatusReg status = tc->readMiscReg(MISCREG_STATUS);
105    if (status.exl != 1 && status.bev != 1) {
106        // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
107        SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
108        srsCtl.pss = srsCtl.css;
109        srsCtl.css = srsCtl.ess;
110        tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
111    }
112
113    // set EXL bit (don't care if it is already set!)
114    status.exl = 1;
115    tc->setMiscRegNoEffect(MISCREG_STATUS, status);
116
117    // write EPC
118    PCState pc = tc->pcState();
119    DPRINTF(MipsPRA, "PC: %s\n", pc);
120    bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
121    tc->setMiscRegNoEffect(MISCREG_EPC,
122            pc.pc() - delay_slot ? sizeof(MachInst) : 0);
123
124    // Set Cause_EXCCODE field
125    CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
126    cause.excCode = excCode;
127    cause.bd = delay_slot ? 1 : 0;
128    cause.ce = 0;
129    tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
130}
131
132#if FULL_SYSTEM
133void
134MipsFaultBase::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
135{
136    tc->setPC(HandlerBase);
137    tc->setNextPC(HandlerBase + sizeof(MachInst));
138    tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst));
139}
140
141void
142IntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst)
143{
144    DPRINTF(MipsPRA, "%s encountered.\n", name());
145    setExceptionState(tc, 0xC);
146
147    // Set new PC
148    Addr HandlerBase;
149    StatusReg status = tc->readMiscReg(MISCREG_STATUS);
150    // Here, the handler is dependent on BEV, which is not modified by
151    // setExceptionState()
152    if (!status.bev) {
153        // See MIPS ARM Vol 3, Revision 2, Page 38
154        HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
155    } else {
156        HandlerBase = 0xBFC00200;
157    }
158    setHandlerPC(HandlerBase, tc);
159}
160
161void
162TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst)
163{
164    DPRINTF(MipsPRA, "%s encountered.\n", name());
165    setExceptionState(tc, 0xD);
166
167    // Set new PC
168    Addr HandlerBase;
169    // Offset 0x180 - General Exception Vector
170    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
171    setHandlerPC(HandlerBase, tc);
172}
173
174void
175BreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst)
176{
177    setExceptionState(tc, 0x9);
178
179    // Set new PC
180    Addr HandlerBase;
181    // Offset 0x180 - General Exception Vector
182    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
183    setHandlerPC(HandlerBase, tc);
184}
185
186void
187TlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
188{
189    DPRINTF(MipsPRA, "%s encountered.\n", name());
190    setExceptionState(tc, store ? 0x3 : 0x2);
191
192    tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
193    EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
194    entryHi.asid = entryHiAsid;
195    entryHi.vpn2 = entryHiVPN2;
196    entryHi.vpn2x = entryHiVPN2X;
197    tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
198
199    ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
200    context.badVPN2 = contextBadVPN2;
201    tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
202
203    // Set new PC
204    Addr HandlerBase;
205    // Offset 0x180 - General Exception Vector
206    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
207    setHandlerPC(HandlerBase, tc);
208}
209
210void
211AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
212{
213    DPRINTF(MipsPRA, "%s encountered.\n", name());
214    setExceptionState(tc, store ? 0x5 : 0x4);
215    tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
216
217    // Set new PC
218    Addr HandlerBase;
219    // Offset 0x180 - General Exception Vector
220    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
221    setHandlerPC(HandlerBase, tc);
222}
223
224void
225TlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
226{
227    DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
228    setExceptionState(tc, store ? 0x3 : 0x2);
229
230    Addr HandlerBase;
231    tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
232    EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
233    entryHi.asid = entryHiAsid;
234    entryHi.vpn2 = entryHiVPN2;
235    entryHi.vpn2x = entryHiVPN2X;
236    tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
237    ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
238    context.badVPN2 = contextBadVPN2;
239    tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
240
241    StatusReg status = tc->readMiscReg(MISCREG_STATUS);
242    // Since handler depends on EXL bit, must check EXL bit before setting it!!
243    // See MIPS ARM Vol 3, Revision 2, Page 38
244    if (status.exl == 1) {
245        // Offset 0x180 - General Exception Vector
246        HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
247    } else {
248        // Offset 0x000
249        HandlerBase = tc->readMiscReg(MISCREG_EBASE);
250    }
251    setHandlerPC(HandlerBase, tc);
252}
253
254void
255TLBModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst)
256{
257    DPRINTF(MipsPRA, "%s encountered.\n", name());
258    tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
259    EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
260    entryHi.asid = entryHiAsid;
261    entryHi.vpn2 = entryHiVPN2;
262    entryHi.vpn2x = entryHiVPN2X;
263    tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
264
265    ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
266    context.badVPN2 = contextBadVPN2;
267    tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
268
269    // Set new PC
270    Addr HandlerBase;
271    // Offset 0x180 - General Exception Vector
272    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
273    setExceptionState(tc, 0x1);
274    setHandlerPC(HandlerBase, tc);
275
276}
277
278void
279SystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst)
280{
281    DPRINTF(MipsPRA, "%s encountered.\n", name());
282    setExceptionState(tc, 0x8);
283
284    // Set new PC
285    Addr HandlerBase;
286    // Offset 0x180 - General Exception Vector
287    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
288    setHandlerPC(HandlerBase, tc);
289}
290
291void
292InterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst)
293{
294#if  FULL_SYSTEM
295    DPRINTF(MipsPRA, "%s encountered.\n", name());
296    setExceptionState(tc, 0x0A);
297    Addr HandlerBase;
298
299    CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
300    if (cause.iv) {
301        // Offset 200 for release 2
302        HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
303    } else {
304        //Ofset at 180 for release 1
305        HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
306    }
307
308    setHandlerPC(HandlerBase, tc);
309#endif
310}
311
312#endif // FULL_SYSTEM
313
314void
315ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
316{
317#if FULL_SYSTEM
318    DPRINTF(MipsPRA, "%s encountered.\n", name());
319    /* All reset activity must be invoked from here */
320    tc->setPC(vect());
321    tc->setNextPC(vect() + sizeof(MachInst));
322    tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst));
323    DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC());
324#endif
325
326    // Set Coprocessor 1 (Floating Point) To Usable
327    StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
328    status.cu.cu1 = 1;
329    tc->setMiscReg(MISCREG_STATUS, status);
330}
331
332void
333ReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst)
334{
335#if  FULL_SYSTEM
336    DPRINTF(MipsPRA, "%s encountered.\n", name());
337    setExceptionState(tc, 0x0A);
338    Addr HandlerBase;
339    // Offset 0x180 - General Exception Vector
340    HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
341    setHandlerPC(HandlerBase, tc);
342#else
343    panic("%s encountered.\n", name());
344#endif
345}
346
347void
348ThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst)
349{
350    DPRINTF(MipsPRA, "%s encountered.\n", name());
351    panic("%s encountered.\n", name());
352}
353
354void
355DspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst)
356{
357    DPRINTF(MipsPRA, "%s encountered.\n", name());
358    panic("%s encountered.\n", name());
359}
360
361void
362CoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
363{
364#if FULL_SYSTEM
365    DPRINTF(MipsPRA, "%s encountered.\n", name());
366    setExceptionState(tc, 0xb);
367    // The ID of the coprocessor causing the exception is stored in
368    // CoprocessorUnusableFault::coProcID
369    CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
370    cause.ce = coProcID;
371    tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
372
373    Addr HandlerBase;
374    // Offset 0x180 - General Exception Vector
375    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
376    setHandlerPC(HandlerBase, tc);
377
378#else
379    warn("%s (CP%d) encountered.\n", name(), coProcID);
380#endif
381}
382
383} // namespace MipsISA
384
385