faults.cc revision 8578
12689Sktlim@umich.edu/* 22689Sktlim@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 32689Sktlim@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 42689Sktlim@umich.edu * All rights reserved. 52689Sktlim@umich.edu * 62689Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 72689Sktlim@umich.edu * modification, are permitted provided that the following conditions are 82689Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 92689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 102689Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 112689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 122689Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 132689Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 142689Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 152689Sktlim@umich.edu * this software without specific prior written permission. 162689Sktlim@umich.edu * 172689Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182689Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192689Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202689Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212689Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222689Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232689Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242689Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252689Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262689Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272689Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282689Sktlim@umich.edu * 292689Sktlim@umich.edu * Authors: Gabe Black 302290SN/A * Korey Sewell 313368Sstever@eecs.umich.edu * Jaidev Patwardhan 322680Sktlim@umich.edu */ 332290SN/A 342290SN/A#include "arch/mips/faults.hh" 352680Sktlim@umich.edu#include "arch/mips/pra_constants.hh" 362680Sktlim@umich.edu#include "base/trace.hh" 372290SN/A#include "cpu/base.hh" 382290SN/A#include "cpu/thread_context.hh" 392290SN/A#include "debug/MipsPRA.hh" 402290SN/A 412290SN/A#if !FULL_SYSTEM 422290SN/A#include "mem/page_table.hh" 433368Sstever@eecs.umich.edu#include "sim/process.hh" 442680Sktlim@umich.edu#endif 452290SN/A 462290SN/Anamespace MipsISA 472290SN/A{ 485336Shines@cs.fsu.edu 492290SN/Atypedef MipsFaultBase::FaultVals FaultVals; 504873Sstever@eecs.umich.edu 512290SN/Atemplate <> FaultVals MipsFault<SystemCallFault>::vals = 52 { "Syscall", 0x180, ExcCodeSys }; 53 54template <> FaultVals MipsFault<ReservedInstructionFault>::vals = 55 { "Reserved Instruction Fault", 0x180, ExcCodeRI }; 56 57template <> FaultVals MipsFault<ThreadFault>::vals = 58 { "Thread Fault", 0x180, ExcCodeDummy }; 59 60template <> FaultVals MipsFault<IntegerOverflowFault>::vals = 61 { "Integer Overflow Exception", 0x180, ExcCodeOv }; 62 63template <> FaultVals MipsFault<TrapFault>::vals = 64 { "Trap", 0x180, ExcCodeTr }; 65 66template <> FaultVals MipsFault<BreakpointFault>::vals = 67 { "Breakpoint", 0x180, ExcCodeBp }; 68 69template <> FaultVals MipsFault<DspStateDisabledFault>::vals = 70 { "DSP Disabled Fault", 0x180, ExcCodeDummy }; 71 72template <> FaultVals MipsFault<MachineCheckFault>::vals = 73 { "Machine Check", 0x180, ExcCodeMCheck }; 74 75template <> FaultVals MipsFault<ResetFault>::vals = 76 { "Reset Fault", 0x000, ExcCodeDummy }; 77 78template <> FaultVals MipsFault<SoftResetFault>::vals = 79 { "Soft Reset Fault", 0x000, ExcCodeDummy }; 80 81template <> FaultVals MipsFault<NonMaskableInterrupt>::vals = 82 { "Non Maskable Interrupt", 0x000, ExcCodeDummy }; 83 84template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals = 85 { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU }; 86 87template <> FaultVals MipsFault<InterruptFault>::vals = 88 { "Interrupt", 0x000, ExcCodeInt }; 89 90template <> FaultVals MipsFault<AddressErrorFault>::vals = 91 { "Address Error", 0x180, ExcCodeDummy }; 92 93template <> FaultVals MipsFault<TlbInvalidFault>::vals = 94 { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy }; 95 96template <> FaultVals MipsFault<TlbRefillFault>::vals = 97 { "TLB Refill Exception", 0x180, ExcCodeDummy }; 98 99template <> FaultVals MipsFault<TlbModifiedFault>::vals = 100 { "TLB Modified Exception", 0x180, ExcCodeMod }; 101 102void 103MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) 104{ 105 // modify SRS Ctl - Save CSS, put ESS into CSS 106 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 107 if (status.exl != 1 && status.bev != 1) { 108 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 109 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); 110 srsCtl.pss = srsCtl.css; 111 srsCtl.css = srsCtl.ess; 112 tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl); 113 } 114 115 // set EXL bit (don't care if it is already set!) 116 status.exl = 1; 117 tc->setMiscRegNoEffect(MISCREG_STATUS, status); 118 119 // write EPC 120 PCState pc = tc->pcState(); 121 DPRINTF(MipsPRA, "PC: %s\n", pc); 122 bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc(); 123 tc->setMiscRegNoEffect(MISCREG_EPC, 124 pc.pc() - delay_slot ? sizeof(MachInst) : 0); 125 126 // Set Cause_EXCCODE field 127 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 128 cause.excCode = excCode; 129 cause.bd = delay_slot ? 1 : 0; 130 cause.ce = 0; 131 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 132} 133 134void 135MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst) 136{ 137 if (FULL_SYSTEM) { 138 DPRINTF(MipsPRA, "Fault %s encountered.\n", name()); 139 setExceptionState(tc, code()); 140 tc->pcState(vect(tc)); 141 } else { 142 panic("Fault %s encountered.\n", name()); 143 } 144} 145 146void 147ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst) 148{ 149 if (FULL_SYSTEM) { 150 DPRINTF(MipsPRA, "%s encountered.\n", name()); 151 /* All reset activity must be invoked from here */ 152 Addr handler = vect(tc); 153 tc->pcState(handler); 154 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler); 155 } 156 157 // Set Coprocessor 1 (Floating Point) To Usable 158 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 159 status.cu.cu1 = 1; 160 tc->setMiscReg(MISCREG_STATUS, status); 161} 162 163void 164SoftResetFault::invoke(ThreadContext *tc, StaticInstPtr inst) 165{ 166 panic("Soft reset not implemented.\n"); 167} 168 169void 170NonMaskableInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst) 171{ 172 panic("Non maskable interrupt not implemented.\n"); 173} 174 175} // namespace MipsISA 176 177