faults.cc revision 8573
12131SN/A/* 25268Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 52131SN/A * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 162131SN/A * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 295254Sksewell@umich.edu * Authors: Gabe Black 305254Sksewell@umich.edu * Korey Sewell 315222Sksewell@umich.edu * Jaidev Patwardhan 322131SN/A */ 332131SN/A 342239SN/A#include "arch/mips/faults.hh" 357676Snate@binkert.org#include "arch/mips/pra_constants.hh" 367676Snate@binkert.org#include "base/trace.hh" 377676Snate@binkert.org#include "cpu/base.hh" 382680Sktlim@umich.edu#include "cpu/thread_context.hh" 398232Snate@binkert.org#include "debug/MipsPRA.hh" 407676Snate@binkert.org 412800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM 427676Snate@binkert.org#include "mem/page_table.hh" 432800Ssaidi@eecs.umich.edu#include "sim/process.hh" 442800Ssaidi@eecs.umich.edu#endif 452131SN/A 462447SN/Anamespace MipsISA 472447SN/A{ 482131SN/A 498566Sgblack@eecs.umich.edutypedef MipsFaultBase::FaultVals FaultVals; 502131SN/A 518566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<MachineCheckFault>::vals = 528566Sgblack@eecs.umich.edu { "Machine Check", 0x0401 }; 532447SN/A 548566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ResetFault>::vals = 555222Sksewell@umich.edu#if FULL_SYSTEM 568566Sgblack@eecs.umich.edu { "Reset Fault", 0xBFC00000}; 575222Sksewell@umich.edu#else 588566Sgblack@eecs.umich.edu { "Reset Fault", 0x001}; 595222Sksewell@umich.edu#endif 602447SN/A 618566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<AddressErrorFault>::vals = 628566Sgblack@eecs.umich.edu { "Address Error", 0x0180 }; 635222Sksewell@umich.edu 648566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<SystemCallFault>::vals = 658566Sgblack@eecs.umich.edu { "Syscall", 0x0180 }; 665222Sksewell@umich.edu 678566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<CoprocessorUnusableFault>::vals = 688566Sgblack@eecs.umich.edu { "Coprocessor Unusable Fault", 0x180 }; 695222Sksewell@umich.edu 708566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ReservedInstructionFault>::vals = 718566Sgblack@eecs.umich.edu { "Reserved Instruction Fault", 0x0180 }; 724661Sksewell@umich.edu 738566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ThreadFault>::vals = 748566Sgblack@eecs.umich.edu { "Thread Fault", 0x00F1 }; 754661Sksewell@umich.edu 768568Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<IntegerOverflowFault>::vals = 778568Sgblack@eecs.umich.edu { "Integer Overflow Exception", 0x180 }; 782447SN/A 798566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<InterruptFault>::vals = 808566Sgblack@eecs.umich.edu { "interrupt", 0x0180 }; 814661Sksewell@umich.edu 828566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TrapFault>::vals = 838566Sgblack@eecs.umich.edu { "Trap", 0x0180 }; 842447SN/A 858566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<BreakpointFault>::vals = 868566Sgblack@eecs.umich.edu { "Breakpoint", 0x0180 }; 875222Sksewell@umich.edu 888573Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TlbInvalidFault>::vals = 898573Sgblack@eecs.umich.edu { "Invalid TLB Entry Exception", 0x0180 }; 905222Sksewell@umich.edu 918573Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TlbRefillFault>::vals = 928573Sgblack@eecs.umich.edu { "TLB Refill Exception", 0x0180 }; 932447SN/A 948566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TLBModifiedFault>::vals = 958566Sgblack@eecs.umich.edu { "TLB Modified Exception", 0x0180 }; 962447SN/A 978566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<DspStateDisabledFault>::vals = 988566Sgblack@eecs.umich.edu { "DSP Disabled Fault", 0x001a }; 994661Sksewell@umich.edu 1005222Sksewell@umich.edu#if FULL_SYSTEM 1016378Sgblack@eecs.umich.eduvoid 1028566Sgblack@eecs.umich.eduMipsFaultBase::setHandlerPC(Addr HandlerBase, ThreadContext *tc) 1035222Sksewell@umich.edu{ 1046378Sgblack@eecs.umich.edu tc->setPC(HandlerBase); 1056378Sgblack@eecs.umich.edu tc->setNextPC(HandlerBase + sizeof(MachInst)); 1066378Sgblack@eecs.umich.edu tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst)); 1075222Sksewell@umich.edu} 1085222Sksewell@umich.edu 1096378Sgblack@eecs.umich.eduvoid 1108566Sgblack@eecs.umich.eduMipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) 1115222Sksewell@umich.edu{ 1126378Sgblack@eecs.umich.edu // modify SRS Ctl - Save CSS, put ESS into CSS 1136383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 1146379Sgblack@eecs.umich.edu if (status.exl != 1 && status.bev != 1) { 1156378Sgblack@eecs.umich.edu // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 1166383Sgblack@eecs.umich.edu SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); 1176379Sgblack@eecs.umich.edu srsCtl.pss = srsCtl.css; 1186379Sgblack@eecs.umich.edu srsCtl.css = srsCtl.ess; 1196383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl); 1205222Sksewell@umich.edu } 1215222Sksewell@umich.edu 1226378Sgblack@eecs.umich.edu // set EXL bit (don't care if it is already set!) 1236379Sgblack@eecs.umich.edu status.exl = 1; 1246383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_STATUS, status); 1255222Sksewell@umich.edu 1266378Sgblack@eecs.umich.edu // write EPC 1276378Sgblack@eecs.umich.edu // CHECK ME or FIXME or FIX ME or POSSIBLE HACK 1286378Sgblack@eecs.umich.edu // Check to see if the exception occurred in the branch delay slot 1296378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "PC: %x, NextPC: %x, NNPC: %x\n", 1306378Sgblack@eecs.umich.edu tc->readPC(), tc->readNextPC(), tc->readNextNPC()); 1316379Sgblack@eecs.umich.edu int bd = 0; 1326378Sgblack@eecs.umich.edu if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) { 1336383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC() - sizeof(MachInst)); 1346378Sgblack@eecs.umich.edu // In the branch delay slot? set CAUSE_31 1356379Sgblack@eecs.umich.edu bd = 1; 1366378Sgblack@eecs.umich.edu } else { 1376383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC()); 1386378Sgblack@eecs.umich.edu // In the branch delay slot? reset CAUSE_31 1396379Sgblack@eecs.umich.edu bd = 0; 1406378Sgblack@eecs.umich.edu } 1415222Sksewell@umich.edu 1426378Sgblack@eecs.umich.edu // Set Cause_EXCCODE field 1436383Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 1446379Sgblack@eecs.umich.edu cause.excCode = excCode; 1456379Sgblack@eecs.umich.edu cause.bd = bd; 1466379Sgblack@eecs.umich.edu cause.ce = 0; 1476383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 1486378Sgblack@eecs.umich.edu} 1496378Sgblack@eecs.umich.edu 1506378Sgblack@eecs.umich.eduvoid 1518568Sgblack@eecs.umich.eduIntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1526378Sgblack@eecs.umich.edu{ 1536378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 1546378Sgblack@eecs.umich.edu setExceptionState(tc, 0xC); 1556378Sgblack@eecs.umich.edu 1566378Sgblack@eecs.umich.edu // Set new PC 1576378Sgblack@eecs.umich.edu Addr HandlerBase; 1586383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 1596378Sgblack@eecs.umich.edu // Here, the handler is dependent on BEV, which is not modified by 1606378Sgblack@eecs.umich.edu // setExceptionState() 1616379Sgblack@eecs.umich.edu if (!status.bev) { 1626378Sgblack@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 1636383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 1646378Sgblack@eecs.umich.edu } else { 1656378Sgblack@eecs.umich.edu HandlerBase = 0xBFC00200; 1666378Sgblack@eecs.umich.edu } 1676378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 1686378Sgblack@eecs.umich.edu} 1696378Sgblack@eecs.umich.edu 1706378Sgblack@eecs.umich.eduvoid 1717678Sgblack@eecs.umich.eduTrapFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1726378Sgblack@eecs.umich.edu{ 1736378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 1746378Sgblack@eecs.umich.edu setExceptionState(tc, 0xD); 1756378Sgblack@eecs.umich.edu 1766378Sgblack@eecs.umich.edu // Set new PC 1776378Sgblack@eecs.umich.edu Addr HandlerBase; 1786378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 1796383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 1806378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 1816378Sgblack@eecs.umich.edu} 1826378Sgblack@eecs.umich.edu 1836378Sgblack@eecs.umich.eduvoid 1847678Sgblack@eecs.umich.eduBreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1856378Sgblack@eecs.umich.edu{ 1866378Sgblack@eecs.umich.edu setExceptionState(tc, 0x9); 1876378Sgblack@eecs.umich.edu 1886378Sgblack@eecs.umich.edu // Set new PC 1896378Sgblack@eecs.umich.edu Addr HandlerBase; 1906378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 1916383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 1926378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 1936378Sgblack@eecs.umich.edu} 1946378Sgblack@eecs.umich.edu 1956378Sgblack@eecs.umich.eduvoid 1968573Sgblack@eecs.umich.eduTlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1976378Sgblack@eecs.umich.edu{ 1986378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 1998573Sgblack@eecs.umich.edu setExceptionState(tc, store ? 0x3 : 0x2); 2006378Sgblack@eecs.umich.edu 2016383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2026383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2036379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 2046379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2056379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 2066383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2076379Sgblack@eecs.umich.edu 2086383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2096379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2106383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2116378Sgblack@eecs.umich.edu 2126378Sgblack@eecs.umich.edu // Set new PC 2136378Sgblack@eecs.umich.edu Addr HandlerBase; 2146378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2156383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2166379Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2176378Sgblack@eecs.umich.edu} 2186378Sgblack@eecs.umich.edu 2196378Sgblack@eecs.umich.eduvoid 2207678Sgblack@eecs.umich.eduAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2216378Sgblack@eecs.umich.edu{ 2226378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2238570Sgblack@eecs.umich.edu setExceptionState(tc, store ? 0x5 : 0x4); 2248570Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr); 2256378Sgblack@eecs.umich.edu 2266378Sgblack@eecs.umich.edu // Set new PC 2276378Sgblack@eecs.umich.edu Addr HandlerBase; 2286378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2296383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2306378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2316378Sgblack@eecs.umich.edu} 2326378Sgblack@eecs.umich.edu 2336378Sgblack@eecs.umich.eduvoid 2348573Sgblack@eecs.umich.eduTlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2356378Sgblack@eecs.umich.edu{ 2366383Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR); 2378573Sgblack@eecs.umich.edu setExceptionState(tc, store ? 0x3 : 0x2); 2388573Sgblack@eecs.umich.edu 2396378Sgblack@eecs.umich.edu Addr HandlerBase; 2406383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2416383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2426379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 2436379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2446379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 2456383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2466383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2476379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2486383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2496378Sgblack@eecs.umich.edu 2506383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 2516378Sgblack@eecs.umich.edu // Since handler depends on EXL bit, must check EXL bit before setting it!! 2526378Sgblack@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 2536379Sgblack@eecs.umich.edu if (status.exl == 1) { 2546378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2556383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2566378Sgblack@eecs.umich.edu } else { 2576378Sgblack@eecs.umich.edu // Offset 0x000 2586383Sgblack@eecs.umich.edu HandlerBase = tc->readMiscReg(MISCREG_EBASE); 2596378Sgblack@eecs.umich.edu } 2606378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2616378Sgblack@eecs.umich.edu} 2626378Sgblack@eecs.umich.edu 2636378Sgblack@eecs.umich.eduvoid 2647678Sgblack@eecs.umich.eduTLBModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2656378Sgblack@eecs.umich.edu{ 2666378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2676383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2686383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2696379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 2706379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2716379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 2726383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2736379Sgblack@eecs.umich.edu 2746383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2756379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2766383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2776378Sgblack@eecs.umich.edu 2786378Sgblack@eecs.umich.edu // Set new PC 2796378Sgblack@eecs.umich.edu Addr HandlerBase; 2806378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2816383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2826378Sgblack@eecs.umich.edu setExceptionState(tc, 0x1); 2836378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2845222Sksewell@umich.edu 2855222Sksewell@umich.edu} 2865222Sksewell@umich.edu 2876378Sgblack@eecs.umich.eduvoid 2887678Sgblack@eecs.umich.eduSystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2895222Sksewell@umich.edu{ 2906378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2916378Sgblack@eecs.umich.edu setExceptionState(tc, 0x8); 2925222Sksewell@umich.edu 2936378Sgblack@eecs.umich.edu // Set new PC 2946378Sgblack@eecs.umich.edu Addr HandlerBase; 2956378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2966383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2976378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2985222Sksewell@umich.edu} 2995222Sksewell@umich.edu 3006378Sgblack@eecs.umich.eduvoid 3017678Sgblack@eecs.umich.eduInterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3025222Sksewell@umich.edu{ 3035222Sksewell@umich.edu#if FULL_SYSTEM 3046378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3056378Sgblack@eecs.umich.edu setExceptionState(tc, 0x0A); 3066378Sgblack@eecs.umich.edu Addr HandlerBase; 3075222Sksewell@umich.edu 3086383Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); 3096379Sgblack@eecs.umich.edu if (cause.iv) { 3106378Sgblack@eecs.umich.edu // Offset 200 for release 2 3116383Sgblack@eecs.umich.edu HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 3126378Sgblack@eecs.umich.edu } else { 3136378Sgblack@eecs.umich.edu //Ofset at 180 for release 1 3146383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 3156378Sgblack@eecs.umich.edu } 3165222Sksewell@umich.edu 3176378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3185222Sksewell@umich.edu#endif 3195222Sksewell@umich.edu} 3205222Sksewell@umich.edu 3215222Sksewell@umich.edu#endif // FULL_SYSTEM 3225222Sksewell@umich.edu 3236378Sgblack@eecs.umich.eduvoid 3247678Sgblack@eecs.umich.eduResetFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3254661Sksewell@umich.edu{ 3265224Sksewell@umich.edu#if FULL_SYSTEM 3276378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3286378Sgblack@eecs.umich.edu /* All reset activity must be invoked from here */ 3296378Sgblack@eecs.umich.edu tc->setPC(vect()); 3306378Sgblack@eecs.umich.edu tc->setNextPC(vect() + sizeof(MachInst)); 3316378Sgblack@eecs.umich.edu tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst)); 3326379Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC()); 3335224Sksewell@umich.edu#endif 3345224Sksewell@umich.edu 3356378Sgblack@eecs.umich.edu // Set Coprocessor 1 (Floating Point) To Usable 3366383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 3376379Sgblack@eecs.umich.edu status.cu.cu1 = 1; 3386383Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_STATUS, status); 3395222Sksewell@umich.edu} 3405222Sksewell@umich.edu 3416378Sgblack@eecs.umich.eduvoid 3427678Sgblack@eecs.umich.eduReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3435222Sksewell@umich.edu{ 3445222Sksewell@umich.edu#if FULL_SYSTEM 3456378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3466378Sgblack@eecs.umich.edu setExceptionState(tc, 0x0A); 3476378Sgblack@eecs.umich.edu Addr HandlerBase; 3486378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3496383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 3506378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3515222Sksewell@umich.edu#else 3525222Sksewell@umich.edu panic("%s encountered.\n", name()); 3535222Sksewell@umich.edu#endif 3545222Sksewell@umich.edu} 3555222Sksewell@umich.edu 3566378Sgblack@eecs.umich.eduvoid 3577678Sgblack@eecs.umich.eduThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3585222Sksewell@umich.edu{ 3596378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3606378Sgblack@eecs.umich.edu panic("%s encountered.\n", name()); 3615222Sksewell@umich.edu} 3625222Sksewell@umich.edu 3636378Sgblack@eecs.umich.eduvoid 3647678Sgblack@eecs.umich.eduDspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3655222Sksewell@umich.edu{ 3666378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3676378Sgblack@eecs.umich.edu panic("%s encountered.\n", name()); 3684661Sksewell@umich.edu} 3694661Sksewell@umich.edu 3706378Sgblack@eecs.umich.eduvoid 3717678Sgblack@eecs.umich.eduCoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3724661Sksewell@umich.edu{ 3735222Sksewell@umich.edu#if FULL_SYSTEM 3746378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3756378Sgblack@eecs.umich.edu setExceptionState(tc, 0xb); 3766378Sgblack@eecs.umich.edu // The ID of the coprocessor causing the exception is stored in 3776378Sgblack@eecs.umich.edu // CoprocessorUnusableFault::coProcID 3786383Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 3796379Sgblack@eecs.umich.edu cause.ce = coProcID; 3806383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 3814661Sksewell@umich.edu 3826378Sgblack@eecs.umich.edu Addr HandlerBase; 3836378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3846383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 3856378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3864661Sksewell@umich.edu 3875222Sksewell@umich.edu#else 3885224Sksewell@umich.edu warn("%s (CP%d) encountered.\n", name(), coProcID); 3895222Sksewell@umich.edu#endif 3904661Sksewell@umich.edu} 3914661Sksewell@umich.edu 3922447SN/A} // namespace MipsISA 3932447SN/A 394