faults.cc revision 8568
12131SN/A/* 25268Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 52131SN/A * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 162131SN/A * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 295254Sksewell@umich.edu * Authors: Gabe Black 305254Sksewell@umich.edu * Korey Sewell 315222Sksewell@umich.edu * Jaidev Patwardhan 322131SN/A */ 332131SN/A 342239SN/A#include "arch/mips/faults.hh" 357676Snate@binkert.org#include "arch/mips/pra_constants.hh" 367676Snate@binkert.org#include "base/trace.hh" 377676Snate@binkert.org#include "cpu/base.hh" 382680Sktlim@umich.edu#include "cpu/thread_context.hh" 398232Snate@binkert.org#include "debug/MipsPRA.hh" 407676Snate@binkert.org 412800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM 427676Snate@binkert.org#include "mem/page_table.hh" 432800Ssaidi@eecs.umich.edu#include "sim/process.hh" 442800Ssaidi@eecs.umich.edu#endif 452131SN/A 462447SN/Anamespace MipsISA 472447SN/A{ 482131SN/A 498566Sgblack@eecs.umich.edutypedef MipsFaultBase::FaultVals FaultVals; 502131SN/A 518566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<MachineCheckFault>::vals = 528566Sgblack@eecs.umich.edu { "Machine Check", 0x0401 }; 532447SN/A 548566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ResetFault>::vals = 555222Sksewell@umich.edu#if FULL_SYSTEM 568566Sgblack@eecs.umich.edu { "Reset Fault", 0xBFC00000}; 575222Sksewell@umich.edu#else 588566Sgblack@eecs.umich.edu { "Reset Fault", 0x001}; 595222Sksewell@umich.edu#endif 602447SN/A 618566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<AddressErrorFault>::vals = 628566Sgblack@eecs.umich.edu { "Address Error", 0x0180 }; 635222Sksewell@umich.edu 648566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<StoreAddressErrorFault>::vals = 658566Sgblack@eecs.umich.edu { "Store Address Error", 0x0180 }; 665222Sksewell@umich.edu 678566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<SystemCallFault>::vals = 688566Sgblack@eecs.umich.edu { "Syscall", 0x0180 }; 695222Sksewell@umich.edu 708566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<CoprocessorUnusableFault>::vals = 718566Sgblack@eecs.umich.edu { "Coprocessor Unusable Fault", 0x180 }; 725222Sksewell@umich.edu 738566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ReservedInstructionFault>::vals = 748566Sgblack@eecs.umich.edu { "Reserved Instruction Fault", 0x0180 }; 754661Sksewell@umich.edu 768566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ThreadFault>::vals = 778566Sgblack@eecs.umich.edu { "Thread Fault", 0x00F1 }; 784661Sksewell@umich.edu 798568Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<IntegerOverflowFault>::vals = 808568Sgblack@eecs.umich.edu { "Integer Overflow Exception", 0x180 }; 812447SN/A 828566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<InterruptFault>::vals = 838566Sgblack@eecs.umich.edu { "interrupt", 0x0180 }; 844661Sksewell@umich.edu 858566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TrapFault>::vals = 868566Sgblack@eecs.umich.edu { "Trap", 0x0180 }; 872447SN/A 888566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<BreakpointFault>::vals = 898566Sgblack@eecs.umich.edu { "Breakpoint", 0x0180 }; 905222Sksewell@umich.edu 918566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ItbInvalidFault>::vals = 928566Sgblack@eecs.umich.edu { "Invalid TLB Entry Exception (I-Fetch/LW)", 0x0180 }; 935222Sksewell@umich.edu 948566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ItbRefillFault>::vals = 958566Sgblack@eecs.umich.edu { "TLB Refill Exception (I-Fetch/LW)", 0x0180 }; 965222Sksewell@umich.edu 978566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<DtbInvalidFault>::vals = 988566Sgblack@eecs.umich.edu { "Invalid TLB Entry Exception (Store)", 0x0180 }; 992447SN/A 1008566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<DtbRefillFault>::vals = 1018566Sgblack@eecs.umich.edu { "TLB Refill Exception (Store)", 0x0180 }; 1022447SN/A 1038566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TLBModifiedFault>::vals = 1048566Sgblack@eecs.umich.edu { "TLB Modified Exception", 0x0180 }; 1052447SN/A 1068566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<DspStateDisabledFault>::vals = 1078566Sgblack@eecs.umich.edu { "DSP Disabled Fault", 0x001a }; 1084661Sksewell@umich.edu 1095222Sksewell@umich.edu#if FULL_SYSTEM 1106378Sgblack@eecs.umich.eduvoid 1118566Sgblack@eecs.umich.eduMipsFaultBase::setHandlerPC(Addr HandlerBase, ThreadContext *tc) 1125222Sksewell@umich.edu{ 1136378Sgblack@eecs.umich.edu tc->setPC(HandlerBase); 1146378Sgblack@eecs.umich.edu tc->setNextPC(HandlerBase + sizeof(MachInst)); 1156378Sgblack@eecs.umich.edu tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst)); 1165222Sksewell@umich.edu} 1175222Sksewell@umich.edu 1186378Sgblack@eecs.umich.eduvoid 1198566Sgblack@eecs.umich.eduMipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) 1205222Sksewell@umich.edu{ 1216378Sgblack@eecs.umich.edu // modify SRS Ctl - Save CSS, put ESS into CSS 1226383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 1236379Sgblack@eecs.umich.edu if (status.exl != 1 && status.bev != 1) { 1246378Sgblack@eecs.umich.edu // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 1256383Sgblack@eecs.umich.edu SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); 1266379Sgblack@eecs.umich.edu srsCtl.pss = srsCtl.css; 1276379Sgblack@eecs.umich.edu srsCtl.css = srsCtl.ess; 1286383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl); 1295222Sksewell@umich.edu } 1305222Sksewell@umich.edu 1316378Sgblack@eecs.umich.edu // set EXL bit (don't care if it is already set!) 1326379Sgblack@eecs.umich.edu status.exl = 1; 1336383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_STATUS, status); 1345222Sksewell@umich.edu 1356378Sgblack@eecs.umich.edu // write EPC 1366378Sgblack@eecs.umich.edu // CHECK ME or FIXME or FIX ME or POSSIBLE HACK 1376378Sgblack@eecs.umich.edu // Check to see if the exception occurred in the branch delay slot 1386378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "PC: %x, NextPC: %x, NNPC: %x\n", 1396378Sgblack@eecs.umich.edu tc->readPC(), tc->readNextPC(), tc->readNextNPC()); 1406379Sgblack@eecs.umich.edu int bd = 0; 1416378Sgblack@eecs.umich.edu if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) { 1426383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC() - sizeof(MachInst)); 1436378Sgblack@eecs.umich.edu // In the branch delay slot? set CAUSE_31 1446379Sgblack@eecs.umich.edu bd = 1; 1456378Sgblack@eecs.umich.edu } else { 1466383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC()); 1476378Sgblack@eecs.umich.edu // In the branch delay slot? reset CAUSE_31 1486379Sgblack@eecs.umich.edu bd = 0; 1496378Sgblack@eecs.umich.edu } 1505222Sksewell@umich.edu 1516378Sgblack@eecs.umich.edu // Set Cause_EXCCODE field 1526383Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 1536379Sgblack@eecs.umich.edu cause.excCode = excCode; 1546379Sgblack@eecs.umich.edu cause.bd = bd; 1556379Sgblack@eecs.umich.edu cause.ce = 0; 1566383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 1576378Sgblack@eecs.umich.edu} 1586378Sgblack@eecs.umich.edu 1596378Sgblack@eecs.umich.eduvoid 1608568Sgblack@eecs.umich.eduIntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1616378Sgblack@eecs.umich.edu{ 1626378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 1636378Sgblack@eecs.umich.edu setExceptionState(tc, 0xC); 1646378Sgblack@eecs.umich.edu 1656378Sgblack@eecs.umich.edu // Set new PC 1666378Sgblack@eecs.umich.edu Addr HandlerBase; 1676383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 1686378Sgblack@eecs.umich.edu // Here, the handler is dependent on BEV, which is not modified by 1696378Sgblack@eecs.umich.edu // setExceptionState() 1706379Sgblack@eecs.umich.edu if (!status.bev) { 1716378Sgblack@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 1726383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 1736378Sgblack@eecs.umich.edu } else { 1746378Sgblack@eecs.umich.edu HandlerBase = 0xBFC00200; 1756378Sgblack@eecs.umich.edu } 1766378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 1776378Sgblack@eecs.umich.edu} 1786378Sgblack@eecs.umich.edu 1796378Sgblack@eecs.umich.eduvoid 1807678Sgblack@eecs.umich.eduStoreAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1816378Sgblack@eecs.umich.edu{ 1826378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 1836378Sgblack@eecs.umich.edu setExceptionState(tc, 0x5); 1846383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 1856378Sgblack@eecs.umich.edu 1866378Sgblack@eecs.umich.edu // Set new PC 1876378Sgblack@eecs.umich.edu Addr HandlerBase; 1886378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 1896383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 1906378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 1916378Sgblack@eecs.umich.edu} 1926378Sgblack@eecs.umich.edu 1936378Sgblack@eecs.umich.eduvoid 1947678Sgblack@eecs.umich.eduTrapFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1956378Sgblack@eecs.umich.edu{ 1966378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 1976378Sgblack@eecs.umich.edu setExceptionState(tc, 0xD); 1986378Sgblack@eecs.umich.edu 1996378Sgblack@eecs.umich.edu // Set new PC 2006378Sgblack@eecs.umich.edu Addr HandlerBase; 2016378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2026383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2036378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2046378Sgblack@eecs.umich.edu} 2056378Sgblack@eecs.umich.edu 2066378Sgblack@eecs.umich.eduvoid 2077678Sgblack@eecs.umich.eduBreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2086378Sgblack@eecs.umich.edu{ 2096378Sgblack@eecs.umich.edu setExceptionState(tc, 0x9); 2106378Sgblack@eecs.umich.edu 2116378Sgblack@eecs.umich.edu // Set new PC 2126378Sgblack@eecs.umich.edu Addr HandlerBase; 2136378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2146383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2156378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2166378Sgblack@eecs.umich.edu} 2176378Sgblack@eecs.umich.edu 2186378Sgblack@eecs.umich.eduvoid 2197678Sgblack@eecs.umich.eduDtbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2206378Sgblack@eecs.umich.edu{ 2216378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2226378Sgblack@eecs.umich.edu 2236383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2246383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2256379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 2266379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2276379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 2286383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2296379Sgblack@eecs.umich.edu 2306383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2316379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2326383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2336378Sgblack@eecs.umich.edu setExceptionState(tc, 0x3); 2346378Sgblack@eecs.umich.edu 2356378Sgblack@eecs.umich.edu 2366378Sgblack@eecs.umich.edu // Set new PC 2376378Sgblack@eecs.umich.edu Addr HandlerBase; 2386378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2396383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2406379Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2416378Sgblack@eecs.umich.edu} 2426378Sgblack@eecs.umich.edu 2436378Sgblack@eecs.umich.eduvoid 2447678Sgblack@eecs.umich.eduAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2456378Sgblack@eecs.umich.edu{ 2466378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2476378Sgblack@eecs.umich.edu setExceptionState(tc, 0x4); 2486383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2496378Sgblack@eecs.umich.edu 2506378Sgblack@eecs.umich.edu // Set new PC 2516378Sgblack@eecs.umich.edu Addr HandlerBase; 2526378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2536383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2546378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2556378Sgblack@eecs.umich.edu} 2566378Sgblack@eecs.umich.edu 2576378Sgblack@eecs.umich.eduvoid 2587678Sgblack@eecs.umich.eduItbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2596378Sgblack@eecs.umich.edu{ 2606378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2616378Sgblack@eecs.umich.edu setExceptionState(tc, 0x2); 2626383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2636383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2646379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 2656379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2666379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 2676383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2686379Sgblack@eecs.umich.edu 2696383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2706379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2716383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2726378Sgblack@eecs.umich.edu 2736378Sgblack@eecs.umich.edu 2746378Sgblack@eecs.umich.edu // Set new PC 2756378Sgblack@eecs.umich.edu Addr HandlerBase; 2766378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2776383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2786378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase,tc); 2796379Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n", 2806383Sgblack@eecs.umich.edu HandlerBase, tc->readMiscReg(MISCREG_EPC)); 2816378Sgblack@eecs.umich.edu} 2826378Sgblack@eecs.umich.edu 2836378Sgblack@eecs.umich.eduvoid 2847678Sgblack@eecs.umich.eduItbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2856378Sgblack@eecs.umich.edu{ 2866383Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR); 2876378Sgblack@eecs.umich.edu Addr HandlerBase; 2886383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2896383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2906379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 2916379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2926379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 2936383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2946383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2956379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2966383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2976378Sgblack@eecs.umich.edu 2986383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 2996378Sgblack@eecs.umich.edu // Since handler depends on EXL bit, must check EXL bit before setting it!! 3006378Sgblack@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 3016379Sgblack@eecs.umich.edu if (status.exl == 1) { 3026378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3036383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 3046378Sgblack@eecs.umich.edu } else { 3056378Sgblack@eecs.umich.edu // Offset 0x000 3066383Sgblack@eecs.umich.edu HandlerBase = tc->readMiscReg(MISCREG_EBASE); 3076378Sgblack@eecs.umich.edu } 3086378Sgblack@eecs.umich.edu 3096378Sgblack@eecs.umich.edu setExceptionState(tc, 0x2); 3106378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3116378Sgblack@eecs.umich.edu} 3126378Sgblack@eecs.umich.edu 3136378Sgblack@eecs.umich.eduvoid 3147678Sgblack@eecs.umich.eduDtbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3156378Sgblack@eecs.umich.edu{ 3166378Sgblack@eecs.umich.edu // Set new PC 3176378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3186378Sgblack@eecs.umich.edu Addr HandlerBase; 3196383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 3206383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 3216379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 3226379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 3236379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 3246383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 3256378Sgblack@eecs.umich.edu 3266383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 3276379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 3286383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 3296379Sgblack@eecs.umich.edu 3306383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 3316378Sgblack@eecs.umich.edu // Since handler depends on EXL bit, must check EXL bit before setting it!! 3326378Sgblack@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 3336379Sgblack@eecs.umich.edu if (status.exl) { 3346378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3356383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 3366378Sgblack@eecs.umich.edu } else { 3376378Sgblack@eecs.umich.edu // Offset 0x000 3386383Sgblack@eecs.umich.edu HandlerBase = tc->readMiscReg(MISCREG_EBASE); 3396378Sgblack@eecs.umich.edu } 3406378Sgblack@eecs.umich.edu 3416378Sgblack@eecs.umich.edu setExceptionState(tc, 0x3); 3426378Sgblack@eecs.umich.edu 3436378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3446378Sgblack@eecs.umich.edu} 3456378Sgblack@eecs.umich.edu 3466378Sgblack@eecs.umich.eduvoid 3477678Sgblack@eecs.umich.eduTLBModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3486378Sgblack@eecs.umich.edu{ 3496378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3506383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 3516383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 3526379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 3536379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 3546379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 3556383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 3566379Sgblack@eecs.umich.edu 3576383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 3586379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 3596383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 3606378Sgblack@eecs.umich.edu 3616378Sgblack@eecs.umich.edu // Set new PC 3626378Sgblack@eecs.umich.edu Addr HandlerBase; 3636378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3646383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 3656378Sgblack@eecs.umich.edu setExceptionState(tc, 0x1); 3666378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3675222Sksewell@umich.edu 3685222Sksewell@umich.edu} 3695222Sksewell@umich.edu 3706378Sgblack@eecs.umich.eduvoid 3717678Sgblack@eecs.umich.eduSystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3725222Sksewell@umich.edu{ 3736378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3746378Sgblack@eecs.umich.edu setExceptionState(tc, 0x8); 3755222Sksewell@umich.edu 3766378Sgblack@eecs.umich.edu // Set new PC 3776378Sgblack@eecs.umich.edu Addr HandlerBase; 3786378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3796383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 3806378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3815222Sksewell@umich.edu} 3825222Sksewell@umich.edu 3836378Sgblack@eecs.umich.eduvoid 3847678Sgblack@eecs.umich.eduInterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3855222Sksewell@umich.edu{ 3865222Sksewell@umich.edu#if FULL_SYSTEM 3876378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3886378Sgblack@eecs.umich.edu setExceptionState(tc, 0x0A); 3896378Sgblack@eecs.umich.edu Addr HandlerBase; 3905222Sksewell@umich.edu 3916383Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); 3926379Sgblack@eecs.umich.edu if (cause.iv) { 3936378Sgblack@eecs.umich.edu // Offset 200 for release 2 3946383Sgblack@eecs.umich.edu HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 3956378Sgblack@eecs.umich.edu } else { 3966378Sgblack@eecs.umich.edu //Ofset at 180 for release 1 3976383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 3986378Sgblack@eecs.umich.edu } 3995222Sksewell@umich.edu 4006378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 4015222Sksewell@umich.edu#endif 4025222Sksewell@umich.edu} 4035222Sksewell@umich.edu 4045222Sksewell@umich.edu#endif // FULL_SYSTEM 4055222Sksewell@umich.edu 4066378Sgblack@eecs.umich.eduvoid 4077678Sgblack@eecs.umich.eduResetFault::invoke(ThreadContext *tc, StaticInstPtr inst) 4084661Sksewell@umich.edu{ 4095224Sksewell@umich.edu#if FULL_SYSTEM 4106378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4116378Sgblack@eecs.umich.edu /* All reset activity must be invoked from here */ 4126378Sgblack@eecs.umich.edu tc->setPC(vect()); 4136378Sgblack@eecs.umich.edu tc->setNextPC(vect() + sizeof(MachInst)); 4146378Sgblack@eecs.umich.edu tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst)); 4156379Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC()); 4165224Sksewell@umich.edu#endif 4175224Sksewell@umich.edu 4186378Sgblack@eecs.umich.edu // Set Coprocessor 1 (Floating Point) To Usable 4196383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 4206379Sgblack@eecs.umich.edu status.cu.cu1 = 1; 4216383Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_STATUS, status); 4225222Sksewell@umich.edu} 4235222Sksewell@umich.edu 4246378Sgblack@eecs.umich.eduvoid 4257678Sgblack@eecs.umich.eduReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst) 4265222Sksewell@umich.edu{ 4275222Sksewell@umich.edu#if FULL_SYSTEM 4286378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4296378Sgblack@eecs.umich.edu setExceptionState(tc, 0x0A); 4306378Sgblack@eecs.umich.edu Addr HandlerBase; 4316378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 4326383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 4336378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 4345222Sksewell@umich.edu#else 4355222Sksewell@umich.edu panic("%s encountered.\n", name()); 4365222Sksewell@umich.edu#endif 4375222Sksewell@umich.edu} 4385222Sksewell@umich.edu 4396378Sgblack@eecs.umich.eduvoid 4407678Sgblack@eecs.umich.eduThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst) 4415222Sksewell@umich.edu{ 4426378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4436378Sgblack@eecs.umich.edu panic("%s encountered.\n", name()); 4445222Sksewell@umich.edu} 4455222Sksewell@umich.edu 4466378Sgblack@eecs.umich.eduvoid 4477678Sgblack@eecs.umich.eduDspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst) 4485222Sksewell@umich.edu{ 4496378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4506378Sgblack@eecs.umich.edu panic("%s encountered.\n", name()); 4514661Sksewell@umich.edu} 4524661Sksewell@umich.edu 4536378Sgblack@eecs.umich.eduvoid 4547678Sgblack@eecs.umich.eduCoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst) 4554661Sksewell@umich.edu{ 4565222Sksewell@umich.edu#if FULL_SYSTEM 4576378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4586378Sgblack@eecs.umich.edu setExceptionState(tc, 0xb); 4596378Sgblack@eecs.umich.edu // The ID of the coprocessor causing the exception is stored in 4606378Sgblack@eecs.umich.edu // CoprocessorUnusableFault::coProcID 4616383Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 4626379Sgblack@eecs.umich.edu cause.ce = coProcID; 4636383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 4644661Sksewell@umich.edu 4656378Sgblack@eecs.umich.edu Addr HandlerBase; 4666378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 4676383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 4686378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 4694661Sksewell@umich.edu 4705222Sksewell@umich.edu#else 4715224Sksewell@umich.edu warn("%s (CP%d) encountered.\n", name(), coProcID); 4725222Sksewell@umich.edu#endif 4734661Sksewell@umich.edu} 4744661Sksewell@umich.edu 4752447SN/A} // namespace MipsISA 4762447SN/A 477