faults.cc revision 8566
12131SN/A/* 25268Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 52131SN/A * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 162131SN/A * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 295254Sksewell@umich.edu * Authors: Gabe Black 305254Sksewell@umich.edu * Korey Sewell 315222Sksewell@umich.edu * Jaidev Patwardhan 322131SN/A */ 332131SN/A 342239SN/A#include "arch/mips/faults.hh" 357676Snate@binkert.org#include "arch/mips/pra_constants.hh" 367676Snate@binkert.org#include "base/trace.hh" 377676Snate@binkert.org#include "cpu/base.hh" 382680Sktlim@umich.edu#include "cpu/thread_context.hh" 398232Snate@binkert.org#include "debug/MipsPRA.hh" 407676Snate@binkert.org 412800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM 427676Snate@binkert.org#include "mem/page_table.hh" 432800Ssaidi@eecs.umich.edu#include "sim/process.hh" 442800Ssaidi@eecs.umich.edu#endif 452131SN/A 462447SN/Anamespace MipsISA 472447SN/A{ 482131SN/A 498566Sgblack@eecs.umich.edutypedef MipsFaultBase::FaultVals FaultVals; 502131SN/A 518566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<MachineCheckFault>::vals = 528566Sgblack@eecs.umich.edu { "Machine Check", 0x0401 }; 532447SN/A 548566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<AlignmentFault>::vals = 558566Sgblack@eecs.umich.edu { "Alignment", 0x0301 }; 568566Sgblack@eecs.umich.edu 578566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ResetFault>::vals = 585222Sksewell@umich.edu#if FULL_SYSTEM 598566Sgblack@eecs.umich.edu { "Reset Fault", 0xBFC00000}; 605222Sksewell@umich.edu#else 618566Sgblack@eecs.umich.edu { "Reset Fault", 0x001}; 625222Sksewell@umich.edu#endif 632447SN/A 648566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<AddressErrorFault>::vals = 658566Sgblack@eecs.umich.edu { "Address Error", 0x0180 }; 665222Sksewell@umich.edu 678566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<StoreAddressErrorFault>::vals = 688566Sgblack@eecs.umich.edu { "Store Address Error", 0x0180 }; 695222Sksewell@umich.edu 708566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<SystemCallFault>::vals = 718566Sgblack@eecs.umich.edu { "Syscall", 0x0180 }; 725222Sksewell@umich.edu 738566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<CoprocessorUnusableFault>::vals = 748566Sgblack@eecs.umich.edu { "Coprocessor Unusable Fault", 0x180 }; 755222Sksewell@umich.edu 768566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ReservedInstructionFault>::vals = 778566Sgblack@eecs.umich.edu { "Reserved Instruction Fault", 0x0180 }; 784661Sksewell@umich.edu 798566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ThreadFault>::vals = 808566Sgblack@eecs.umich.edu { "Thread Fault", 0x00F1 }; 814661Sksewell@umich.edu 828566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ArithmeticFault>::vals = 838566Sgblack@eecs.umich.edu { "Arithmetic Overflow Exception", 0x180 }; 844661Sksewell@umich.edu 858566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<UnimplementedOpcodeFault>::vals = 868566Sgblack@eecs.umich.edu { "opdec", 0x0481 }; 872447SN/A 888566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<InterruptFault>::vals = 898566Sgblack@eecs.umich.edu { "interrupt", 0x0180 }; 904661Sksewell@umich.edu 918566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TrapFault>::vals = 928566Sgblack@eecs.umich.edu { "Trap", 0x0180 }; 932447SN/A 948566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<BreakpointFault>::vals = 958566Sgblack@eecs.umich.edu { "Breakpoint", 0x0180 }; 965222Sksewell@umich.edu 978566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ItbInvalidFault>::vals = 988566Sgblack@eecs.umich.edu { "Invalid TLB Entry Exception (I-Fetch/LW)", 0x0180 }; 995222Sksewell@umich.edu 1008566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ItbPageFault>::vals = 1018566Sgblack@eecs.umich.edu { "itbmiss", 0x0181 }; 1025222Sksewell@umich.edu 1038566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ItbMissFault>::vals = 1048566Sgblack@eecs.umich.edu { "itbmiss", 0x0181 }; 1055222Sksewell@umich.edu 1068566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ItbAcvFault>::vals = 1078566Sgblack@eecs.umich.edu { "iaccvio", 0x0081 }; 1085222Sksewell@umich.edu 1098566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ItbRefillFault>::vals = 1108566Sgblack@eecs.umich.edu { "TLB Refill Exception (I-Fetch/LW)", 0x0180 }; 1115222Sksewell@umich.edu 1128566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<NDtbMissFault>::vals = 1138566Sgblack@eecs.umich.edu { "dtb_miss_single", 0x0201 }; 1145222Sksewell@umich.edu 1158566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<PDtbMissFault>::vals = 1168566Sgblack@eecs.umich.edu { "dtb_miss_double", 0x0281 }; 1172447SN/A 1188566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<DtbPageFault>::vals = 1198566Sgblack@eecs.umich.edu { "dfault", 0x0381 }; 1202447SN/A 1218566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<DtbAcvFault>::vals = 1228566Sgblack@eecs.umich.edu { "dfault", 0x0381 }; 1232447SN/A 1248566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<DtbInvalidFault>::vals = 1258566Sgblack@eecs.umich.edu { "Invalid TLB Entry Exception (Store)", 0x0180 }; 1262447SN/A 1278566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<DtbRefillFault>::vals = 1288566Sgblack@eecs.umich.edu { "TLB Refill Exception (Store)", 0x0180 }; 1292447SN/A 1308566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TLBModifiedFault>::vals = 1318566Sgblack@eecs.umich.edu { "TLB Modified Exception", 0x0180 }; 1322447SN/A 1338566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<FloatEnableFault>::vals = 1348566Sgblack@eecs.umich.edu { "float_enable_fault", 0x0581 }; 1352447SN/A 1368566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<IntegerOverflowFault>::vals = 1378566Sgblack@eecs.umich.edu { "Integer Overflow Fault", 0x0501 }; 1382447SN/A 1398566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<DspStateDisabledFault>::vals = 1408566Sgblack@eecs.umich.edu { "DSP Disabled Fault", 0x001a }; 1414661Sksewell@umich.edu 1425222Sksewell@umich.edu#if FULL_SYSTEM 1436378Sgblack@eecs.umich.eduvoid 1448566Sgblack@eecs.umich.eduMipsFaultBase::setHandlerPC(Addr HandlerBase, ThreadContext *tc) 1455222Sksewell@umich.edu{ 1466378Sgblack@eecs.umich.edu tc->setPC(HandlerBase); 1476378Sgblack@eecs.umich.edu tc->setNextPC(HandlerBase + sizeof(MachInst)); 1486378Sgblack@eecs.umich.edu tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst)); 1495222Sksewell@umich.edu} 1505222Sksewell@umich.edu 1516378Sgblack@eecs.umich.eduvoid 1528566Sgblack@eecs.umich.eduMipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) 1535222Sksewell@umich.edu{ 1546378Sgblack@eecs.umich.edu // modify SRS Ctl - Save CSS, put ESS into CSS 1556383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 1566379Sgblack@eecs.umich.edu if (status.exl != 1 && status.bev != 1) { 1576378Sgblack@eecs.umich.edu // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 1586383Sgblack@eecs.umich.edu SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); 1596379Sgblack@eecs.umich.edu srsCtl.pss = srsCtl.css; 1606379Sgblack@eecs.umich.edu srsCtl.css = srsCtl.ess; 1616383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl); 1625222Sksewell@umich.edu } 1635222Sksewell@umich.edu 1646378Sgblack@eecs.umich.edu // set EXL bit (don't care if it is already set!) 1656379Sgblack@eecs.umich.edu status.exl = 1; 1666383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_STATUS, status); 1675222Sksewell@umich.edu 1686378Sgblack@eecs.umich.edu // write EPC 1696378Sgblack@eecs.umich.edu // CHECK ME or FIXME or FIX ME or POSSIBLE HACK 1706378Sgblack@eecs.umich.edu // Check to see if the exception occurred in the branch delay slot 1716378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "PC: %x, NextPC: %x, NNPC: %x\n", 1726378Sgblack@eecs.umich.edu tc->readPC(), tc->readNextPC(), tc->readNextNPC()); 1736379Sgblack@eecs.umich.edu int bd = 0; 1746378Sgblack@eecs.umich.edu if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) { 1756383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC() - sizeof(MachInst)); 1766378Sgblack@eecs.umich.edu // In the branch delay slot? set CAUSE_31 1776379Sgblack@eecs.umich.edu bd = 1; 1786378Sgblack@eecs.umich.edu } else { 1796383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC()); 1806378Sgblack@eecs.umich.edu // In the branch delay slot? reset CAUSE_31 1816379Sgblack@eecs.umich.edu bd = 0; 1826378Sgblack@eecs.umich.edu } 1835222Sksewell@umich.edu 1846378Sgblack@eecs.umich.edu // Set Cause_EXCCODE field 1856383Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 1866379Sgblack@eecs.umich.edu cause.excCode = excCode; 1876379Sgblack@eecs.umich.edu cause.bd = bd; 1886379Sgblack@eecs.umich.edu cause.ce = 0; 1896383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 1906378Sgblack@eecs.umich.edu} 1916378Sgblack@eecs.umich.edu 1926378Sgblack@eecs.umich.eduvoid 1937678Sgblack@eecs.umich.eduArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst) 1946378Sgblack@eecs.umich.edu{ 1956378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 1966378Sgblack@eecs.umich.edu setExceptionState(tc, 0xC); 1976378Sgblack@eecs.umich.edu 1986378Sgblack@eecs.umich.edu // Set new PC 1996378Sgblack@eecs.umich.edu Addr HandlerBase; 2006383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 2016378Sgblack@eecs.umich.edu // Here, the handler is dependent on BEV, which is not modified by 2026378Sgblack@eecs.umich.edu // setExceptionState() 2036379Sgblack@eecs.umich.edu if (!status.bev) { 2046378Sgblack@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 2056383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2066378Sgblack@eecs.umich.edu } else { 2076378Sgblack@eecs.umich.edu HandlerBase = 0xBFC00200; 2086378Sgblack@eecs.umich.edu } 2096378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2106378Sgblack@eecs.umich.edu} 2116378Sgblack@eecs.umich.edu 2126378Sgblack@eecs.umich.eduvoid 2137678Sgblack@eecs.umich.eduStoreAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2146378Sgblack@eecs.umich.edu{ 2156378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2166378Sgblack@eecs.umich.edu setExceptionState(tc, 0x5); 2176383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2186378Sgblack@eecs.umich.edu 2196378Sgblack@eecs.umich.edu // Set new PC 2206378Sgblack@eecs.umich.edu Addr HandlerBase; 2216378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2226383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2236378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2246378Sgblack@eecs.umich.edu} 2256378Sgblack@eecs.umich.edu 2266378Sgblack@eecs.umich.eduvoid 2277678Sgblack@eecs.umich.eduTrapFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2286378Sgblack@eecs.umich.edu{ 2296378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2306378Sgblack@eecs.umich.edu setExceptionState(tc, 0xD); 2316378Sgblack@eecs.umich.edu 2326378Sgblack@eecs.umich.edu // Set new PC 2336378Sgblack@eecs.umich.edu Addr HandlerBase; 2346378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2356383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2366378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2376378Sgblack@eecs.umich.edu} 2386378Sgblack@eecs.umich.edu 2396378Sgblack@eecs.umich.eduvoid 2407678Sgblack@eecs.umich.eduBreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2416378Sgblack@eecs.umich.edu{ 2426378Sgblack@eecs.umich.edu setExceptionState(tc, 0x9); 2436378Sgblack@eecs.umich.edu 2446378Sgblack@eecs.umich.edu // Set new PC 2456378Sgblack@eecs.umich.edu Addr HandlerBase; 2466378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2476383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2486378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2496378Sgblack@eecs.umich.edu} 2506378Sgblack@eecs.umich.edu 2516378Sgblack@eecs.umich.eduvoid 2527678Sgblack@eecs.umich.eduDtbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2536378Sgblack@eecs.umich.edu{ 2546378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2556378Sgblack@eecs.umich.edu 2566383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2576383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2586379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 2596379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2606379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 2616383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2626379Sgblack@eecs.umich.edu 2636383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2646379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2656383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2666378Sgblack@eecs.umich.edu setExceptionState(tc, 0x3); 2676378Sgblack@eecs.umich.edu 2686378Sgblack@eecs.umich.edu 2696378Sgblack@eecs.umich.edu // Set new PC 2706378Sgblack@eecs.umich.edu Addr HandlerBase; 2716378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2726383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2736379Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2746378Sgblack@eecs.umich.edu} 2756378Sgblack@eecs.umich.edu 2766378Sgblack@eecs.umich.eduvoid 2777678Sgblack@eecs.umich.eduAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2786378Sgblack@eecs.umich.edu{ 2796378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2806378Sgblack@eecs.umich.edu setExceptionState(tc, 0x4); 2816383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2826378Sgblack@eecs.umich.edu 2836378Sgblack@eecs.umich.edu // Set new PC 2846378Sgblack@eecs.umich.edu Addr HandlerBase; 2856378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2866383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 2876378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2886378Sgblack@eecs.umich.edu} 2896378Sgblack@eecs.umich.edu 2906378Sgblack@eecs.umich.eduvoid 2917678Sgblack@eecs.umich.eduItbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst) 2926378Sgblack@eecs.umich.edu{ 2936378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2946378Sgblack@eecs.umich.edu setExceptionState(tc, 0x2); 2956383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 2966383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2976379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 2986379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2996379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 3006383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 3016379Sgblack@eecs.umich.edu 3026383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 3036379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 3046383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 3056378Sgblack@eecs.umich.edu 3066378Sgblack@eecs.umich.edu 3076378Sgblack@eecs.umich.edu // Set new PC 3086378Sgblack@eecs.umich.edu Addr HandlerBase; 3096378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3106383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 3116378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase,tc); 3126379Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n", 3136383Sgblack@eecs.umich.edu HandlerBase, tc->readMiscReg(MISCREG_EPC)); 3146378Sgblack@eecs.umich.edu} 3156378Sgblack@eecs.umich.edu 3166378Sgblack@eecs.umich.eduvoid 3177678Sgblack@eecs.umich.eduItbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3186378Sgblack@eecs.umich.edu{ 3196383Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR); 3206378Sgblack@eecs.umich.edu Addr HandlerBase; 3216383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 3226383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 3236379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 3246379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 3256379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 3266383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 3276383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 3286379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 3296383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 3306378Sgblack@eecs.umich.edu 3316383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 3326378Sgblack@eecs.umich.edu // Since handler depends on EXL bit, must check EXL bit before setting it!! 3336378Sgblack@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 3346379Sgblack@eecs.umich.edu if (status.exl == 1) { 3356378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3366383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 3376378Sgblack@eecs.umich.edu } else { 3386378Sgblack@eecs.umich.edu // Offset 0x000 3396383Sgblack@eecs.umich.edu HandlerBase = tc->readMiscReg(MISCREG_EBASE); 3406378Sgblack@eecs.umich.edu } 3416378Sgblack@eecs.umich.edu 3426378Sgblack@eecs.umich.edu setExceptionState(tc, 0x2); 3436378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3446378Sgblack@eecs.umich.edu} 3456378Sgblack@eecs.umich.edu 3466378Sgblack@eecs.umich.eduvoid 3477678Sgblack@eecs.umich.eduDtbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3486378Sgblack@eecs.umich.edu{ 3496378Sgblack@eecs.umich.edu // Set new PC 3506378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3516378Sgblack@eecs.umich.edu Addr HandlerBase; 3526383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 3536383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 3546379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 3556379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 3566379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 3576383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 3586378Sgblack@eecs.umich.edu 3596383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 3606379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 3616383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 3626379Sgblack@eecs.umich.edu 3636383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 3646378Sgblack@eecs.umich.edu // Since handler depends on EXL bit, must check EXL bit before setting it!! 3656378Sgblack@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 3666379Sgblack@eecs.umich.edu if (status.exl) { 3676378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3686383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 3696378Sgblack@eecs.umich.edu } else { 3706378Sgblack@eecs.umich.edu // Offset 0x000 3716383Sgblack@eecs.umich.edu HandlerBase = tc->readMiscReg(MISCREG_EBASE); 3726378Sgblack@eecs.umich.edu } 3736378Sgblack@eecs.umich.edu 3746378Sgblack@eecs.umich.edu setExceptionState(tc, 0x3); 3756378Sgblack@eecs.umich.edu 3766378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3776378Sgblack@eecs.umich.edu} 3786378Sgblack@eecs.umich.edu 3796378Sgblack@eecs.umich.eduvoid 3807678Sgblack@eecs.umich.eduTLBModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst) 3816378Sgblack@eecs.umich.edu{ 3826378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3836383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); 3846383Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 3856379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 3866379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 3876379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 3886383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 3896379Sgblack@eecs.umich.edu 3906383Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 3916379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 3926383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 3936378Sgblack@eecs.umich.edu 3946378Sgblack@eecs.umich.edu // Set new PC 3956378Sgblack@eecs.umich.edu Addr HandlerBase; 3966378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3976383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 3986378Sgblack@eecs.umich.edu setExceptionState(tc, 0x1); 3996378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 4005222Sksewell@umich.edu 4015222Sksewell@umich.edu} 4025222Sksewell@umich.edu 4036378Sgblack@eecs.umich.eduvoid 4047678Sgblack@eecs.umich.eduSystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst) 4055222Sksewell@umich.edu{ 4066378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4076378Sgblack@eecs.umich.edu setExceptionState(tc, 0x8); 4085222Sksewell@umich.edu 4096378Sgblack@eecs.umich.edu // Set new PC 4106378Sgblack@eecs.umich.edu Addr HandlerBase; 4116378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 4126383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 4136378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 4145222Sksewell@umich.edu} 4155222Sksewell@umich.edu 4166378Sgblack@eecs.umich.eduvoid 4177678Sgblack@eecs.umich.eduInterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst) 4185222Sksewell@umich.edu{ 4195222Sksewell@umich.edu#if FULL_SYSTEM 4206378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4216378Sgblack@eecs.umich.edu setExceptionState(tc, 0x0A); 4226378Sgblack@eecs.umich.edu Addr HandlerBase; 4235222Sksewell@umich.edu 4246383Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); 4256379Sgblack@eecs.umich.edu if (cause.iv) { 4266378Sgblack@eecs.umich.edu // Offset 200 for release 2 4276383Sgblack@eecs.umich.edu HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 4286378Sgblack@eecs.umich.edu } else { 4296378Sgblack@eecs.umich.edu //Ofset at 180 for release 1 4306383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 4316378Sgblack@eecs.umich.edu } 4325222Sksewell@umich.edu 4336378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 4345222Sksewell@umich.edu#endif 4355222Sksewell@umich.edu} 4365222Sksewell@umich.edu 4375222Sksewell@umich.edu#endif // FULL_SYSTEM 4385222Sksewell@umich.edu 4396378Sgblack@eecs.umich.eduvoid 4407678Sgblack@eecs.umich.eduResetFault::invoke(ThreadContext *tc, StaticInstPtr inst) 4414661Sksewell@umich.edu{ 4425224Sksewell@umich.edu#if FULL_SYSTEM 4436378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4446378Sgblack@eecs.umich.edu /* All reset activity must be invoked from here */ 4456378Sgblack@eecs.umich.edu tc->setPC(vect()); 4466378Sgblack@eecs.umich.edu tc->setNextPC(vect() + sizeof(MachInst)); 4476378Sgblack@eecs.umich.edu tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst)); 4486379Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC()); 4495224Sksewell@umich.edu#endif 4505224Sksewell@umich.edu 4516378Sgblack@eecs.umich.edu // Set Coprocessor 1 (Floating Point) To Usable 4526383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 4536379Sgblack@eecs.umich.edu status.cu.cu1 = 1; 4546383Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_STATUS, status); 4555222Sksewell@umich.edu} 4565222Sksewell@umich.edu 4576378Sgblack@eecs.umich.eduvoid 4587678Sgblack@eecs.umich.eduReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst) 4595222Sksewell@umich.edu{ 4605222Sksewell@umich.edu#if FULL_SYSTEM 4616378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4626378Sgblack@eecs.umich.edu setExceptionState(tc, 0x0A); 4636378Sgblack@eecs.umich.edu Addr HandlerBase; 4646378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 4656383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); 4666378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 4675222Sksewell@umich.edu#else 4685222Sksewell@umich.edu panic("%s encountered.\n", name()); 4695222Sksewell@umich.edu#endif 4705222Sksewell@umich.edu} 4715222Sksewell@umich.edu 4726378Sgblack@eecs.umich.eduvoid 4737678Sgblack@eecs.umich.eduThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst) 4745222Sksewell@umich.edu{ 4756378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4766378Sgblack@eecs.umich.edu panic("%s encountered.\n", name()); 4775222Sksewell@umich.edu} 4785222Sksewell@umich.edu 4796378Sgblack@eecs.umich.eduvoid 4807678Sgblack@eecs.umich.eduDspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst) 4815222Sksewell@umich.edu{ 4826378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4836378Sgblack@eecs.umich.edu panic("%s encountered.\n", name()); 4844661Sksewell@umich.edu} 4854661Sksewell@umich.edu 4866378Sgblack@eecs.umich.eduvoid 4877678Sgblack@eecs.umich.eduCoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst) 4884661Sksewell@umich.edu{ 4895222Sksewell@umich.edu#if FULL_SYSTEM 4906378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4916378Sgblack@eecs.umich.edu setExceptionState(tc, 0xb); 4926378Sgblack@eecs.umich.edu // The ID of the coprocessor causing the exception is stored in 4936378Sgblack@eecs.umich.edu // CoprocessorUnusableFault::coProcID 4946383Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 4956379Sgblack@eecs.umich.edu cause.ce = coProcID; 4966383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 4974661Sksewell@umich.edu 4986378Sgblack@eecs.umich.edu Addr HandlerBase; 4996378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 5006383Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 5016378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 5024661Sksewell@umich.edu 5035222Sksewell@umich.edu#else 5045224Sksewell@umich.edu warn("%s (CP%d) encountered.\n", name(), coProcID); 5055222Sksewell@umich.edu#endif 5064661Sksewell@umich.edu} 5074661Sksewell@umich.edu 5082447SN/A} // namespace MipsISA 5092447SN/A 510