faults.cc revision 6379
12131SN/A/* 25268Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 52131SN/A * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 162131SN/A * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 295254Sksewell@umich.edu * Authors: Gabe Black 305254Sksewell@umich.edu * Korey Sewell 315222Sksewell@umich.edu * Jaidev Patwardhan 322131SN/A */ 332131SN/A 342239SN/A#include "arch/mips/faults.hh" 352680Sktlim@umich.edu#include "cpu/thread_context.hh" 362447SN/A#include "cpu/base.hh" 372447SN/A#include "base/trace.hh" 385222Sksewell@umich.edu#include "arch/mips/pra_constants.hh" 392800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM 402800Ssaidi@eecs.umich.edu#include "sim/process.hh" 412800Ssaidi@eecs.umich.edu#include "mem/page_table.hh" 422800Ssaidi@eecs.umich.edu#endif 432131SN/A 442447SN/Anamespace MipsISA 452447SN/A{ 462131SN/A 472479SN/AFaultName MachineCheckFault::_name = "Machine Check"; 482447SN/AFaultVect MachineCheckFault::_vect = 0x0401; 492447SN/AFaultStat MachineCheckFault::_count; 502131SN/A 512479SN/AFaultName AlignmentFault::_name = "Alignment"; 522447SN/AFaultVect AlignmentFault::_vect = 0x0301; 532447SN/AFaultStat AlignmentFault::_count; 542447SN/A 555224Sksewell@umich.eduFaultName ResetFault::_name = "Reset Fault"; 565222Sksewell@umich.edu#if FULL_SYSTEM 575222Sksewell@umich.eduFaultVect ResetFault::_vect = 0xBFC00000; 585222Sksewell@umich.edu#else 595222Sksewell@umich.eduFaultVect ResetFault::_vect = 0x001; 605222Sksewell@umich.edu#endif 612447SN/AFaultStat ResetFault::_count; 622447SN/A 635222Sksewell@umich.eduFaultName AddressErrorFault::_name = "Address Error"; 645222Sksewell@umich.eduFaultVect AddressErrorFault::_vect = 0x0180; 655222Sksewell@umich.eduFaultStat AddressErrorFault::_count; 665222Sksewell@umich.edu 675222Sksewell@umich.eduFaultName StoreAddressErrorFault::_name = "Store Address Error"; 685222Sksewell@umich.eduFaultVect StoreAddressErrorFault::_vect = 0x0180; 695222Sksewell@umich.eduFaultStat StoreAddressErrorFault::_count; 705222Sksewell@umich.edu 715222Sksewell@umich.edu 725222Sksewell@umich.eduFaultName SystemCallFault::_name = "Syscall"; 735222Sksewell@umich.eduFaultVect SystemCallFault::_vect = 0x0180; 745222Sksewell@umich.eduFaultStat SystemCallFault::_count; 755222Sksewell@umich.edu 765224Sksewell@umich.eduFaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable Fault"; 775222Sksewell@umich.eduFaultVect CoprocessorUnusableFault::_vect = 0x180; 784661Sksewell@umich.eduFaultStat CoprocessorUnusableFault::_count; 794661Sksewell@umich.edu 805224Sksewell@umich.eduFaultName ReservedInstructionFault::_name = "Reserved Instruction Fault"; 815222Sksewell@umich.eduFaultVect ReservedInstructionFault::_vect = 0x0180; 824661Sksewell@umich.eduFaultStat ReservedInstructionFault::_count; 834661Sksewell@umich.edu 845224Sksewell@umich.eduFaultName ThreadFault::_name = "Thread Fault"; 854661Sksewell@umich.eduFaultVect ThreadFault::_vect = 0x00F1; 864661Sksewell@umich.eduFaultStat ThreadFault::_count; 874661Sksewell@umich.edu 885222Sksewell@umich.eduFaultName ArithmeticFault::_name = "Arithmetic Overflow Exception"; 895222Sksewell@umich.eduFaultVect ArithmeticFault::_vect = 0x180; 902447SN/AFaultStat ArithmeticFault::_count; 912447SN/A 924661Sksewell@umich.eduFaultName UnimplementedOpcodeFault::_name = "opdec"; 934661Sksewell@umich.eduFaultVect UnimplementedOpcodeFault::_vect = 0x0481; 944661Sksewell@umich.eduFaultStat UnimplementedOpcodeFault::_count; 954661Sksewell@umich.edu 962447SN/AFaultName InterruptFault::_name = "interrupt"; 975222Sksewell@umich.eduFaultVect InterruptFault::_vect = 0x0180; 982447SN/AFaultStat InterruptFault::_count; 992447SN/A 1005222Sksewell@umich.eduFaultName TrapFault::_name = "Trap"; 1015222Sksewell@umich.eduFaultVect TrapFault::_vect = 0x0180; 1025222Sksewell@umich.eduFaultStat TrapFault::_count; 1035222Sksewell@umich.edu 1045222Sksewell@umich.eduFaultName BreakpointFault::_name = "Breakpoint"; 1055222Sksewell@umich.eduFaultVect BreakpointFault::_vect = 0x0180; 1065222Sksewell@umich.eduFaultStat BreakpointFault::_count; 1075222Sksewell@umich.edu 1085222Sksewell@umich.eduFaultName ItbInvalidFault::_name = "Invalid TLB Entry Exception (I-Fetch/LW)"; 1095222Sksewell@umich.eduFaultVect ItbInvalidFault::_vect = 0x0180; 1105222Sksewell@umich.eduFaultStat ItbInvalidFault::_count; 1115222Sksewell@umich.edu 1125222Sksewell@umich.eduFaultName ItbPageFault::_name = "itbmiss"; 1135222Sksewell@umich.eduFaultVect ItbPageFault::_vect = 0x0181; 1145222Sksewell@umich.eduFaultStat ItbPageFault::_count; 1155222Sksewell@umich.edu 1165222Sksewell@umich.eduFaultName ItbMissFault::_name = "itbmiss"; 1175222Sksewell@umich.eduFaultVect ItbMissFault::_vect = 0x0181; 1185222Sksewell@umich.eduFaultStat ItbMissFault::_count; 1195222Sksewell@umich.edu 1205222Sksewell@umich.eduFaultName ItbAcvFault::_name = "iaccvio"; 1215222Sksewell@umich.eduFaultVect ItbAcvFault::_vect = 0x0081; 1225222Sksewell@umich.eduFaultStat ItbAcvFault::_count; 1235222Sksewell@umich.edu 1245222Sksewell@umich.eduFaultName ItbRefillFault::_name = "TLB Refill Exception (I-Fetch/LW)"; 1255222Sksewell@umich.eduFaultVect ItbRefillFault::_vect = 0x0180; 1265222Sksewell@umich.eduFaultStat ItbRefillFault::_count; 1275222Sksewell@umich.edu 1282447SN/AFaultName NDtbMissFault::_name = "dtb_miss_single"; 1292447SN/AFaultVect NDtbMissFault::_vect = 0x0201; 1302447SN/AFaultStat NDtbMissFault::_count; 1312447SN/A 1322447SN/AFaultName PDtbMissFault::_name = "dtb_miss_double"; 1332447SN/AFaultVect PDtbMissFault::_vect = 0x0281; 1342447SN/AFaultStat PDtbMissFault::_count; 1352447SN/A 1362447SN/AFaultName DtbPageFault::_name = "dfault"; 1372447SN/AFaultVect DtbPageFault::_vect = 0x0381; 1382447SN/AFaultStat DtbPageFault::_count; 1392447SN/A 1402447SN/AFaultName DtbAcvFault::_name = "dfault"; 1412447SN/AFaultVect DtbAcvFault::_vect = 0x0381; 1422447SN/AFaultStat DtbAcvFault::_count; 1432447SN/A 1445222Sksewell@umich.eduFaultName DtbInvalidFault::_name = "Invalid TLB Entry Exception (Store)"; 1455222Sksewell@umich.eduFaultVect DtbInvalidFault::_vect = 0x0180; 1465222Sksewell@umich.eduFaultStat DtbInvalidFault::_count; 1472447SN/A 1485222Sksewell@umich.eduFaultName DtbRefillFault::_name = "TLB Refill Exception (Store)"; 1495222Sksewell@umich.eduFaultVect DtbRefillFault::_vect = 0x0180; 1505222Sksewell@umich.eduFaultStat DtbRefillFault::_count; 1512447SN/A 1525222Sksewell@umich.eduFaultName TLBModifiedFault::_name = "TLB Modified Exception"; 1535222Sksewell@umich.eduFaultVect TLBModifiedFault::_vect = 0x0180; 1545222Sksewell@umich.eduFaultStat TLBModifiedFault::_count; 1552447SN/A 1565222Sksewell@umich.eduFaultName FloatEnableFault::_name = "float_enable_fault"; 1572447SN/AFaultVect FloatEnableFault::_vect = 0x0581; 1582447SN/AFaultStat FloatEnableFault::_count; 1592447SN/A 1605222Sksewell@umich.eduFaultName IntegerOverflowFault::_name = "Integer Overflow Fault"; 1612447SN/AFaultVect IntegerOverflowFault::_vect = 0x0501; 1622447SN/AFaultStat IntegerOverflowFault::_count; 1632447SN/A 1645222Sksewell@umich.eduFaultName DspStateDisabledFault::_name = "DSP Disabled Fault"; 1654661Sksewell@umich.eduFaultVect DspStateDisabledFault::_vect = 0x001a; 1664661Sksewell@umich.eduFaultStat DspStateDisabledFault::_count; 1674661Sksewell@umich.edu 1685222Sksewell@umich.edu#if FULL_SYSTEM 1696378Sgblack@eecs.umich.eduvoid 1706378Sgblack@eecs.umich.eduMipsFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc) 1715222Sksewell@umich.edu{ 1726378Sgblack@eecs.umich.edu tc->setPC(HandlerBase); 1736378Sgblack@eecs.umich.edu tc->setNextPC(HandlerBase + sizeof(MachInst)); 1746378Sgblack@eecs.umich.edu tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst)); 1755222Sksewell@umich.edu} 1765222Sksewell@umich.edu 1776378Sgblack@eecs.umich.eduvoid 1786379Sgblack@eecs.umich.eduMipsFault::setExceptionState(ThreadContext *tc, uint8_t excCode) 1795222Sksewell@umich.edu{ 1806378Sgblack@eecs.umich.edu // modify SRS Ctl - Save CSS, put ESS into CSS 1816379Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(Status); 1826379Sgblack@eecs.umich.edu if (status.exl != 1 && status.bev != 1) { 1836378Sgblack@eecs.umich.edu // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 1846379Sgblack@eecs.umich.edu SRSCtlReg srsCtl = tc->readMiscReg(SRSCtl); 1856379Sgblack@eecs.umich.edu srsCtl.pss = srsCtl.css; 1866379Sgblack@eecs.umich.edu srsCtl.css = srsCtl.ess; 1876379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(SRSCtl, srsCtl); 1885222Sksewell@umich.edu } 1895222Sksewell@umich.edu 1906378Sgblack@eecs.umich.edu // set EXL bit (don't care if it is already set!) 1916379Sgblack@eecs.umich.edu status.exl = 1; 1926379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(Status, status); 1935222Sksewell@umich.edu 1946378Sgblack@eecs.umich.edu // write EPC 1956378Sgblack@eecs.umich.edu // CHECK ME or FIXME or FIX ME or POSSIBLE HACK 1966378Sgblack@eecs.umich.edu // Check to see if the exception occurred in the branch delay slot 1976378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "PC: %x, NextPC: %x, NNPC: %x\n", 1986378Sgblack@eecs.umich.edu tc->readPC(), tc->readNextPC(), tc->readNextNPC()); 1996379Sgblack@eecs.umich.edu int bd = 0; 2006378Sgblack@eecs.umich.edu if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) { 2016379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(EPC, tc->readPC() - sizeof(MachInst)); 2026378Sgblack@eecs.umich.edu // In the branch delay slot? set CAUSE_31 2036379Sgblack@eecs.umich.edu bd = 1; 2046378Sgblack@eecs.umich.edu } else { 2056379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(EPC, tc->readPC()); 2066378Sgblack@eecs.umich.edu // In the branch delay slot? reset CAUSE_31 2076379Sgblack@eecs.umich.edu bd = 0; 2086378Sgblack@eecs.umich.edu } 2095222Sksewell@umich.edu 2106378Sgblack@eecs.umich.edu // Set Cause_EXCCODE field 2116379Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscReg(Cause); 2126379Sgblack@eecs.umich.edu cause.excCode = excCode; 2136379Sgblack@eecs.umich.edu cause.bd = bd; 2146379Sgblack@eecs.umich.edu cause.ce = 0; 2156379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(Cause, cause); 2166378Sgblack@eecs.umich.edu} 2176378Sgblack@eecs.umich.edu 2186378Sgblack@eecs.umich.eduvoid 2196378Sgblack@eecs.umich.eduArithmeticFault::invoke(ThreadContext *tc) 2206378Sgblack@eecs.umich.edu{ 2216378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2226378Sgblack@eecs.umich.edu setExceptionState(tc, 0xC); 2236378Sgblack@eecs.umich.edu 2246378Sgblack@eecs.umich.edu // Set new PC 2256378Sgblack@eecs.umich.edu Addr HandlerBase; 2266379Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(Status); 2276378Sgblack@eecs.umich.edu // Here, the handler is dependent on BEV, which is not modified by 2286378Sgblack@eecs.umich.edu // setExceptionState() 2296379Sgblack@eecs.umich.edu if (!status.bev) { 2306378Sgblack@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 2316379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(EBase); 2326378Sgblack@eecs.umich.edu } else { 2336378Sgblack@eecs.umich.edu HandlerBase = 0xBFC00200; 2346378Sgblack@eecs.umich.edu } 2356378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2366378Sgblack@eecs.umich.edu} 2376378Sgblack@eecs.umich.edu 2386378Sgblack@eecs.umich.eduvoid 2396378Sgblack@eecs.umich.eduStoreAddressErrorFault::invoke(ThreadContext *tc) 2406378Sgblack@eecs.umich.edu{ 2416378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2426378Sgblack@eecs.umich.edu setExceptionState(tc, 0x5); 2436379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(BadVAddr, badVAddr); 2446378Sgblack@eecs.umich.edu 2456378Sgblack@eecs.umich.edu // Set new PC 2466378Sgblack@eecs.umich.edu Addr HandlerBase; 2476378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2486379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(EBase); 2496378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2506378Sgblack@eecs.umich.edu} 2516378Sgblack@eecs.umich.edu 2526378Sgblack@eecs.umich.eduvoid 2536378Sgblack@eecs.umich.eduTrapFault::invoke(ThreadContext *tc) 2546378Sgblack@eecs.umich.edu{ 2556378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2566378Sgblack@eecs.umich.edu setExceptionState(tc, 0xD); 2576378Sgblack@eecs.umich.edu 2586378Sgblack@eecs.umich.edu // Set new PC 2596378Sgblack@eecs.umich.edu Addr HandlerBase; 2606378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2616379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(EBase); 2626378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2636378Sgblack@eecs.umich.edu} 2646378Sgblack@eecs.umich.edu 2656378Sgblack@eecs.umich.eduvoid 2666378Sgblack@eecs.umich.eduBreakpointFault::invoke(ThreadContext *tc) 2676378Sgblack@eecs.umich.edu{ 2686378Sgblack@eecs.umich.edu setExceptionState(tc, 0x9); 2696378Sgblack@eecs.umich.edu 2706378Sgblack@eecs.umich.edu // Set new PC 2716378Sgblack@eecs.umich.edu Addr HandlerBase; 2726378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2736379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(EBase); 2746378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 2756378Sgblack@eecs.umich.edu} 2766378Sgblack@eecs.umich.edu 2776378Sgblack@eecs.umich.eduvoid 2786378Sgblack@eecs.umich.eduDtbInvalidFault::invoke(ThreadContext *tc) 2796378Sgblack@eecs.umich.edu{ 2806378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 2816378Sgblack@eecs.umich.edu 2826379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(BadVAddr, badVAddr); 2836379Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(EntryHi); 2846379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 2856379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 2866379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 2876379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(EntryHi, entryHi); 2886379Sgblack@eecs.umich.edu 2896379Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(Context); 2906379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 2916379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(Context, context); 2926378Sgblack@eecs.umich.edu setExceptionState(tc, 0x3); 2936378Sgblack@eecs.umich.edu 2946378Sgblack@eecs.umich.edu 2956378Sgblack@eecs.umich.edu // Set new PC 2966378Sgblack@eecs.umich.edu Addr HandlerBase; 2976378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 2986379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(EBase); 2996379Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3006378Sgblack@eecs.umich.edu} 3016378Sgblack@eecs.umich.edu 3026378Sgblack@eecs.umich.eduvoid 3036378Sgblack@eecs.umich.eduAddressErrorFault::invoke(ThreadContext *tc) 3046378Sgblack@eecs.umich.edu{ 3056378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3066378Sgblack@eecs.umich.edu setExceptionState(tc, 0x4); 3076379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(BadVAddr, badVAddr); 3086378Sgblack@eecs.umich.edu 3096378Sgblack@eecs.umich.edu // Set new PC 3106378Sgblack@eecs.umich.edu Addr HandlerBase; 3116378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3126379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(EBase); 3136378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3146378Sgblack@eecs.umich.edu} 3156378Sgblack@eecs.umich.edu 3166378Sgblack@eecs.umich.eduvoid 3176378Sgblack@eecs.umich.eduItbInvalidFault::invoke(ThreadContext *tc) 3186378Sgblack@eecs.umich.edu{ 3196378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3206378Sgblack@eecs.umich.edu setExceptionState(tc, 0x2); 3216379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(BadVAddr, badVAddr); 3226379Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(EntryHi); 3236379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 3246379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 3256379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 3266379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(EntryHi, entryHi); 3276379Sgblack@eecs.umich.edu 3286379Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(Context); 3296379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 3306379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(Context, context); 3316378Sgblack@eecs.umich.edu 3326378Sgblack@eecs.umich.edu 3336378Sgblack@eecs.umich.edu // Set new PC 3346378Sgblack@eecs.umich.edu Addr HandlerBase; 3356378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3366379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(EBase); 3376378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase,tc); 3386379Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n", 3396379Sgblack@eecs.umich.edu HandlerBase, tc->readMiscReg(EPC)); 3406378Sgblack@eecs.umich.edu} 3416378Sgblack@eecs.umich.edu 3426378Sgblack@eecs.umich.eduvoid 3436378Sgblack@eecs.umich.eduItbRefillFault::invoke(ThreadContext *tc) 3446378Sgblack@eecs.umich.edu{ 3456379Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), badVAddr); 3466378Sgblack@eecs.umich.edu Addr HandlerBase; 3476379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(BadVAddr, badVAddr); 3486379Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(EntryHi); 3496379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 3506379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 3516379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 3526379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(EntryHi, entryHi); 3536379Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(Context); 3546379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 3556379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(Context, context); 3566378Sgblack@eecs.umich.edu 3576379Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(Status); 3586378Sgblack@eecs.umich.edu // Since handler depends on EXL bit, must check EXL bit before setting it!! 3596378Sgblack@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 3606379Sgblack@eecs.umich.edu if (status.exl == 1) { 3616378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3626379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(EBase); 3636378Sgblack@eecs.umich.edu } else { 3646378Sgblack@eecs.umich.edu // Offset 0x000 3656379Sgblack@eecs.umich.edu HandlerBase = tc->readMiscReg(EBase); 3666378Sgblack@eecs.umich.edu } 3676378Sgblack@eecs.umich.edu 3686378Sgblack@eecs.umich.edu setExceptionState(tc, 0x2); 3696378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 3706378Sgblack@eecs.umich.edu} 3716378Sgblack@eecs.umich.edu 3726378Sgblack@eecs.umich.eduvoid 3736378Sgblack@eecs.umich.eduDtbRefillFault::invoke(ThreadContext *tc) 3746378Sgblack@eecs.umich.edu{ 3756378Sgblack@eecs.umich.edu // Set new PC 3766378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 3776378Sgblack@eecs.umich.edu Addr HandlerBase; 3786379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(BadVAddr, badVAddr); 3796379Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(EntryHi); 3806379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 3816379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 3826379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 3836379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(EntryHi, entryHi); 3846378Sgblack@eecs.umich.edu 3856379Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(Context); 3866379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 3876379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(Context, context); 3886379Sgblack@eecs.umich.edu 3896379Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(Status); 3906378Sgblack@eecs.umich.edu // Since handler depends on EXL bit, must check EXL bit before setting it!! 3916378Sgblack@eecs.umich.edu // See MIPS ARM Vol 3, Revision 2, Page 38 3926379Sgblack@eecs.umich.edu if (status.exl) { 3936378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 3946379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(EBase); 3956378Sgblack@eecs.umich.edu } else { 3966378Sgblack@eecs.umich.edu // Offset 0x000 3976379Sgblack@eecs.umich.edu HandlerBase = tc->readMiscReg(EBase); 3986378Sgblack@eecs.umich.edu } 3996378Sgblack@eecs.umich.edu 4006378Sgblack@eecs.umich.edu setExceptionState(tc, 0x3); 4016378Sgblack@eecs.umich.edu 4026378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 4036378Sgblack@eecs.umich.edu} 4046378Sgblack@eecs.umich.edu 4056378Sgblack@eecs.umich.eduvoid 4066378Sgblack@eecs.umich.eduTLBModifiedFault::invoke(ThreadContext *tc) 4076378Sgblack@eecs.umich.edu{ 4086378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4096379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(BadVAddr, badVAddr); 4106379Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(EntryHi); 4116379Sgblack@eecs.umich.edu entryHi.asid = entryHiAsid; 4126379Sgblack@eecs.umich.edu entryHi.vpn2 = entryHiVPN2; 4136379Sgblack@eecs.umich.edu entryHi.vpn2x = entryHiVPN2X; 4146379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(EntryHi, entryHi); 4156379Sgblack@eecs.umich.edu 4166379Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(Context); 4176379Sgblack@eecs.umich.edu context.badVPN2 = contextBadVPN2; 4186379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(Context, context); 4196378Sgblack@eecs.umich.edu 4206378Sgblack@eecs.umich.edu // Set new PC 4216378Sgblack@eecs.umich.edu Addr HandlerBase; 4226378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 4236379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(EBase); 4246378Sgblack@eecs.umich.edu setExceptionState(tc, 0x1); 4256378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 4265222Sksewell@umich.edu 4275222Sksewell@umich.edu} 4285222Sksewell@umich.edu 4296378Sgblack@eecs.umich.eduvoid 4306378Sgblack@eecs.umich.eduSystemCallFault::invoke(ThreadContext *tc) 4315222Sksewell@umich.edu{ 4326378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4336378Sgblack@eecs.umich.edu setExceptionState(tc, 0x8); 4345222Sksewell@umich.edu 4356378Sgblack@eecs.umich.edu // Set new PC 4366378Sgblack@eecs.umich.edu Addr HandlerBase; 4376378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 4386379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(EBase); 4396378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 4405222Sksewell@umich.edu} 4415222Sksewell@umich.edu 4426378Sgblack@eecs.umich.eduvoid 4436378Sgblack@eecs.umich.eduInterruptFault::invoke(ThreadContext *tc) 4445222Sksewell@umich.edu{ 4455222Sksewell@umich.edu#if FULL_SYSTEM 4466378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4476378Sgblack@eecs.umich.edu setExceptionState(tc, 0x0A); 4486378Sgblack@eecs.umich.edu Addr HandlerBase; 4495222Sksewell@umich.edu 4506379Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscRegNoEffect(Cause); 4516379Sgblack@eecs.umich.edu if (cause.iv) { 4526378Sgblack@eecs.umich.edu // Offset 200 for release 2 4536379Sgblack@eecs.umich.edu HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(EBase); 4546378Sgblack@eecs.umich.edu } else { 4556378Sgblack@eecs.umich.edu //Ofset at 180 for release 1 4566379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscRegNoEffect(EBase); 4576378Sgblack@eecs.umich.edu } 4585222Sksewell@umich.edu 4596378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 4605222Sksewell@umich.edu#endif 4615222Sksewell@umich.edu} 4625222Sksewell@umich.edu 4635222Sksewell@umich.edu#endif // FULL_SYSTEM 4645222Sksewell@umich.edu 4656378Sgblack@eecs.umich.eduvoid 4666378Sgblack@eecs.umich.eduResetFault::invoke(ThreadContext *tc) 4674661Sksewell@umich.edu{ 4685224Sksewell@umich.edu#if FULL_SYSTEM 4696378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4706378Sgblack@eecs.umich.edu /* All reset activity must be invoked from here */ 4716378Sgblack@eecs.umich.edu tc->setPC(vect()); 4726378Sgblack@eecs.umich.edu tc->setNextPC(vect() + sizeof(MachInst)); 4736378Sgblack@eecs.umich.edu tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst)); 4746379Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC()); 4755224Sksewell@umich.edu#endif 4765224Sksewell@umich.edu 4776378Sgblack@eecs.umich.edu // Set Coprocessor 1 (Floating Point) To Usable 4786379Sgblack@eecs.umich.edu StatusReg status = tc->readMiscRegNoEffect(Status); 4796379Sgblack@eecs.umich.edu status.cu.cu1 = 1; 4806379Sgblack@eecs.umich.edu tc->setMiscReg(Status, status); 4815222Sksewell@umich.edu} 4825222Sksewell@umich.edu 4836378Sgblack@eecs.umich.eduvoid 4846378Sgblack@eecs.umich.eduReservedInstructionFault::invoke(ThreadContext *tc) 4855222Sksewell@umich.edu{ 4865222Sksewell@umich.edu#if FULL_SYSTEM 4876378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 4886378Sgblack@eecs.umich.edu setExceptionState(tc, 0x0A); 4896378Sgblack@eecs.umich.edu Addr HandlerBase; 4906378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 4916379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscRegNoEffect(EBase); 4926378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 4935222Sksewell@umich.edu#else 4945222Sksewell@umich.edu panic("%s encountered.\n", name()); 4955222Sksewell@umich.edu#endif 4965222Sksewell@umich.edu} 4975222Sksewell@umich.edu 4986378Sgblack@eecs.umich.eduvoid 4996378Sgblack@eecs.umich.eduThreadFault::invoke(ThreadContext *tc) 5005222Sksewell@umich.edu{ 5016378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 5026378Sgblack@eecs.umich.edu panic("%s encountered.\n", name()); 5035222Sksewell@umich.edu} 5045222Sksewell@umich.edu 5056378Sgblack@eecs.umich.eduvoid 5066378Sgblack@eecs.umich.eduDspStateDisabledFault::invoke(ThreadContext *tc) 5075222Sksewell@umich.edu{ 5086378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 5096378Sgblack@eecs.umich.edu panic("%s encountered.\n", name()); 5104661Sksewell@umich.edu} 5114661Sksewell@umich.edu 5126378Sgblack@eecs.umich.eduvoid 5136378Sgblack@eecs.umich.eduCoprocessorUnusableFault::invoke(ThreadContext *tc) 5144661Sksewell@umich.edu{ 5155222Sksewell@umich.edu#if FULL_SYSTEM 5166378Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 5176378Sgblack@eecs.umich.edu setExceptionState(tc, 0xb); 5186378Sgblack@eecs.umich.edu // The ID of the coprocessor causing the exception is stored in 5196378Sgblack@eecs.umich.edu // CoprocessorUnusableFault::coProcID 5206379Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscReg(Cause); 5216379Sgblack@eecs.umich.edu cause.ce = coProcID; 5226379Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(Cause, cause); 5234661Sksewell@umich.edu 5246378Sgblack@eecs.umich.edu Addr HandlerBase; 5256378Sgblack@eecs.umich.edu // Offset 0x180 - General Exception Vector 5266379Sgblack@eecs.umich.edu HandlerBase = vect() + tc->readMiscReg(EBase); 5276378Sgblack@eecs.umich.edu setHandlerPC(HandlerBase, tc); 5284661Sksewell@umich.edu 5295222Sksewell@umich.edu#else 5305224Sksewell@umich.edu warn("%s (CP%d) encountered.\n", name(), coProcID); 5315222Sksewell@umich.edu#endif 5324661Sksewell@umich.edu} 5334661Sksewell@umich.edu 5342447SN/A} // namespace MipsISA 5352447SN/A 536