faults.cc revision 5268
12131SN/A/* 25268Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 52131SN/A * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 162131SN/A * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 295254Sksewell@umich.edu * Authors: Gabe Black 305254Sksewell@umich.edu * Korey Sewell 315222Sksewell@umich.edu * Jaidev Patwardhan 322131SN/A */ 332131SN/A 342239SN/A#include "arch/mips/faults.hh" 352680Sktlim@umich.edu#include "cpu/thread_context.hh" 362447SN/A#include "cpu/base.hh" 372447SN/A#include "base/trace.hh" 385222Sksewell@umich.edu#include "arch/mips/pra_constants.hh" 392800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM 402800Ssaidi@eecs.umich.edu#include "sim/process.hh" 412800Ssaidi@eecs.umich.edu#include "mem/page_table.hh" 422800Ssaidi@eecs.umich.edu#endif 432131SN/A 442447SN/Anamespace MipsISA 452447SN/A{ 462131SN/A 472479SN/AFaultName MachineCheckFault::_name = "Machine Check"; 482447SN/AFaultVect MachineCheckFault::_vect = 0x0401; 492447SN/AFaultStat MachineCheckFault::_count; 502131SN/A 512479SN/AFaultName AlignmentFault::_name = "Alignment"; 522447SN/AFaultVect AlignmentFault::_vect = 0x0301; 532447SN/AFaultStat AlignmentFault::_count; 542447SN/A 555224Sksewell@umich.eduFaultName ResetFault::_name = "Reset Fault"; 565222Sksewell@umich.edu#if FULL_SYSTEM 575222Sksewell@umich.eduFaultVect ResetFault::_vect = 0xBFC00000; 585222Sksewell@umich.edu#else 595222Sksewell@umich.eduFaultVect ResetFault::_vect = 0x001; 605222Sksewell@umich.edu#endif 612447SN/AFaultStat ResetFault::_count; 622447SN/A 635222Sksewell@umich.eduFaultName AddressErrorFault::_name = "Address Error"; 645222Sksewell@umich.eduFaultVect AddressErrorFault::_vect = 0x0180; 655222Sksewell@umich.eduFaultStat AddressErrorFault::_count; 665222Sksewell@umich.edu 675222Sksewell@umich.eduFaultName StoreAddressErrorFault::_name = "Store Address Error"; 685222Sksewell@umich.eduFaultVect StoreAddressErrorFault::_vect = 0x0180; 695222Sksewell@umich.eduFaultStat StoreAddressErrorFault::_count; 705222Sksewell@umich.edu 715222Sksewell@umich.edu 725222Sksewell@umich.eduFaultName SystemCallFault::_name = "Syscall"; 735222Sksewell@umich.eduFaultVect SystemCallFault::_vect = 0x0180; 745222Sksewell@umich.eduFaultStat SystemCallFault::_count; 755222Sksewell@umich.edu 765224Sksewell@umich.eduFaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable Fault"; 775222Sksewell@umich.eduFaultVect CoprocessorUnusableFault::_vect = 0x180; 784661Sksewell@umich.eduFaultStat CoprocessorUnusableFault::_count; 794661Sksewell@umich.edu 805224Sksewell@umich.eduFaultName ReservedInstructionFault::_name = "Reserved Instruction Fault"; 815222Sksewell@umich.eduFaultVect ReservedInstructionFault::_vect = 0x0180; 824661Sksewell@umich.eduFaultStat ReservedInstructionFault::_count; 834661Sksewell@umich.edu 845224Sksewell@umich.eduFaultName ThreadFault::_name = "Thread Fault"; 854661Sksewell@umich.eduFaultVect ThreadFault::_vect = 0x00F1; 864661Sksewell@umich.eduFaultStat ThreadFault::_count; 874661Sksewell@umich.edu 884661Sksewell@umich.edu 895222Sksewell@umich.eduFaultName ArithmeticFault::_name = "Arithmetic Overflow Exception"; 905222Sksewell@umich.eduFaultVect ArithmeticFault::_vect = 0x180; 912447SN/AFaultStat ArithmeticFault::_count; 922447SN/A 934661Sksewell@umich.eduFaultName UnimplementedOpcodeFault::_name = "opdec"; 944661Sksewell@umich.eduFaultVect UnimplementedOpcodeFault::_vect = 0x0481; 954661Sksewell@umich.eduFaultStat UnimplementedOpcodeFault::_count; 964661Sksewell@umich.edu 972447SN/AFaultName InterruptFault::_name = "interrupt"; 985222Sksewell@umich.eduFaultVect InterruptFault::_vect = 0x0180; 992447SN/AFaultStat InterruptFault::_count; 1002447SN/A 1015222Sksewell@umich.eduFaultName TrapFault::_name = "Trap"; 1025222Sksewell@umich.eduFaultVect TrapFault::_vect = 0x0180; 1035222Sksewell@umich.eduFaultStat TrapFault::_count; 1045222Sksewell@umich.edu 1055222Sksewell@umich.eduFaultName BreakpointFault::_name = "Breakpoint"; 1065222Sksewell@umich.eduFaultVect BreakpointFault::_vect = 0x0180; 1075222Sksewell@umich.eduFaultStat BreakpointFault::_count; 1085222Sksewell@umich.edu 1095222Sksewell@umich.edu 1105222Sksewell@umich.eduFaultName ItbInvalidFault::_name = "Invalid TLB Entry Exception (I-Fetch/LW)"; 1115222Sksewell@umich.eduFaultVect ItbInvalidFault::_vect = 0x0180; 1125222Sksewell@umich.eduFaultStat ItbInvalidFault::_count; 1135222Sksewell@umich.edu 1145222Sksewell@umich.eduFaultName ItbPageFault::_name = "itbmiss"; 1155222Sksewell@umich.eduFaultVect ItbPageFault::_vect = 0x0181; 1165222Sksewell@umich.eduFaultStat ItbPageFault::_count; 1175222Sksewell@umich.edu 1185222Sksewell@umich.eduFaultName ItbMissFault::_name = "itbmiss"; 1195222Sksewell@umich.eduFaultVect ItbMissFault::_vect = 0x0181; 1205222Sksewell@umich.eduFaultStat ItbMissFault::_count; 1215222Sksewell@umich.edu 1225222Sksewell@umich.eduFaultName ItbAcvFault::_name = "iaccvio"; 1235222Sksewell@umich.eduFaultVect ItbAcvFault::_vect = 0x0081; 1245222Sksewell@umich.eduFaultStat ItbAcvFault::_count; 1255222Sksewell@umich.edu 1265222Sksewell@umich.eduFaultName ItbRefillFault::_name = "TLB Refill Exception (I-Fetch/LW)"; 1275222Sksewell@umich.eduFaultVect ItbRefillFault::_vect = 0x0180; 1285222Sksewell@umich.eduFaultStat ItbRefillFault::_count; 1295222Sksewell@umich.edu 1302447SN/AFaultName NDtbMissFault::_name = "dtb_miss_single"; 1312447SN/AFaultVect NDtbMissFault::_vect = 0x0201; 1322447SN/AFaultStat NDtbMissFault::_count; 1332447SN/A 1342447SN/AFaultName PDtbMissFault::_name = "dtb_miss_double"; 1352447SN/AFaultVect PDtbMissFault::_vect = 0x0281; 1362447SN/AFaultStat PDtbMissFault::_count; 1372447SN/A 1382447SN/AFaultName DtbPageFault::_name = "dfault"; 1392447SN/AFaultVect DtbPageFault::_vect = 0x0381; 1402447SN/AFaultStat DtbPageFault::_count; 1412447SN/A 1422447SN/AFaultName DtbAcvFault::_name = "dfault"; 1432447SN/AFaultVect DtbAcvFault::_vect = 0x0381; 1442447SN/AFaultStat DtbAcvFault::_count; 1452447SN/A 1465222Sksewell@umich.eduFaultName DtbInvalidFault::_name = "Invalid TLB Entry Exception (Store)"; 1475222Sksewell@umich.eduFaultVect DtbInvalidFault::_vect = 0x0180; 1485222Sksewell@umich.eduFaultStat DtbInvalidFault::_count; 1492447SN/A 1505222Sksewell@umich.eduFaultName DtbRefillFault::_name = "TLB Refill Exception (Store)"; 1515222Sksewell@umich.eduFaultVect DtbRefillFault::_vect = 0x0180; 1525222Sksewell@umich.eduFaultStat DtbRefillFault::_count; 1532447SN/A 1545222Sksewell@umich.eduFaultName TLBModifiedFault::_name = "TLB Modified Exception"; 1555222Sksewell@umich.eduFaultVect TLBModifiedFault::_vect = 0x0180; 1565222Sksewell@umich.eduFaultStat TLBModifiedFault::_count; 1572447SN/A 1585222Sksewell@umich.eduFaultName FloatEnableFault::_name = "float_enable_fault"; 1592447SN/AFaultVect FloatEnableFault::_vect = 0x0581; 1602447SN/AFaultStat FloatEnableFault::_count; 1612447SN/A 1625222Sksewell@umich.eduFaultName IntegerOverflowFault::_name = "Integer Overflow Fault"; 1632447SN/AFaultVect IntegerOverflowFault::_vect = 0x0501; 1642447SN/AFaultStat IntegerOverflowFault::_count; 1652447SN/A 1665222Sksewell@umich.eduFaultName DspStateDisabledFault::_name = "DSP Disabled Fault"; 1674661Sksewell@umich.eduFaultVect DspStateDisabledFault::_vect = 0x001a; 1684661Sksewell@umich.eduFaultStat DspStateDisabledFault::_count; 1694661Sksewell@umich.edu 1705222Sksewell@umich.edu#if FULL_SYSTEM 1715222Sksewell@umich.eduvoid MipsFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc) 1725222Sksewell@umich.edu{ 1735222Sksewell@umich.edu tc->setPC(HandlerBase); 1745222Sksewell@umich.edu tc->setNextPC(HandlerBase+sizeof(MachInst)); 1755222Sksewell@umich.edu tc->setNextNPC(HandlerBase+2*sizeof(MachInst)); 1765222Sksewell@umich.edu} 1775222Sksewell@umich.edu 1785222Sksewell@umich.eduvoid MipsFault::setExceptionState(ThreadContext *tc,uint8_t ExcCode) 1795222Sksewell@umich.edu{ 1805222Sksewell@umich.edu // modify SRS Ctl - Save CSS, put ESS into CSS 1815222Sksewell@umich.edu MiscReg stat = tc->readMiscReg(MipsISA::Status); 1825222Sksewell@umich.edu if(bits(stat,Status_EXL) != 1 && bits(stat,Status_BEV) != 1) 1835222Sksewell@umich.edu { 1845222Sksewell@umich.edu // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 1855222Sksewell@umich.edu MiscReg srs = tc->readMiscReg(MipsISA::SRSCtl); 1865222Sksewell@umich.edu uint8_t CSS,ESS; 1875222Sksewell@umich.edu CSS = bits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO); 1885222Sksewell@umich.edu ESS = bits(srs,SRSCtl_ESS_HI,SRSCtl_ESS_LO); 1895222Sksewell@umich.edu // Move CSS to PSS 1905222Sksewell@umich.edu replaceBits(srs,SRSCtl_PSS_HI,SRSCtl_PSS_LO,CSS); 1915222Sksewell@umich.edu // Move ESS to CSS 1925222Sksewell@umich.edu replaceBits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO,ESS); 1935222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::SRSCtl,srs); 1945250Sksewell@umich.edu //tc->setShadowSet(ESS); 1955222Sksewell@umich.edu } 1965222Sksewell@umich.edu 1975222Sksewell@umich.edu // set EXL bit (don't care if it is already set!) 1985222Sksewell@umich.edu replaceBits(stat,Status_EXL_HI,Status_EXL_LO,1); 1995222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::Status,stat); 2005222Sksewell@umich.edu 2015222Sksewell@umich.edu // write EPC 2025222Sksewell@umich.edu // warn("Set EPC to %x\n",tc->readPC()); 2035222Sksewell@umich.edu // CHECK ME or FIXME or FIX ME or POSSIBLE HACK 2045222Sksewell@umich.edu // Check to see if the exception occurred in the branch delay slot 2055222Sksewell@umich.edu DPRINTF(MipsPRA,"PC: %x, NextPC: %x, NNPC: %x\n",tc->readPC(),tc->readNextPC(),tc->readNextNPC()); 2065222Sksewell@umich.edu int C_BD=0; 2075222Sksewell@umich.edu if(tc->readPC() + sizeof(MachInst) != tc->readNextPC()){ 2085222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::EPC,tc->readPC()-sizeof(MachInst)); 2095222Sksewell@umich.edu // In the branch delay slot? set CAUSE_31 2105222Sksewell@umich.edu C_BD = 1; 2115222Sksewell@umich.edu } else { 2125222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::EPC,tc->readPC()); 2135222Sksewell@umich.edu // In the branch delay slot? reset CAUSE_31 2145222Sksewell@umich.edu C_BD = 0; 2155222Sksewell@umich.edu } 2165222Sksewell@umich.edu 2175222Sksewell@umich.edu // Set Cause_EXCCODE field 2185222Sksewell@umich.edu MiscReg cause = tc->readMiscReg(MipsISA::Cause); 2195222Sksewell@umich.edu replaceBits(cause,Cause_EXCCODE_HI,Cause_EXCCODE_LO,ExcCode); 2205222Sksewell@umich.edu replaceBits(cause,Cause_BD_HI,Cause_BD_LO,C_BD); 2215222Sksewell@umich.edu replaceBits(cause,Cause_CE_HI,Cause_CE_LO,0); 2225222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::Cause,cause); 2235222Sksewell@umich.edu 2245222Sksewell@umich.edu} 2255222Sksewell@umich.edu 2265222Sksewell@umich.eduvoid ArithmeticFault::invoke(ThreadContext *tc) 2275222Sksewell@umich.edu{ 2285222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 2295222Sksewell@umich.edu setExceptionState(tc,0xC); 2305222Sksewell@umich.edu 2315222Sksewell@umich.edu // Set new PC 2325222Sksewell@umich.edu Addr HandlerBase; 2335222Sksewell@umich.edu MiscReg stat = tc->readMiscReg(MipsISA::Status); 2345222Sksewell@umich.edu // Here, the handler is dependent on BEV, which is not modified by setExceptionState() 2355222Sksewell@umich.edu if(bits(stat,Status_BEV)==0){ // See MIPS ARM Vol 3, Revision 2, Page 38 2365222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); 2375222Sksewell@umich.edu }else{ 2385222Sksewell@umich.edu HandlerBase = 0xBFC00200; 2395222Sksewell@umich.edu } 2405222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 2415222Sksewell@umich.edu // warn("Exception Handler At: %x \n",HandlerBase); 2425222Sksewell@umich.edu} 2435222Sksewell@umich.edu 2445222Sksewell@umich.eduvoid StoreAddressErrorFault::invoke(ThreadContext *tc) 2455222Sksewell@umich.edu{ 2465222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 2475222Sksewell@umich.edu setExceptionState(tc,0x5); 2485222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr); 2495222Sksewell@umich.edu 2505222Sksewell@umich.edu // Set new PC 2515222Sksewell@umich.edu Addr HandlerBase; 2525222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector 2535222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 2545222Sksewell@umich.edu // warn("Exception Handler At: %x \n",HandlerBase); 2555222Sksewell@umich.edu // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC)); 2565222Sksewell@umich.edu 2575222Sksewell@umich.edu} 2585222Sksewell@umich.edu 2595222Sksewell@umich.eduvoid TrapFault::invoke(ThreadContext *tc) 2605222Sksewell@umich.edu{ 2615222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 2625222Sksewell@umich.edu // warn("%s encountered.\n", name()); 2635222Sksewell@umich.edu setExceptionState(tc,0xD); 2645222Sksewell@umich.edu 2655222Sksewell@umich.edu // Set new PC 2665222Sksewell@umich.edu Addr HandlerBase; 2675222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector 2685222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 2695222Sksewell@umich.edu // warn("Exception Handler At: %x \n",HandlerBase); 2705222Sksewell@umich.edu // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC)); 2715222Sksewell@umich.edu} 2725222Sksewell@umich.edu 2735222Sksewell@umich.eduvoid BreakpointFault::invoke(ThreadContext *tc) 2745222Sksewell@umich.edu{ 2755222Sksewell@umich.edu setExceptionState(tc,0x9); 2765222Sksewell@umich.edu 2775222Sksewell@umich.edu // Set new PC 2785222Sksewell@umich.edu Addr HandlerBase; 2795222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector 2805222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 2815222Sksewell@umich.edu // warn("Exception Handler At: %x \n",HandlerBase); 2825222Sksewell@umich.edu // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC)); 2835222Sksewell@umich.edu 2845222Sksewell@umich.edu} 2855222Sksewell@umich.edu 2865222Sksewell@umich.eduvoid DtbInvalidFault::invoke(ThreadContext *tc) 2875222Sksewell@umich.edu{ 2885222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 2895222Sksewell@umich.edu // warn("%s encountered.\n", name()); 2905222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr); 2915222Sksewell@umich.edu MiscReg eh = tc->readMiscReg(MipsISA::EntryHi); 2925222Sksewell@umich.edu replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid); 2935222Sksewell@umich.edu replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2); 2945222Sksewell@umich.edu replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X); 2955222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::EntryHi,eh); 2965222Sksewell@umich.edu MiscReg ctxt = tc->readMiscReg(MipsISA::Context); 2975222Sksewell@umich.edu replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2); 2985222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::Context,ctxt); 2995222Sksewell@umich.edu setExceptionState(tc,0x3); 3005222Sksewell@umich.edu 3015222Sksewell@umich.edu 3025222Sksewell@umich.edu // Set new PC 3035222Sksewell@umich.edu Addr HandlerBase; 3045222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector 3055222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 3065222Sksewell@umich.edu // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC)); 3075222Sksewell@umich.edu} 3085222Sksewell@umich.edu 3095222Sksewell@umich.eduvoid AddressErrorFault::invoke(ThreadContext *tc) 3105222Sksewell@umich.edu{ 3115222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 3125222Sksewell@umich.edu setExceptionState(tc,0x4); 3135222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr); 3145222Sksewell@umich.edu 3155222Sksewell@umich.edu // Set new PC 3165222Sksewell@umich.edu Addr HandlerBase; 3175222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector 3185222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 3195222Sksewell@umich.edu} 3205222Sksewell@umich.edu 3215222Sksewell@umich.eduvoid ItbInvalidFault::invoke(ThreadContext *tc) 3225222Sksewell@umich.edu{ 3235222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 3245222Sksewell@umich.edu setExceptionState(tc,0x2); 3255222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr); 3265222Sksewell@umich.edu MiscReg eh = tc->readMiscReg(MipsISA::EntryHi); 3275222Sksewell@umich.edu replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid); 3285222Sksewell@umich.edu replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2); 3295222Sksewell@umich.edu replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X); 3305222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::EntryHi,eh); 3315222Sksewell@umich.edu MiscReg ctxt = tc->readMiscReg(MipsISA::Context); 3325222Sksewell@umich.edu replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2); 3335222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::Context,ctxt); 3345222Sksewell@umich.edu 3355222Sksewell@umich.edu 3365222Sksewell@umich.edu // Set new PC 3375222Sksewell@umich.edu Addr HandlerBase; 3385222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector 3395222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 3405222Sksewell@umich.edu DPRINTF(MipsPRA,"Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC)); 3415222Sksewell@umich.edu} 3425222Sksewell@umich.edu 3435222Sksewell@umich.eduvoid ItbRefillFault::invoke(ThreadContext *tc) 3445222Sksewell@umich.edu{ 3455222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered (%x).\n", name(),BadVAddr); 3465222Sksewell@umich.edu Addr HandlerBase; 3475222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr); 3485222Sksewell@umich.edu MiscReg eh = tc->readMiscReg(MipsISA::EntryHi); 3495222Sksewell@umich.edu replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid); 3505222Sksewell@umich.edu replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2); 3515222Sksewell@umich.edu replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X); 3525222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::EntryHi,eh); 3535222Sksewell@umich.edu MiscReg ctxt = tc->readMiscReg(MipsISA::Context); 3545222Sksewell@umich.edu replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2); 3555222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::Context,ctxt); 3565222Sksewell@umich.edu 3575222Sksewell@umich.edu MiscReg stat = tc->readMiscReg(MipsISA::Status); 3585222Sksewell@umich.edu // Since handler depends on EXL bit, must check EXL bit before setting it!! 3595222Sksewell@umich.edu if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38 3605222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector 3615222Sksewell@umich.edu }else{ 3625222Sksewell@umich.edu HandlerBase = tc->readMiscReg(MipsISA::EBase); // Offset 0x000 3635222Sksewell@umich.edu } 3645222Sksewell@umich.edu 3655222Sksewell@umich.edu setExceptionState(tc,0x2); 3665222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 3675222Sksewell@umich.edu} 3685222Sksewell@umich.edu 3695222Sksewell@umich.eduvoid DtbRefillFault::invoke(ThreadContext *tc) 3705222Sksewell@umich.edu{ 3715222Sksewell@umich.edu // Set new PC 3725222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 3735222Sksewell@umich.edu Addr HandlerBase; 3745222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr); 3755222Sksewell@umich.edu MiscReg eh = tc->readMiscReg(MipsISA::EntryHi); 3765222Sksewell@umich.edu replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid); 3775222Sksewell@umich.edu replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2); 3785222Sksewell@umich.edu replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X); 3795222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::EntryHi,eh); 3805222Sksewell@umich.edu MiscReg ctxt = tc->readMiscReg(MipsISA::Context); 3815222Sksewell@umich.edu replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2); 3825222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::Context,ctxt); 3835222Sksewell@umich.edu 3845222Sksewell@umich.edu MiscReg stat = tc->readMiscReg(MipsISA::Status); 3855222Sksewell@umich.edu // Since handler depends on EXL bit, must check EXL bit before setting it!! 3865222Sksewell@umich.edu if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38 3875222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector 3885222Sksewell@umich.edu }else{ 3895222Sksewell@umich.edu HandlerBase = tc->readMiscReg(MipsISA::EBase); // Offset 0x000 3905222Sksewell@umich.edu } 3915222Sksewell@umich.edu 3925222Sksewell@umich.edu 3935222Sksewell@umich.edu setExceptionState(tc,0x3); 3945222Sksewell@umich.edu 3955222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 3965222Sksewell@umich.edu} 3975222Sksewell@umich.edu 3985222Sksewell@umich.eduvoid TLBModifiedFault::invoke(ThreadContext *tc) 3995222Sksewell@umich.edu{ 4005222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 4015222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr); 4025222Sksewell@umich.edu MiscReg eh = tc->readMiscReg(MipsISA::EntryHi); 4035222Sksewell@umich.edu replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid); 4045222Sksewell@umich.edu replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2); 4055222Sksewell@umich.edu replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X); 4065222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::EntryHi,eh); 4075222Sksewell@umich.edu MiscReg ctxt = tc->readMiscReg(MipsISA::Context); 4085222Sksewell@umich.edu replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2); 4095222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::Context,ctxt); 4105222Sksewell@umich.edu 4115222Sksewell@umich.edu // Set new PC 4125222Sksewell@umich.edu Addr HandlerBase; 4135222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector 4145222Sksewell@umich.edu setExceptionState(tc,0x1); 4155222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 4165222Sksewell@umich.edu // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC)); 4175222Sksewell@umich.edu 4185222Sksewell@umich.edu} 4195222Sksewell@umich.edu 4205222Sksewell@umich.eduvoid SystemCallFault::invoke(ThreadContext *tc) 4215222Sksewell@umich.edu{ 4225222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 4235222Sksewell@umich.edu setExceptionState(tc,0x8); 4245222Sksewell@umich.edu 4255222Sksewell@umich.edu // Set new PC 4265222Sksewell@umich.edu Addr HandlerBase; 4275222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector 4285222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 4295222Sksewell@umich.edu // warn("Exception Handler At: %x \n",HandlerBase); 4305222Sksewell@umich.edu // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC)); 4315222Sksewell@umich.edu 4325222Sksewell@umich.edu} 4335222Sksewell@umich.edu 4345222Sksewell@umich.eduvoid InterruptFault::invoke(ThreadContext *tc) 4355222Sksewell@umich.edu{ 4365222Sksewell@umich.edu#if FULL_SYSTEM 4375222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 4385222Sksewell@umich.edu //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil 4395222Sksewell@umich.edu setExceptionState(tc,0x0A); 4405222Sksewell@umich.edu Addr HandlerBase; 4415222Sksewell@umich.edu 4425222Sksewell@umich.edu 4435222Sksewell@umich.edu uint8_t IV = bits(tc->readMiscRegNoEffect(MipsISA::Cause),Cause_IV); 4445222Sksewell@umich.edu if (IV)// Offset 200 for release 2 4455222Sksewell@umich.edu HandlerBase= 0x20 + vect() + tc->readMiscRegNoEffect(MipsISA::EBase); 4465222Sksewell@umich.edu else//Ofset at 180 for release 1 4475222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase); 4485222Sksewell@umich.edu 4495222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 4505222Sksewell@umich.edu#endif 4515222Sksewell@umich.edu} 4525222Sksewell@umich.edu 4535222Sksewell@umich.edu#endif // FULL_SYSTEM 4545222Sksewell@umich.edu 4554661Sksewell@umich.eduvoid ResetFault::invoke(ThreadContext *tc) 4564661Sksewell@umich.edu{ 4575224Sksewell@umich.edu#if FULL_SYSTEM 4585222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 4595222Sksewell@umich.edu /* All reset activity must be invoked from here */ 4605222Sksewell@umich.edu tc->setPC(vect()); 4615222Sksewell@umich.edu tc->setNextPC(vect()+sizeof(MachInst)); 4625222Sksewell@umich.edu tc->setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst)); 4635222Sksewell@umich.edu DPRINTF(MipsPRA,"(%x) - ResetFault::invoke : PC set to %x",(unsigned)tc,(unsigned)tc->readPC()); 4645224Sksewell@umich.edu#endif 4655224Sksewell@umich.edu 4665224Sksewell@umich.edu // Set Coprocessor 1 (Floating Point) To Usable 4675224Sksewell@umich.edu tc->setMiscReg(MipsISA::Status, MipsISA::Status | 0x20000000); 4685222Sksewell@umich.edu} 4695222Sksewell@umich.edu 4705222Sksewell@umich.eduvoid ReservedInstructionFault::invoke(ThreadContext *tc) 4715222Sksewell@umich.edu{ 4725222Sksewell@umich.edu#if FULL_SYSTEM 4735222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 4745222Sksewell@umich.edu //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil 4755222Sksewell@umich.edu setExceptionState(tc,0x0A); 4765222Sksewell@umich.edu Addr HandlerBase; 4775222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase); // Offset 0x180 - General Exception Vector 4785222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 4795222Sksewell@umich.edu#else 4805222Sksewell@umich.edu panic("%s encountered.\n", name()); 4815222Sksewell@umich.edu#endif 4825222Sksewell@umich.edu} 4835222Sksewell@umich.edu 4845222Sksewell@umich.eduvoid ThreadFault::invoke(ThreadContext *tc) 4855222Sksewell@umich.edu{ 4865222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 4875222Sksewell@umich.edu panic("%s encountered.\n", name()); 4885222Sksewell@umich.edu} 4895222Sksewell@umich.edu 4905222Sksewell@umich.eduvoid DspStateDisabledFault::invoke(ThreadContext *tc) 4915222Sksewell@umich.edu{ 4925222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 4935222Sksewell@umich.edu panic("%s encountered.\n", name()); 4944661Sksewell@umich.edu} 4954661Sksewell@umich.edu 4964661Sksewell@umich.eduvoid CoprocessorUnusableFault::invoke(ThreadContext *tc) 4974661Sksewell@umich.edu{ 4985222Sksewell@umich.edu#if FULL_SYSTEM 4995222Sksewell@umich.edu DPRINTF(MipsPRA,"%s encountered.\n", name()); 5005222Sksewell@umich.edu setExceptionState(tc,0xb); 5015222Sksewell@umich.edu /* The ID of the coprocessor causing the exception is stored in CoprocessorUnusableFault::coProcID */ 5025222Sksewell@umich.edu MiscReg cause = tc->readMiscReg(MipsISA::Cause); 5035222Sksewell@umich.edu replaceBits(cause,Cause_CE_HI,Cause_CE_LO,coProcID); 5045222Sksewell@umich.edu tc->setMiscRegNoEffect(MipsISA::Cause,cause); 5054661Sksewell@umich.edu 5065222Sksewell@umich.edu Addr HandlerBase; 5075222Sksewell@umich.edu HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector 5085222Sksewell@umich.edu setHandlerPC(HandlerBase,tc); 5094661Sksewell@umich.edu 5105222Sksewell@umich.edu // warn("Status: %x, Cause: %x\n",tc->readMiscReg(MipsISA::Status),tc->readMiscReg(MipsISA::Cause)); 5115222Sksewell@umich.edu#else 5125224Sksewell@umich.edu warn("%s (CP%d) encountered.\n", name(), coProcID); 5135222Sksewell@umich.edu#endif 5144661Sksewell@umich.edu} 5154661Sksewell@umich.edu 5162447SN/A} // namespace MipsISA 5172447SN/A 518