faults.cc revision 4661
11736SN/A/* 27778Sgblack@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 31736SN/A * All rights reserved. 41736SN/A * 51736SN/A * Redistribution and use in source and binary forms, with or without 61736SN/A * modification, are permitted provided that the following conditions are 71736SN/A * met: redistributions of source code must retain the above copyright 81736SN/A * notice, this list of conditions and the following disclaimer; 91736SN/A * redistributions in binary form must reproduce the above copyright 101736SN/A * notice, this list of conditions and the following disclaimer in the 111736SN/A * documentation and/or other materials provided with the distribution; 121736SN/A * neither the name of the copyright holders nor the names of its 131736SN/A * contributors may be used to endorse or promote products derived from 141736SN/A * this software without specific prior written permission. 151736SN/A * 161736SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171736SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181736SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191736SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201736SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211736SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221736SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231736SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241736SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251736SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261736SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Gabe Black 297778Sgblack@eecs.umich.edu * Korey Sewell 301736SN/A */ 311519SN/A 321519SN/A#include "arch/mips/faults.hh" 331519SN/A#include "cpu/thread_context.hh" 341519SN/A#include "cpu/base.hh" 351519SN/A#include "base/trace.hh" 361519SN/A 371519SN/A#if !FULL_SYSTEM 381519SN/A#include "sim/process.hh" 391519SN/A#include "mem/page_table.hh" 401519SN/A#endif 411519SN/A 421519SN/Anamespace MipsISA 431519SN/A{ 441519SN/A 451519SN/AFaultName MachineCheckFault::_name = "Machine Check"; 461519SN/AFaultVect MachineCheckFault::_vect = 0x0401; 471519SN/AFaultStat MachineCheckFault::_count; 481519SN/A 491519SN/AFaultName AlignmentFault::_name = "Alignment"; 501519SN/AFaultVect AlignmentFault::_vect = 0x0301; 511519SN/AFaultStat AlignmentFault::_count; 521519SN/A 531519SN/AFaultName ResetFault::_name = "reset"; 541519SN/AFaultVect ResetFault::_vect = 0x0001; 551606SN/AFaultStat ResetFault::_count; 561519SN/A 571606SN/AFaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable"; 581606SN/AFaultVect CoprocessorUnusableFault::_vect = 0xF001; 591606SN/AFaultStat CoprocessorUnusableFault::_count; 601606SN/A 611519SN/AFaultName ReservedInstructionFault::_name = "Reserved Instruction"; 621606SN/AFaultVect ReservedInstructionFault::_vect = 0x0F01; 631519SN/AFaultStat ReservedInstructionFault::_count; 641606SN/A 651519SN/AFaultName ThreadFault::_name = "thread"; 661606SN/AFaultVect ThreadFault::_vect = 0x00F1; 671519SN/AFaultStat ThreadFault::_count; 681606SN/A 691519SN/A 701606SN/AFaultName ArithmeticFault::_name = "arith"; 711519SN/AFaultVect ArithmeticFault::_vect = 0x0501; 721606SN/AFaultStat ArithmeticFault::_count; 731519SN/A 741606SN/AFaultName UnimplementedOpcodeFault::_name = "opdec"; 751519SN/AFaultVect UnimplementedOpcodeFault::_vect = 0x0481; 761606SN/AFaultStat UnimplementedOpcodeFault::_count; 771519SN/A 781606SN/A#if !FULL_SYSTEM 791519SN/A//FaultName PageTableFault::_name = "page_table_fault"; 801606SN/A//FaultVect PageTableFault::_vect = 0x0000; 811519SN/A//FaultStat PageTableFault::_count; 821606SN/A#endif 831519SN/A 841606SN/AFaultName InterruptFault::_name = "interrupt"; 851519SN/AFaultVect InterruptFault::_vect = 0x0101; 861606SN/AFaultStat InterruptFault::_count; 871519SN/A 881606SN/AFaultName NDtbMissFault::_name = "dtb_miss_single"; 891519SN/AFaultVect NDtbMissFault::_vect = 0x0201; 901606SN/AFaultStat NDtbMissFault::_count; 911519SN/A 921606SN/AFaultName PDtbMissFault::_name = "dtb_miss_double"; 931519SN/AFaultVect PDtbMissFault::_vect = 0x0281; 941606SN/AFaultStat PDtbMissFault::_count; 951606SN/A 961606SN/AFaultName DtbPageFault::_name = "dfault"; 971606SN/AFaultVect DtbPageFault::_vect = 0x0381; 981944SN/AFaultStat DtbPageFault::_count; 991606SN/A 1001606SN/AFaultName DtbAcvFault::_name = "dfault"; 1011519SN/AFaultVect DtbAcvFault::_vect = 0x0381; 1021606SN/AFaultStat DtbAcvFault::_count; 1031606SN/A 1041858SN/AFaultName ItbMissFault::_name = "itbmiss"; 1051858SN/AFaultVect ItbMissFault::_vect = 0x0181; 1061858SN/AFaultStat ItbMissFault::_count; 1071858SN/A 1081858SN/AFaultName ItbPageFault::_name = "itbmiss"; 1091606SN/AFaultVect ItbPageFault::_vect = 0x0181; 1101606SN/AFaultStat ItbPageFault::_count; 1111606SN/A 1121606SN/AFaultName ItbAcvFault::_name = "iaccvio"; 1131606SN/AFaultVect ItbAcvFault::_vect = 0x0081; 1141858SN/AFaultStat ItbAcvFault::_count; 1151858SN/A 1161858SN/AFaultName FloatEnableFault::_name = "fen"; 1171858SN/AFaultVect FloatEnableFault::_vect = 0x0581; 1181519SN/AFaultStat FloatEnableFault::_count; 1191589SN/A 1201519SN/AFaultName IntegerOverflowFault::_name = "intover"; 1211606SN/AFaultVect IntegerOverflowFault::_vect = 0x0501; 1221606SN/AFaultStat IntegerOverflowFault::_count; 1231606SN/A 1241606SN/AFaultName DspStateDisabledFault::_name = "intover"; 1251519SN/AFaultVect DspStateDisabledFault::_vect = 0x001a; 1261606SN/AFaultStat DspStateDisabledFault::_count; 1271519SN/A 1281606SN/A 1291519SN/A/*void PageTableFault::invoke(ThreadContext *tc) 1301606SN/A{ 1311519SN/A Process *p = tc->getProcessPtr(); 1321606SN/A 1331519SN/A Addr page_addr = p->pTable->pageAlign(vaddr); 1341606SN/A 1351519SN/A warn("%i: [tid:%i]: %s encountered @ addr %x. Allocating new page for address range %x - %x.\n", 1361589SN/A curTick, tc->getThreadNum(), name(), vaddr, page_addr, page_addr+VMPageSize); 1371519SN/A 1381606SN/A p->pTable->allocate(page_addr, VMPageSize); 1391606SN/A 1401606SN/A return; 1411606SN/A} 1421519SN/A*/ 1431606SN/A /* address is higher than the stack region or in the current stack region 1441519SN/A if (vaddr > p->stack_base || vaddr > p->stack_min) 1451606SN/A FaultBase::invoke(tc); 1461519SN/A 1471606SN/A // We've accessed the next page 1481519SN/A if (vaddr > p->stack_min - PageBytes) { 1491606SN/A p->stack_min -= PageBytes; 1501519SN/A if (p->stack_base - p->stack_min > 8*1024*1024) { 1511606SN/A warn("Already allocated Over max stack size for one thread\n"); 1521606SN/A } 1534167SN/A warn("%i: Allocating page for range %x - %x", 1541606SN/A curTick, p->stack_min, p->stack_min-PageBytes); 1551606SN/A 1561606SN/A p->pTable->allocate(p->stack_min, PageBytes); 1571606SN/A warn("Increasing stack size by one page."); 1581606SN/A } else { 1591606SN/A FaultBase::invoke(tc); 1601606SN/A }*/ 1611606SN/A 1621606SN/Avoid ResetFault::invoke(ThreadContext *tc) 1631606SN/A{ 1641606SN/A warn("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name()); 1651606SN/A //tc->getCpuPtr()->reset(); 1661606SN/A} 1671606SN/A 1681606SN/Avoid CoprocessorUnusableFault::invoke(ThreadContext *tc) 1691606SN/A{ 1701606SN/A panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name()); 1711606SN/A} 1721606SN/A 1731606SN/Avoid ReservedInstructionFault::invoke(ThreadContext *tc) 1741606SN/A{ 1754167SN/A panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name()); 1764167SN/A} 1774167SN/A 1784167SN/Avoid ThreadFault::invoke(ThreadContext *tc) 1794167SN/A{ 1804167SN/A panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name()); 1814167SN/A} 1824167SN/A 1834167SN/Avoid DspStateDisabledFault::invoke(ThreadContext *tc) 1844167SN/A{ 1854167SN/A panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name()); 1864167SN/A} 1874167SN/A 1884167SN/A} // namespace MipsISA 1894167SN/A 1904167SN/A