faults.cc revision 3573
113168Smatt.horsnell@arm.com/*
213168Smatt.horsnell@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan
313168Smatt.horsnell@arm.com * All rights reserved.
413168Smatt.horsnell@arm.com *
513168Smatt.horsnell@arm.com * Redistribution and use in source and binary forms, with or without
613168Smatt.horsnell@arm.com * modification, are permitted provided that the following conditions are
713168Smatt.horsnell@arm.com * met: redistributions of source code must retain the above copyright
813168Smatt.horsnell@arm.com * notice, this list of conditions and the following disclaimer;
913168Smatt.horsnell@arm.com * redistributions in binary form must reproduce the above copyright
1013168Smatt.horsnell@arm.com * notice, this list of conditions and the following disclaimer in the
1113168Smatt.horsnell@arm.com * documentation and/or other materials provided with the distribution;
1213168Smatt.horsnell@arm.com * neither the name of the copyright holders nor the names of its
1313168Smatt.horsnell@arm.com * contributors may be used to endorse or promote products derived from
1413168Smatt.horsnell@arm.com * this software without specific prior written permission.
1513168Smatt.horsnell@arm.com *
1613168Smatt.horsnell@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1713168Smatt.horsnell@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1813168Smatt.horsnell@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1913168Smatt.horsnell@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2013168Smatt.horsnell@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2113168Smatt.horsnell@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2213168Smatt.horsnell@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2313168Smatt.horsnell@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2413168Smatt.horsnell@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2513168Smatt.horsnell@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2613168Smatt.horsnell@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2713168Smatt.horsnell@arm.com *
2813168Smatt.horsnell@arm.com * Authors: Gabe Black
2913168Smatt.horsnell@arm.com *          Korey Sewell
3013168Smatt.horsnell@arm.com */
3113168Smatt.horsnell@arm.com
3213168Smatt.horsnell@arm.com#include "arch/mips/faults.hh"
3313168Smatt.horsnell@arm.com#include "cpu/thread_context.hh"
3413168Smatt.horsnell@arm.com#include "cpu/base.hh"
3513168Smatt.horsnell@arm.com#include "base/trace.hh"
3613168Smatt.horsnell@arm.com
3713168Smatt.horsnell@arm.com#if !FULL_SYSTEM
3813168Smatt.horsnell@arm.com#include "sim/process.hh"
3913168Smatt.horsnell@arm.com#include "mem/page_table.hh"
4013168Smatt.horsnell@arm.com#endif
4113168Smatt.horsnell@arm.com
4213168Smatt.horsnell@arm.comnamespace MipsISA
4313168Smatt.horsnell@arm.com{
4413168Smatt.horsnell@arm.com
4513168Smatt.horsnell@arm.comFaultName MachineCheckFault::_name = "Machine Check";
4613168Smatt.horsnell@arm.comFaultVect MachineCheckFault::_vect = 0x0401;
4713168Smatt.horsnell@arm.comFaultStat MachineCheckFault::_count;
4813168Smatt.horsnell@arm.com
4913168Smatt.horsnell@arm.comFaultName AlignmentFault::_name = "Alignment";
5013168Smatt.horsnell@arm.comFaultVect AlignmentFault::_vect = 0x0301;
5113168Smatt.horsnell@arm.comFaultStat AlignmentFault::_count;
5213168Smatt.horsnell@arm.com
5313544Sgabeblack@google.comFaultName ResetFault::_name = "reset";
5413168Smatt.horsnell@arm.comFaultVect ResetFault::_vect = 0x0001;
5513168Smatt.horsnell@arm.comFaultStat ResetFault::_count;
5613168Smatt.horsnell@arm.com
5713168Smatt.horsnell@arm.comFaultName ArithmeticFault::_name = "arith";
5813168Smatt.horsnell@arm.comFaultVect ArithmeticFault::_vect = 0x0501;
5913168Smatt.horsnell@arm.comFaultStat ArithmeticFault::_count;
6013168Smatt.horsnell@arm.com
6113168Smatt.horsnell@arm.com#if !FULL_SYSTEM
6213168Smatt.horsnell@arm.comFaultName PageTableFault::_name = "page_table_fault";
6313168Smatt.horsnell@arm.comFaultVect PageTableFault::_vect = 0x0000;
6413168Smatt.horsnell@arm.comFaultStat PageTableFault::_count;
6513168Smatt.horsnell@arm.com#endif
6613168Smatt.horsnell@arm.com
6713168Smatt.horsnell@arm.comFaultName InterruptFault::_name = "interrupt";
6813168Smatt.horsnell@arm.comFaultVect InterruptFault::_vect = 0x0101;
6913168Smatt.horsnell@arm.comFaultStat InterruptFault::_count;
70
71FaultName NDtbMissFault::_name = "dtb_miss_single";
72FaultVect NDtbMissFault::_vect = 0x0201;
73FaultStat NDtbMissFault::_count;
74
75FaultName PDtbMissFault::_name = "dtb_miss_double";
76FaultVect PDtbMissFault::_vect = 0x0281;
77FaultStat PDtbMissFault::_count;
78
79FaultName DtbPageFault::_name = "dfault";
80FaultVect DtbPageFault::_vect = 0x0381;
81FaultStat DtbPageFault::_count;
82
83FaultName DtbAcvFault::_name = "dfault";
84FaultVect DtbAcvFault::_vect = 0x0381;
85FaultStat DtbAcvFault::_count;
86
87FaultName ItbMissFault::_name = "itbmiss";
88FaultVect ItbMissFault::_vect = 0x0181;
89FaultStat ItbMissFault::_count;
90
91FaultName ItbPageFault::_name = "itbmiss";
92FaultVect ItbPageFault::_vect = 0x0181;
93FaultStat ItbPageFault::_count;
94
95FaultName ItbAcvFault::_name = "iaccvio";
96FaultVect ItbAcvFault::_vect = 0x0081;
97FaultStat ItbAcvFault::_count;
98
99FaultName UnimplementedOpcodeFault::_name = "opdec";
100FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
101FaultStat UnimplementedOpcodeFault::_count;
102
103FaultName FloatEnableFault::_name = "fen";
104FaultVect FloatEnableFault::_vect = 0x0581;
105FaultStat FloatEnableFault::_count;
106
107FaultName PalFault::_name = "pal";
108FaultVect PalFault::_vect = 0x2001;
109FaultStat PalFault::_count;
110
111FaultName IntegerOverflowFault::_name = "intover";
112FaultVect IntegerOverflowFault::_vect = 0x0501;
113FaultStat IntegerOverflowFault::_count;
114
115void PageTableFault::invoke(ThreadContext *tc)
116{
117    Process *p = tc->getProcessPtr();
118
119    // address is higher than the stack region or in the current stack region
120    if (vaddr > p->stack_base || vaddr > p->stack_min)
121        FaultBase::invoke(tc);
122
123    // We've accessed the next page
124    if (vaddr > p->stack_min - PageBytes) {
125        p->stack_min -= PageBytes;
126        if (p->stack_base - p->stack_min > 8*1024*1024)
127            fatal("Over max stack size for one thread\n");
128        p->pTable->allocate(p->stack_min, PageBytes);
129        warn("Increasing stack size by one page.");
130    } else {
131        FaultBase::invoke(tc);
132    }
133}
134
135} // namespace MipsISA
136
137